Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
49cec4d8 | 2 | /* |
9d3a15aa | 3 | * Faraday Technolog FTGPIO010 gpiochip and interrupt routines |
49cec4d8 LW |
4 | * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> |
5 | * | |
6 | * Based on arch/arm/mach-gemini/gpio.c: | |
7 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | |
8 | * | |
9 | * Based on plat-mxc/gpio.c: | |
10 | * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> | |
11 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
12 | */ | |
13 | #include <linux/gpio/driver.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/platform_device.h> | |
49cec4d8 | 17 | #include <linux/bitops.h> |
da02d794 | 18 | #include <linux/clk.h> |
49cec4d8 LW |
19 | |
20 | /* GPIO registers definition */ | |
21 | #define GPIO_DATA_OUT 0x00 | |
22 | #define GPIO_DATA_IN 0x04 | |
23 | #define GPIO_DIR 0x08 | |
69a87f29 | 24 | #define GPIO_BYPASS_IN 0x0C |
49cec4d8 LW |
25 | #define GPIO_DATA_SET 0x10 |
26 | #define GPIO_DATA_CLR 0x14 | |
27 | #define GPIO_PULL_EN 0x18 | |
28 | #define GPIO_PULL_TYPE 0x1C | |
29 | #define GPIO_INT_EN 0x20 | |
69a87f29 LW |
30 | #define GPIO_INT_STAT_RAW 0x24 |
31 | #define GPIO_INT_STAT_MASKED 0x28 | |
49cec4d8 LW |
32 | #define GPIO_INT_MASK 0x2C |
33 | #define GPIO_INT_CLR 0x30 | |
34 | #define GPIO_INT_TYPE 0x34 | |
35 | #define GPIO_INT_BOTH_EDGE 0x38 | |
36 | #define GPIO_INT_LEVEL 0x3C | |
37 | #define GPIO_DEBOUNCE_EN 0x40 | |
38 | #define GPIO_DEBOUNCE_PRESCALE 0x44 | |
39 | ||
40 | /** | |
9d3a15aa | 41 | * struct ftgpio_gpio - Gemini GPIO state container |
49cec4d8 LW |
42 | * @dev: containing device for this instance |
43 | * @gc: gpiochip for this instance | |
da02d794 LW |
44 | * @base: remapped I/O-memory base |
45 | * @clk: silicon clock | |
49cec4d8 | 46 | */ |
9d3a15aa | 47 | struct ftgpio_gpio { |
49cec4d8 LW |
48 | struct device *dev; |
49 | struct gpio_chip gc; | |
50 | void __iomem *base; | |
da02d794 | 51 | struct clk *clk; |
49cec4d8 LW |
52 | }; |
53 | ||
9d3a15aa | 54 | static void ftgpio_gpio_ack_irq(struct irq_data *d) |
49cec4d8 LW |
55 | { |
56 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
9d3a15aa | 57 | struct ftgpio_gpio *g = gpiochip_get_data(gc); |
49cec4d8 LW |
58 | |
59 | writel(BIT(irqd_to_hwirq(d)), g->base + GPIO_INT_CLR); | |
60 | } | |
61 | ||
9d3a15aa | 62 | static void ftgpio_gpio_mask_irq(struct irq_data *d) |
49cec4d8 LW |
63 | { |
64 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
9d3a15aa | 65 | struct ftgpio_gpio *g = gpiochip_get_data(gc); |
49cec4d8 LW |
66 | u32 val; |
67 | ||
68 | val = readl(g->base + GPIO_INT_EN); | |
69 | val &= ~BIT(irqd_to_hwirq(d)); | |
70 | writel(val, g->base + GPIO_INT_EN); | |
71 | } | |
72 | ||
9d3a15aa | 73 | static void ftgpio_gpio_unmask_irq(struct irq_data *d) |
49cec4d8 LW |
74 | { |
75 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
9d3a15aa | 76 | struct ftgpio_gpio *g = gpiochip_get_data(gc); |
49cec4d8 LW |
77 | u32 val; |
78 | ||
79 | val = readl(g->base + GPIO_INT_EN); | |
80 | val |= BIT(irqd_to_hwirq(d)); | |
81 | writel(val, g->base + GPIO_INT_EN); | |
82 | } | |
83 | ||
9d3a15aa | 84 | static int ftgpio_gpio_set_irq_type(struct irq_data *d, unsigned int type) |
49cec4d8 LW |
85 | { |
86 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
9d3a15aa | 87 | struct ftgpio_gpio *g = gpiochip_get_data(gc); |
49cec4d8 LW |
88 | u32 mask = BIT(irqd_to_hwirq(d)); |
89 | u32 reg_both, reg_level, reg_type; | |
90 | ||
91 | reg_type = readl(g->base + GPIO_INT_TYPE); | |
92 | reg_level = readl(g->base + GPIO_INT_LEVEL); | |
93 | reg_both = readl(g->base + GPIO_INT_BOTH_EDGE); | |
94 | ||
95 | switch (type) { | |
96 | case IRQ_TYPE_EDGE_BOTH: | |
97 | irq_set_handler_locked(d, handle_edge_irq); | |
98 | reg_type &= ~mask; | |
99 | reg_both |= mask; | |
100 | break; | |
101 | case IRQ_TYPE_EDGE_RISING: | |
102 | irq_set_handler_locked(d, handle_edge_irq); | |
103 | reg_type &= ~mask; | |
104 | reg_both &= ~mask; | |
105 | reg_level &= ~mask; | |
106 | break; | |
107 | case IRQ_TYPE_EDGE_FALLING: | |
108 | irq_set_handler_locked(d, handle_edge_irq); | |
109 | reg_type &= ~mask; | |
110 | reg_both &= ~mask; | |
111 | reg_level |= mask; | |
112 | break; | |
113 | case IRQ_TYPE_LEVEL_HIGH: | |
114 | irq_set_handler_locked(d, handle_level_irq); | |
115 | reg_type |= mask; | |
116 | reg_level &= ~mask; | |
117 | break; | |
118 | case IRQ_TYPE_LEVEL_LOW: | |
119 | irq_set_handler_locked(d, handle_level_irq); | |
120 | reg_type |= mask; | |
121 | reg_level |= mask; | |
122 | break; | |
123 | default: | |
124 | irq_set_handler_locked(d, handle_bad_irq); | |
125 | return -EINVAL; | |
126 | } | |
127 | ||
128 | writel(reg_type, g->base + GPIO_INT_TYPE); | |
129 | writel(reg_level, g->base + GPIO_INT_LEVEL); | |
130 | writel(reg_both, g->base + GPIO_INT_BOTH_EDGE); | |
131 | ||
9d3a15aa | 132 | ftgpio_gpio_ack_irq(d); |
49cec4d8 LW |
133 | |
134 | return 0; | |
135 | } | |
136 | ||
9d3a15aa LW |
137 | static struct irq_chip ftgpio_gpio_irqchip = { |
138 | .name = "FTGPIO010", | |
139 | .irq_ack = ftgpio_gpio_ack_irq, | |
140 | .irq_mask = ftgpio_gpio_mask_irq, | |
141 | .irq_unmask = ftgpio_gpio_unmask_irq, | |
142 | .irq_set_type = ftgpio_gpio_set_irq_type, | |
49cec4d8 LW |
143 | }; |
144 | ||
9d3a15aa | 145 | static void ftgpio_gpio_irq_handler(struct irq_desc *desc) |
49cec4d8 LW |
146 | { |
147 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); | |
9d3a15aa | 148 | struct ftgpio_gpio *g = gpiochip_get_data(gc); |
49cec4d8 LW |
149 | struct irq_chip *irqchip = irq_desc_get_chip(desc); |
150 | int offset; | |
151 | unsigned long stat; | |
152 | ||
153 | chained_irq_enter(irqchip, desc); | |
154 | ||
69a87f29 | 155 | stat = readl(g->base + GPIO_INT_STAT_RAW); |
49cec4d8 LW |
156 | if (stat) |
157 | for_each_set_bit(offset, &stat, gc->ngpio) | |
f0fbe7bc | 158 | generic_handle_irq(irq_find_mapping(gc->irq.domain, |
49cec4d8 LW |
159 | offset)); |
160 | ||
161 | chained_irq_exit(irqchip, desc); | |
162 | } | |
163 | ||
9d3a15aa | 164 | static int ftgpio_gpio_probe(struct platform_device *pdev) |
49cec4d8 LW |
165 | { |
166 | struct device *dev = &pdev->dev; | |
167 | struct resource *res; | |
9d3a15aa | 168 | struct ftgpio_gpio *g; |
49cec4d8 LW |
169 | int irq; |
170 | int ret; | |
171 | ||
172 | g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL); | |
173 | if (!g) | |
174 | return -ENOMEM; | |
175 | ||
176 | g->dev = dev; | |
177 | ||
178 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
179 | g->base = devm_ioremap_resource(dev, res); | |
180 | if (IS_ERR(g->base)) | |
181 | return PTR_ERR(g->base); | |
182 | ||
183 | irq = platform_get_irq(pdev, 0); | |
4070a534 AY |
184 | if (irq <= 0) |
185 | return irq ? irq : -EINVAL; | |
49cec4d8 | 186 | |
da02d794 LW |
187 | g->clk = devm_clk_get(dev, NULL); |
188 | if (!IS_ERR(g->clk)) { | |
189 | ret = clk_prepare_enable(g->clk); | |
190 | if (ret) | |
191 | return ret; | |
192 | } else if (PTR_ERR(g->clk) == -EPROBE_DEFER) { | |
193 | /* | |
194 | * Percolate deferrals, for anything else, | |
195 | * just live without the clocking. | |
196 | */ | |
197 | return PTR_ERR(g->clk); | |
198 | } | |
199 | ||
49cec4d8 LW |
200 | ret = bgpio_init(&g->gc, dev, 4, |
201 | g->base + GPIO_DATA_IN, | |
202 | g->base + GPIO_DATA_SET, | |
203 | g->base + GPIO_DATA_CLR, | |
204 | g->base + GPIO_DIR, | |
205 | NULL, | |
206 | 0); | |
207 | if (ret) { | |
208 | dev_err(dev, "unable to init generic GPIO\n"); | |
da02d794 | 209 | goto dis_clk; |
49cec4d8 | 210 | } |
9d3a15aa | 211 | g->gc.label = "FTGPIO010"; |
49cec4d8 LW |
212 | g->gc.base = -1; |
213 | g->gc.parent = dev; | |
214 | g->gc.owner = THIS_MODULE; | |
215 | /* ngpio is set by bgpio_init() */ | |
216 | ||
217 | ret = devm_gpiochip_add_data(dev, &g->gc, g); | |
218 | if (ret) | |
da02d794 | 219 | goto dis_clk; |
49cec4d8 LW |
220 | |
221 | /* Disable, unmask and clear all interrupts */ | |
222 | writel(0x0, g->base + GPIO_INT_EN); | |
223 | writel(0x0, g->base + GPIO_INT_MASK); | |
224 | writel(~0x0, g->base + GPIO_INT_CLR); | |
225 | ||
9d3a15aa | 226 | ret = gpiochip_irqchip_add(&g->gc, &ftgpio_gpio_irqchip, |
49cec4d8 LW |
227 | 0, handle_bad_irq, |
228 | IRQ_TYPE_NONE); | |
229 | if (ret) { | |
230 | dev_info(dev, "could not add irqchip\n"); | |
da02d794 | 231 | goto dis_clk; |
49cec4d8 | 232 | } |
9d3a15aa LW |
233 | gpiochip_set_chained_irqchip(&g->gc, &ftgpio_gpio_irqchip, |
234 | irq, ftgpio_gpio_irq_handler); | |
49cec4d8 | 235 | |
da02d794 | 236 | platform_set_drvdata(pdev, g); |
9d3a15aa | 237 | dev_info(dev, "FTGPIO010 @%p registered\n", g->base); |
49cec4d8 LW |
238 | |
239 | return 0; | |
da02d794 LW |
240 | |
241 | dis_clk: | |
242 | if (!IS_ERR(g->clk)) | |
243 | clk_disable_unprepare(g->clk); | |
244 | return ret; | |
245 | } | |
246 | ||
247 | static int ftgpio_gpio_remove(struct platform_device *pdev) | |
248 | { | |
249 | struct ftgpio_gpio *g = platform_get_drvdata(pdev); | |
250 | ||
251 | if (!IS_ERR(g->clk)) | |
252 | clk_disable_unprepare(g->clk); | |
253 | return 0; | |
49cec4d8 LW |
254 | } |
255 | ||
9d3a15aa | 256 | static const struct of_device_id ftgpio_gpio_of_match[] = { |
49cec4d8 LW |
257 | { |
258 | .compatible = "cortina,gemini-gpio", | |
259 | }, | |
9d3a15aa LW |
260 | { |
261 | .compatible = "moxa,moxart-gpio", | |
262 | }, | |
263 | { | |
264 | .compatible = "faraday,ftgpio010", | |
265 | }, | |
49cec4d8 LW |
266 | {}, |
267 | }; | |
268 | ||
9d3a15aa | 269 | static struct platform_driver ftgpio_gpio_driver = { |
49cec4d8 | 270 | .driver = { |
9d3a15aa LW |
271 | .name = "ftgpio010-gpio", |
272 | .of_match_table = of_match_ptr(ftgpio_gpio_of_match), | |
49cec4d8 | 273 | }, |
da02d794 LW |
274 | .probe = ftgpio_gpio_probe, |
275 | .remove = ftgpio_gpio_remove, | |
49cec4d8 | 276 | }; |
9d3a15aa | 277 | builtin_platform_driver(ftgpio_gpio_driver); |