[linux-2.6-block.git] / drivers / gpio / gpio-ftgpio010.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Faraday Technolog FTGPIO010 gpiochip and interrupt routines
 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
 *
 * Based on arch/arm/mach-gemini/gpio.c:
 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
 *
 * Based on plat-mxc/gpio.c:
 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 */
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/bitops.h>
#include <linux/clk.h>

/* GPIO registers definition */
#define GPIO_DATA_OUT		0x00
#define GPIO_DATA_IN		0x04
#define GPIO_DIR		0x08
#define GPIO_BYPASS_IN		0x0C
#define GPIO_DATA_SET		0x10
#define GPIO_DATA_CLR		0x14
#define GPIO_PULL_EN		0x18
#define GPIO_PULL_TYPE		0x1C
#define GPIO_INT_EN		0x20
#define GPIO_INT_STAT_RAW	0x24
#define GPIO_INT_STAT_MASKED	0x28
#define GPIO_INT_MASK		0x2C
#define GPIO_INT_CLR		0x30
#define GPIO_INT_TYPE		0x34
#define GPIO_INT_BOTH_EDGE	0x38
#define GPIO_INT_LEVEL		0x3C
#define GPIO_DEBOUNCE_EN	0x40
#define GPIO_DEBOUNCE_PRESCALE	0x44

/**
 * struct ftgpio_gpio - Gemini GPIO state container
 * @dev: containing device for this instance
 * @gc: gpiochip for this instance
 * @base: remapped I/O-memory base
 * @clk: silicon clock
 */
struct ftgpio_gpio {
	struct device *dev;
	struct gpio_chip gc;
	void __iomem *base;
	struct clk *clk;
};

static void ftgpio_gpio_ack_irq(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct ftgpio_gpio *g = gpiochip_get_data(gc);

	writel(BIT(irqd_to_hwirq(d)), g->base + GPIO_INT_CLR);
}

static void ftgpio_gpio_mask_irq(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct ftgpio_gpio *g = gpiochip_get_data(gc);
	u32 val;

	val = readl(g->base + GPIO_INT_EN);
	val &= ~BIT(irqd_to_hwirq(d));
	writel(val, g->base + GPIO_INT_EN);
}

static void ftgpio_gpio_unmask_irq(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct ftgpio_gpio *g = gpiochip_get_data(gc);
	u32 val;

	val = readl(g->base + GPIO_INT_EN);
	val |= BIT(irqd_to_hwirq(d));
	writel(val, g->base + GPIO_INT_EN);
}

static int ftgpio_gpio_set_irq_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct ftgpio_gpio *g = gpiochip_get_data(gc);
	u32 mask = BIT(irqd_to_hwirq(d));
	u32 reg_both, reg_level, reg_type;

	reg_type = readl(g->base + GPIO_INT_TYPE);
	reg_level = readl(g->base + GPIO_INT_LEVEL);
	reg_both = readl(g->base + GPIO_INT_BOTH_EDGE);

	switch (type) {
	case IRQ_TYPE_EDGE_BOTH:
		irq_set_handler_locked(d, handle_edge_irq);
		reg_type &= ~mask;
		reg_both |= mask;
		break;
	case IRQ_TYPE_EDGE_RISING:
		irq_set_handler_locked(d, handle_edge_irq);
		reg_type &= ~mask;
		reg_both &= ~mask;
		reg_level &= ~mask;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		irq_set_handler_locked(d, handle_edge_irq);
		reg_type &= ~mask;
		reg_both &= ~mask;
		reg_level |= mask;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		irq_set_handler_locked(d, handle_level_irq);
		reg_type |= mask;
		reg_level &= ~mask;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		irq_set_handler_locked(d, handle_level_irq);
		reg_type |= mask;
		reg_level |= mask;
		break;
	default:
		irq_set_handler_locked(d, handle_bad_irq);
		return -EINVAL;
	}

	writel(reg_type, g->base + GPIO_INT_TYPE);
	writel(reg_level, g->base + GPIO_INT_LEVEL);
	writel(reg_both, g->base + GPIO_INT_BOTH_EDGE);

	ftgpio_gpio_ack_irq(d);

	return 0;
}

static struct irq_chip ftgpio_gpio_irqchip = {
	.name = "FTGPIO010",
	.irq_ack = ftgpio_gpio_ack_irq,
	.irq_mask = ftgpio_gpio_mask_irq,
	.irq_unmask = ftgpio_gpio_unmask_irq,
	.irq_set_type = ftgpio_gpio_set_irq_type,
};

static void ftgpio_gpio_irq_handler(struct irq_desc *desc)
{
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	struct ftgpio_gpio *g = gpiochip_get_data(gc);
	struct irq_chip *irqchip = irq_desc_get_chip(desc);
	int offset;
	unsigned long stat;

	chained_irq_enter(irqchip, desc);

	stat = readl(g->base + GPIO_INT_STAT_RAW);
	if (stat)
		for_each_set_bit(offset, &stat, gc->ngpio)
			generic_handle_irq(irq_find_mapping(gc->irq.domain,
							    offset));

	chained_irq_exit(irqchip, desc);
}

static int ftgpio_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
				  unsigned long config)
{
	enum pin_config_param param = pinconf_to_config_param(config);
	u32 arg = pinconf_to_config_argument(config);
	struct ftgpio_gpio *g = gpiochip_get_data(gc);
	unsigned long pclk_freq;
	u32 deb_div;
	u32 val;

	if (param != PIN_CONFIG_INPUT_DEBOUNCE)
		return -ENOTSUPP;

	/*
	 * Debounce only works if interrupts are enabled. The manual
	 * states that if PCLK is 66 MHz, and this is set to 0x7D0, then
	 * PCLK is divided down to 33 kHz for the debounce timer. 0x7D0 is
	 * 2000 decimal, so what they mean is simply that the PCLK is
	 * divided by this value.
	 *
	 * As we get a debounce setting in microseconds, we calculate the
	 * desired period time and see if we can get a suitable debounce
	 * time.
	 */
	pclk_freq = clk_get_rate(g->clk);
	deb_div = DIV_ROUND_CLOSEST(pclk_freq, arg);

	/* This register is only 24 bits wide */
	if (deb_div > (1 << 24))
		return -ENOTSUPP;

	dev_dbg(g->dev, "prescale divisor: %08x, resulting frequency %lu Hz\n",
		deb_div, (pclk_freq/deb_div));

	val = readl(g->base + GPIO_DEBOUNCE_PRESCALE);
	if (val == deb_div) {
		/*
		 * The debounce timer happens to already be set to the
		 * desireable value, what a coincidence! We can just enable
		 * debounce on this GPIO line and return. This happens more
		 * often than you think, for example when all GPIO keys
		 * on a system are requesting the same debounce interval.
		 */
		val = readl(g->base + GPIO_DEBOUNCE_EN);
		val |= BIT(offset);
		writel(val, g->base + GPIO_DEBOUNCE_EN);
		return 0;
	}

	val = readl(g->base + GPIO_DEBOUNCE_EN);
	if (val) {
		/*
		 * Oh no! Someone is already using the debounce with
		 * another setting than what we need. Bummer.
		 */
		return -ENOTSUPP;
	}

	/* First come, first serve */
	writel(deb_div, g->base + GPIO_DEBOUNCE_PRESCALE);
	/* Enable debounce */
	val |= BIT(offset);
	writel(val, g->base + GPIO_DEBOUNCE_EN);

	return 0;
}

static int ftgpio_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct resource *res;
	struct ftgpio_gpio *g;
	int irq;
	int ret;

	g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
	if (!g)
		return -ENOMEM;

	g->dev = dev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	g->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(g->base))
		return PTR_ERR(g->base);

	irq = platform_get_irq(pdev, 0);
	if (irq <= 0)
		return irq ? irq : -EINVAL;

	g->clk = devm_clk_get(dev, NULL);
	if (!IS_ERR(g->clk)) {
		ret = clk_prepare_enable(g->clk);
		if (ret)
			return ret;
	} else if (PTR_ERR(g->clk) == -EPROBE_DEFER) {
		/*
		 * Percolate deferrals, for anything else,
		 * just live without the clocking.
		 */
		return PTR_ERR(g->clk);
	}

	ret = bgpio_init(&g->gc, dev, 4,
			 g->base + GPIO_DATA_IN,
			 g->base + GPIO_DATA_SET,
			 g->base + GPIO_DATA_CLR,
			 g->base + GPIO_DIR,
			 NULL,
			 0);
	if (ret) {
		dev_err(dev, "unable to init generic GPIO\n");
		goto dis_clk;
	}
	g->gc.label = "FTGPIO010";
	g->gc.base = -1;
	g->gc.parent = dev;
	g->gc.owner = THIS_MODULE;
	/* ngpio is set by bgpio_init() */

	/* We need a silicon clock to do debounce */
	if (!IS_ERR(g->clk))
		g->gc.set_config = ftgpio_gpio_set_config;

	ret = devm_gpiochip_add_data(dev, &g->gc, g);
	if (ret)
		goto dis_clk;

	/* Disable, unmask and clear all interrupts */
	writel(0x0, g->base + GPIO_INT_EN);
	writel(0x0, g->base + GPIO_INT_MASK);
	writel(~0x0, g->base + GPIO_INT_CLR);

	/* Clear any use of debounce */
	writel(0x0, g->base + GPIO_DEBOUNCE_EN);

	ret = gpiochip_irqchip_add(&g->gc, &ftgpio_gpio_irqchip,
				   0, handle_bad_irq,
				   IRQ_TYPE_NONE);
	if (ret) {
		dev_info(dev, "could not add irqchip\n");
		goto dis_clk;
	}
	gpiochip_set_chained_irqchip(&g->gc, &ftgpio_gpio_irqchip,
				     irq, ftgpio_gpio_irq_handler);

	platform_set_drvdata(pdev, g);
	dev_info(dev, "FTGPIO010 @%p registered\n", g->base);

	return 0;

dis_clk:
	if (!IS_ERR(g->clk))
		clk_disable_unprepare(g->clk);
	return ret;
}

static int ftgpio_gpio_remove(struct platform_device *pdev)
{
	struct ftgpio_gpio *g = platform_get_drvdata(pdev);

	if (!IS_ERR(g->clk))
		clk_disable_unprepare(g->clk);
	return 0;
}

static const struct of_device_id ftgpio_gpio_of_match[] = {
	{
		.compatible = "cortina,gemini-gpio",
	},
	{
		.compatible = "moxa,moxart-gpio",
	},
	{
		.compatible = "faraday,ftgpio010",
	},
	{},
};

static struct platform_driver ftgpio_gpio_driver = {
	.driver = {
		.name		= "ftgpio010-gpio",
		.of_match_table = of_match_ptr(ftgpio_gpio_of_match),
	},
	.probe = ftgpio_gpio_probe,
	.remove = ftgpio_gpio_remove,
};
builtin_platform_driver(ftgpio_gpio_driver);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
49cec4d8	2	/*
9d3a15aa	3	* Faraday Technolog FTGPIO010 gpiochip and interrupt routines
49cec4d8 LW	4	* Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
	5	*
	6	* Based on arch/arm/mach-gemini/gpio.c:
	7	* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
	8	*
	9	* Based on plat-mxc/gpio.c:
	10	* MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
	11	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	12	*/
	13	#include <linux/gpio/driver.h>
	14	#include <linux/io.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/platform_device.h>
49cec4d8	17	#include <linux/bitops.h>
da02d794	18	#include <linux/clk.h>
49cec4d8 LW	19
	20	/* GPIO registers definition */
	21	#define GPIO_DATA_OUT 0x00
	22	#define GPIO_DATA_IN 0x04
	23	#define GPIO_DIR 0x08
69a87f29	24	#define GPIO_BYPASS_IN 0x0C
49cec4d8 LW	25	#define GPIO_DATA_SET 0x10
	26	#define GPIO_DATA_CLR 0x14
	27	#define GPIO_PULL_EN 0x18
	28	#define GPIO_PULL_TYPE 0x1C
	29	#define GPIO_INT_EN 0x20
69a87f29 LW	30	#define GPIO_INT_STAT_RAW 0x24
69a87f29 LW	31	#define GPIO_INT_STAT_MASKED 0x28
49cec4d8 LW	32	#define GPIO_INT_MASK 0x2C
	33	#define GPIO_INT_CLR 0x30
	34	#define GPIO_INT_TYPE 0x34
	35	#define GPIO_INT_BOTH_EDGE 0x38
	36	#define GPIO_INT_LEVEL 0x3C
	37	#define GPIO_DEBOUNCE_EN 0x40
	38	#define GPIO_DEBOUNCE_PRESCALE 0x44
	39
	40	/**
9d3a15aa	41	* struct ftgpio_gpio - Gemini GPIO state container
49cec4d8 LW	42	* @dev: containing device for this instance
49cec4d8 LW	43	* @gc: gpiochip for this instance
da02d794 LW	44	* @base: remapped I/O-memory base
da02d794 LW	45	* @clk: silicon clock
49cec4d8	46	*/
9d3a15aa	47	struct ftgpio_gpio {
49cec4d8 LW	48	struct device *dev;
	49	struct gpio_chip gc;
	50	void __iomem *base;
da02d794	51	struct clk *clk;
49cec4d8 LW	52	};
49cec4d8 LW	53
9d3a15aa	54	static void ftgpio_gpio_ack_irq(struct irq_data *d)
49cec4d8 LW	55	{
49cec4d8 LW	56	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
9d3a15aa	57	struct ftgpio_gpio *g = gpiochip_get_data(gc);
49cec4d8 LW	58
	59	writel(BIT(irqd_to_hwirq(d)), g->base + GPIO_INT_CLR);
	60	}
	61
9d3a15aa	62	static void ftgpio_gpio_mask_irq(struct irq_data *d)
49cec4d8 LW	63	{
49cec4d8 LW	64	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
9d3a15aa	65	struct ftgpio_gpio *g = gpiochip_get_data(gc);
49cec4d8 LW	66	u32 val;
	67
	68	val = readl(g->base + GPIO_INT_EN);
	69	val &= ~BIT(irqd_to_hwirq(d));
	70	writel(val, g->base + GPIO_INT_EN);
	71	}
	72
9d3a15aa	73	static void ftgpio_gpio_unmask_irq(struct irq_data *d)
49cec4d8 LW	74	{
49cec4d8 LW	75	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
9d3a15aa	76	struct ftgpio_gpio *g = gpiochip_get_data(gc);
49cec4d8 LW	77	u32 val;
	78
	79	val = readl(g->base + GPIO_INT_EN);
	80	val \|= BIT(irqd_to_hwirq(d));
	81	writel(val, g->base + GPIO_INT_EN);
	82	}
	83
9d3a15aa	84	static int ftgpio_gpio_set_irq_type(struct irq_data *d, unsigned int type)
49cec4d8 LW	85	{
49cec4d8 LW	86	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
9d3a15aa	87	struct ftgpio_gpio *g = gpiochip_get_data(gc);
49cec4d8 LW	88	u32 mask = BIT(irqd_to_hwirq(d));
	89	u32 reg_both, reg_level, reg_type;
	90
	91	reg_type = readl(g->base + GPIO_INT_TYPE);
	92	reg_level = readl(g->base + GPIO_INT_LEVEL);
	93	reg_both = readl(g->base + GPIO_INT_BOTH_EDGE);
	94
	95	switch (type) {
	96	case IRQ_TYPE_EDGE_BOTH:
	97	irq_set_handler_locked(d, handle_edge_irq);
	98	reg_type &= ~mask;
	99	reg_both \|= mask;
	100	break;
	101	case IRQ_TYPE_EDGE_RISING:
	102	irq_set_handler_locked(d, handle_edge_irq);
	103	reg_type &= ~mask;
	104	reg_both &= ~mask;
	105	reg_level &= ~mask;
	106	break;
	107	case IRQ_TYPE_EDGE_FALLING:
	108	irq_set_handler_locked(d, handle_edge_irq);
	109	reg_type &= ~mask;
	110	reg_both &= ~mask;
	111	reg_level \|= mask;
	112	break;
	113	case IRQ_TYPE_LEVEL_HIGH:
	114	irq_set_handler_locked(d, handle_level_irq);
	115	reg_type \|= mask;
	116	reg_level &= ~mask;
	117	break;
	118	case IRQ_TYPE_LEVEL_LOW:
	119	irq_set_handler_locked(d, handle_level_irq);
	120	reg_type \|= mask;
	121	reg_level \|= mask;
	122	break;
	123	default:
	124	irq_set_handler_locked(d, handle_bad_irq);
	125	return -EINVAL;
	126	}
	127
	128	writel(reg_type, g->base + GPIO_INT_TYPE);
	129	writel(reg_level, g->base + GPIO_INT_LEVEL);
	130	writel(reg_both, g->base + GPIO_INT_BOTH_EDGE);
	131
9d3a15aa	132	ftgpio_gpio_ack_irq(d);
49cec4d8 LW	133
	134	return 0;
	135	}
	136
9d3a15aa LW	137	static struct irq_chip ftgpio_gpio_irqchip = {
	138	.name = "FTGPIO010",
	139	.irq_ack = ftgpio_gpio_ack_irq,
	140	.irq_mask = ftgpio_gpio_mask_irq,
	141	.irq_unmask = ftgpio_gpio_unmask_irq,
	142	.irq_set_type = ftgpio_gpio_set_irq_type,
49cec4d8 LW	143	};
49cec4d8 LW	144
9d3a15aa	145	static void ftgpio_gpio_irq_handler(struct irq_desc *desc)
49cec4d8 LW	146	{
49cec4d8 LW	147	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
9d3a15aa	148	struct ftgpio_gpio *g = gpiochip_get_data(gc);
49cec4d8 LW	149	struct irq_chip *irqchip = irq_desc_get_chip(desc);
	150	int offset;
	151	unsigned long stat;
	152
	153	chained_irq_enter(irqchip, desc);
	154
69a87f29	155	stat = readl(g->base + GPIO_INT_STAT_RAW);
49cec4d8 LW	156	if (stat)
49cec4d8 LW	157	for_each_set_bit(offset, &stat, gc->ngpio)
f0fbe7bc	158	generic_handle_irq(irq_find_mapping(gc->irq.domain,
49cec4d8 LW	159	offset));
	160
	161	chained_irq_exit(irqchip, desc);
	162	}
	163
36f3f19a LW	164	static int ftgpio_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
	165	unsigned long config)
	166	{
	167	enum pin_config_param param = pinconf_to_config_param(config);
	168	u32 arg = pinconf_to_config_argument(config);
	169	struct ftgpio_gpio *g = gpiochip_get_data(gc);
	170	unsigned long pclk_freq;
	171	u32 deb_div;
	172	u32 val;
	173
	174	if (param != PIN_CONFIG_INPUT_DEBOUNCE)
	175	return -ENOTSUPP;
	176
	177	/*
	178	* Debounce only works if interrupts are enabled. The manual
	179	* states that if PCLK is 66 MHz, and this is set to 0x7D0, then
	180	* PCLK is divided down to 33 kHz for the debounce timer. 0x7D0 is
	181	* 2000 decimal, so what they mean is simply that the PCLK is
	182	* divided by this value.
	183	*
	184	* As we get a debounce setting in microseconds, we calculate the
	185	* desired period time and see if we can get a suitable debounce
	186	* time.
	187	*/
	188	pclk_freq = clk_get_rate(g->clk);
	189	deb_div = DIV_ROUND_CLOSEST(pclk_freq, arg);
	190
	191	/* This register is only 24 bits wide */
	192	if (deb_div > (1 << 24))
	193	return -ENOTSUPP;
	194
	195	dev_dbg(g->dev, "prescale divisor: %08x, resulting frequency %lu Hz\n",
	196	deb_div, (pclk_freq/deb_div));
	197
	198	val = readl(g->base + GPIO_DEBOUNCE_PRESCALE);
	199	if (val == deb_div) {
	200	/*
	201	* The debounce timer happens to already be set to the
	202	* desireable value, what a coincidence! We can just enable
	203	* debounce on this GPIO line and return. This happens more
	204	* often than you think, for example when all GPIO keys
	205	* on a system are requesting the same debounce interval.
	206	*/
	207	val = readl(g->base + GPIO_DEBOUNCE_EN);
	208	val \|= BIT(offset);
	209	writel(val, g->base + GPIO_DEBOUNCE_EN);
	210	return 0;
	211	}
	212
	213	val = readl(g->base + GPIO_DEBOUNCE_EN);
	214	if (val) {
	215	/*
	216	* Oh no! Someone is already using the debounce with
	217	* another setting than what we need. Bummer.
	218	*/
	219	return -ENOTSUPP;
	220	}
	221
	222	/* First come, first serve */
	223	writel(deb_div, g->base + GPIO_DEBOUNCE_PRESCALE);
	224	/* Enable debounce */
	225	val \|= BIT(offset);
	226	writel(val, g->base + GPIO_DEBOUNCE_EN);
	227
228	return 0;
229	}
230
9d3a15aa	231	static int ftgpio_gpio_probe(struct platform_device *pdev)
49cec4d8 LW	232	{
	233	struct device *dev = &pdev->dev;
	234	struct resource *res;
9d3a15aa	235	struct ftgpio_gpio *g;
49cec4d8 LW	236	int irq;
	237	int ret;
	238
	239	g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
	240	if (!g)
	241	return -ENOMEM;
	242
	243	g->dev = dev;
	244
	245	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	246	g->base = devm_ioremap_resource(dev, res);
	247	if (IS_ERR(g->base))
	248	return PTR_ERR(g->base);
	249
	250	irq = platform_get_irq(pdev, 0);
4070a534 AY	251	if (irq <= 0)
4070a534 AY	252	return irq ? irq : -EINVAL;
49cec4d8	253
da02d794 LW	254	g->clk = devm_clk_get(dev, NULL);
	255	if (!IS_ERR(g->clk)) {
	256	ret = clk_prepare_enable(g->clk);
	257	if (ret)
	258	return ret;
	259	} else if (PTR_ERR(g->clk) == -EPROBE_DEFER) {
	260	/*
	261	* Percolate deferrals, for anything else,
	262	* just live without the clocking.
	263	*/
	264	return PTR_ERR(g->clk);
	265	}
	266
49cec4d8 LW	267	ret = bgpio_init(&g->gc, dev, 4,
	268	g->base + GPIO_DATA_IN,
	269	g->base + GPIO_DATA_SET,
	270	g->base + GPIO_DATA_CLR,
	271	g->base + GPIO_DIR,
	272	NULL,
	273	0);
	274	if (ret) {
	275	dev_err(dev, "unable to init generic GPIO\n");
da02d794	276	goto dis_clk;
49cec4d8	277	}
9d3a15aa	278	g->gc.label = "FTGPIO010";
49cec4d8 LW	279	g->gc.base = -1;
	280	g->gc.parent = dev;
	281	g->gc.owner = THIS_MODULE;
	282	/* ngpio is set by bgpio_init() */
	283
36f3f19a LW	284	/* We need a silicon clock to do debounce */
	285	if (!IS_ERR(g->clk))
	286	g->gc.set_config = ftgpio_gpio_set_config;
	287
49cec4d8 LW	288	ret = devm_gpiochip_add_data(dev, &g->gc, g);
49cec4d8 LW	289	if (ret)
da02d794	290	goto dis_clk;
49cec4d8 LW	291
	292	/* Disable, unmask and clear all interrupts */
	293	writel(0x0, g->base + GPIO_INT_EN);
	294	writel(0x0, g->base + GPIO_INT_MASK);
	295	writel(~0x0, g->base + GPIO_INT_CLR);
	296
36f3f19a LW	297	/* Clear any use of debounce */
	298	writel(0x0, g->base + GPIO_DEBOUNCE_EN);
	299
9d3a15aa	300	ret = gpiochip_irqchip_add(&g->gc, &ftgpio_gpio_irqchip,
49cec4d8 LW	301	0, handle_bad_irq,
	302	IRQ_TYPE_NONE);
	303	if (ret) {
	304	dev_info(dev, "could not add irqchip\n");
da02d794	305	goto dis_clk;
49cec4d8	306	}
9d3a15aa LW	307	gpiochip_set_chained_irqchip(&g->gc, &ftgpio_gpio_irqchip,
9d3a15aa LW	308	irq, ftgpio_gpio_irq_handler);
49cec4d8	309
da02d794	310	platform_set_drvdata(pdev, g);
9d3a15aa	311	dev_info(dev, "FTGPIO010 @%p registered\n", g->base);
49cec4d8 LW	312
49cec4d8 LW	313	return 0;
da02d794 LW	314
	315	dis_clk:
	316	if (!IS_ERR(g->clk))
	317	clk_disable_unprepare(g->clk);
	318	return ret;
	319	}
	320
	321	static int ftgpio_gpio_remove(struct platform_device *pdev)
	322	{
	323	struct ftgpio_gpio *g = platform_get_drvdata(pdev);
	324
	325	if (!IS_ERR(g->clk))
	326	clk_disable_unprepare(g->clk);
	327	return 0;
49cec4d8 LW	328	}
49cec4d8 LW	329
9d3a15aa	330	static const struct of_device_id ftgpio_gpio_of_match[] = {
49cec4d8 LW	331	{
	332	.compatible = "cortina,gemini-gpio",
	333	},
9d3a15aa LW	334	{
	335	.compatible = "moxa,moxart-gpio",
	336	},
	337	{
	338	.compatible = "faraday,ftgpio010",
	339	},
49cec4d8 LW	340	{},
	341	};
	342
9d3a15aa	343	static struct platform_driver ftgpio_gpio_driver = {
49cec4d8	344	.driver = {
9d3a15aa LW	345	.name = "ftgpio010-gpio",
9d3a15aa LW	346	.of_match_table = of_match_ptr(ftgpio_gpio_of_match),
49cec4d8	347	},
da02d794 LW	348	.probe = ftgpio_gpio_probe,
da02d794 LW	349	.remove = ftgpio_gpio_remove,
49cec4d8	350	};
9d3a15aa	351	builtin_platform_driver(ftgpio_gpio_driver);