Commit | Line | Data |
---|---|---|
2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
6c17aa01 | 2 | /* |
1920906f | 3 | * GPIO driver for Fintek Super-I/O F71869, F71869A, F71882, F71889 and F81866 |
6c17aa01 SG |
4 | * |
5 | * Copyright (C) 2010-2013 LaCie | |
6 | * | |
7 | * Author: Simon Guinot <simon.guinot@sequanux.org> | |
6c17aa01 SG |
8 | */ |
9 | ||
10 | #include <linux/module.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/platform_device.h> | |
13 | #include <linux/io.h> | |
148c8642 LW |
14 | #include <linux/gpio/driver.h> |
15 | #include <linux/bitops.h> | |
6c17aa01 SG |
16 | |
17 | #define DRVNAME "gpio-f7188x" | |
18 | ||
19 | /* | |
20 | * Super-I/O registers | |
21 | */ | |
22 | #define SIO_LDSEL 0x07 /* Logical device select */ | |
23 | #define SIO_DEVID 0x20 /* Device ID (2 bytes) */ | |
24 | #define SIO_DEVREV 0x22 /* Device revision */ | |
25 | #define SIO_MANID 0x23 /* Fintek ID (2 bytes) */ | |
26 | ||
27 | #define SIO_LD_GPIO 0x06 /* GPIO logical device */ | |
28 | #define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */ | |
29 | #define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */ | |
30 | ||
31 | #define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */ | |
24ccef35 | 32 | #define SIO_F71869_ID 0x0814 /* F71869 chipset ID */ |
7e960363 | 33 | #define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */ |
6c17aa01 SG |
34 | #define SIO_F71882_ID 0x0541 /* F71882 chipset ID */ |
35 | #define SIO_F71889_ID 0x0909 /* F71889 chipset ID */ | |
d69843e4 | 36 | #define SIO_F71889A_ID 0x1005 /* F71889A chipset ID */ |
1920906f | 37 | #define SIO_F81866_ID 0x1010 /* F81866 chipset ID */ |
b0c3e54e | 38 | #define SIO_F81804_ID 0x1502 /* F81804 chipset ID, same for f81966 */ |
6c17aa01 | 39 | |
b0c3e54e SK |
40 | |
41 | enum chips { f71869, f71869a, f71882fg, f71889a, f71889f, f81866, f81804 }; | |
6c17aa01 SG |
42 | |
43 | static const char * const f7188x_names[] = { | |
24ccef35 | 44 | "f71869", |
7e960363 | 45 | "f71869a", |
6c17aa01 | 46 | "f71882fg", |
d69843e4 | 47 | "f71889a", |
6c17aa01 | 48 | "f71889f", |
1920906f | 49 | "f81866", |
b0c3e54e | 50 | "f81804", |
6c17aa01 SG |
51 | }; |
52 | ||
53 | struct f7188x_sio { | |
54 | int addr; | |
55 | enum chips type; | |
56 | }; | |
57 | ||
58 | struct f7188x_gpio_bank { | |
59 | struct gpio_chip chip; | |
60 | unsigned int regbase; | |
61 | struct f7188x_gpio_data *data; | |
62 | }; | |
63 | ||
64 | struct f7188x_gpio_data { | |
65 | struct f7188x_sio *sio; | |
66 | int nr_bank; | |
67 | struct f7188x_gpio_bank *bank; | |
68 | }; | |
69 | ||
70 | /* | |
71 | * Super-I/O functions. | |
72 | */ | |
73 | ||
74 | static inline int superio_inb(int base, int reg) | |
75 | { | |
76 | outb(reg, base); | |
77 | return inb(base + 1); | |
78 | } | |
79 | ||
80 | static int superio_inw(int base, int reg) | |
81 | { | |
82 | int val; | |
83 | ||
84 | outb(reg++, base); | |
85 | val = inb(base + 1) << 8; | |
86 | outb(reg, base); | |
87 | val |= inb(base + 1); | |
88 | ||
89 | return val; | |
90 | } | |
91 | ||
92 | static inline void superio_outb(int base, int reg, int val) | |
93 | { | |
94 | outb(reg, base); | |
95 | outb(val, base + 1); | |
96 | } | |
97 | ||
98 | static inline int superio_enter(int base) | |
99 | { | |
100 | /* Don't step on other drivers' I/O space by accident. */ | |
101 | if (!request_muxed_region(base, 2, DRVNAME)) { | |
102 | pr_err(DRVNAME "I/O address 0x%04x already in use\n", base); | |
103 | return -EBUSY; | |
104 | } | |
105 | ||
106 | /* According to the datasheet the key must be send twice. */ | |
107 | outb(SIO_UNLOCK_KEY, base); | |
108 | outb(SIO_UNLOCK_KEY, base); | |
109 | ||
110 | return 0; | |
111 | } | |
112 | ||
113 | static inline void superio_select(int base, int ld) | |
114 | { | |
115 | outb(SIO_LDSEL, base); | |
116 | outb(ld, base + 1); | |
117 | } | |
118 | ||
119 | static inline void superio_exit(int base) | |
120 | { | |
121 | outb(SIO_LOCK_KEY, base); | |
122 | release_region(base, 2); | |
123 | } | |
124 | ||
125 | /* | |
126 | * GPIO chip. | |
127 | */ | |
128 | ||
107cdd2d | 129 | static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset); |
6c17aa01 SG |
130 | static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset); |
131 | static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset); | |
132 | static int f7188x_gpio_direction_out(struct gpio_chip *chip, | |
133 | unsigned offset, int value); | |
134 | static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value); | |
2956b5d9 MW |
135 | static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset, |
136 | unsigned long config); | |
6c17aa01 SG |
137 | |
138 | #define F7188X_GPIO_BANK(_base, _ngpio, _regbase) \ | |
139 | { \ | |
140 | .chip = { \ | |
141 | .label = DRVNAME, \ | |
142 | .owner = THIS_MODULE, \ | |
107cdd2d | 143 | .get_direction = f7188x_gpio_get_direction, \ |
6c17aa01 SG |
144 | .direction_input = f7188x_gpio_direction_in, \ |
145 | .get = f7188x_gpio_get, \ | |
146 | .direction_output = f7188x_gpio_direction_out, \ | |
147 | .set = f7188x_gpio_set, \ | |
2956b5d9 | 148 | .set_config = f7188x_gpio_set_config, \ |
6c17aa01 SG |
149 | .base = _base, \ |
150 | .ngpio = _ngpio, \ | |
aeccc1b4 | 151 | .can_sleep = true, \ |
6c17aa01 SG |
152 | }, \ |
153 | .regbase = _regbase, \ | |
154 | } | |
155 | ||
156 | #define gpio_dir(base) (base + 0) | |
157 | #define gpio_data_out(base) (base + 1) | |
158 | #define gpio_data_in(base) (base + 2) | |
159 | /* Output mode register (0:open drain 1:push-pull). */ | |
160 | #define gpio_out_mode(base) (base + 3) | |
161 | ||
24ccef35 AB |
162 | static struct f7188x_gpio_bank f71869_gpio_bank[] = { |
163 | F7188X_GPIO_BANK(0, 6, 0xF0), | |
164 | F7188X_GPIO_BANK(10, 8, 0xE0), | |
165 | F7188X_GPIO_BANK(20, 8, 0xD0), | |
166 | F7188X_GPIO_BANK(30, 8, 0xC0), | |
167 | F7188X_GPIO_BANK(40, 8, 0xB0), | |
168 | F7188X_GPIO_BANK(50, 5, 0xA0), | |
169 | F7188X_GPIO_BANK(60, 6, 0x90), | |
170 | }; | |
171 | ||
7e960363 AB |
172 | static struct f7188x_gpio_bank f71869a_gpio_bank[] = { |
173 | F7188X_GPIO_BANK(0, 6, 0xF0), | |
174 | F7188X_GPIO_BANK(10, 8, 0xE0), | |
175 | F7188X_GPIO_BANK(20, 8, 0xD0), | |
176 | F7188X_GPIO_BANK(30, 8, 0xC0), | |
177 | F7188X_GPIO_BANK(40, 8, 0xB0), | |
178 | F7188X_GPIO_BANK(50, 5, 0xA0), | |
179 | F7188X_GPIO_BANK(60, 8, 0x90), | |
180 | F7188X_GPIO_BANK(70, 8, 0x80), | |
181 | }; | |
182 | ||
6c17aa01 | 183 | static struct f7188x_gpio_bank f71882_gpio_bank[] = { |
38e003f4 | 184 | F7188X_GPIO_BANK(0, 8, 0xF0), |
6c17aa01 SG |
185 | F7188X_GPIO_BANK(10, 8, 0xE0), |
186 | F7188X_GPIO_BANK(20, 8, 0xD0), | |
187 | F7188X_GPIO_BANK(30, 4, 0xC0), | |
188 | F7188X_GPIO_BANK(40, 4, 0xB0), | |
189 | }; | |
190 | ||
d69843e4 MP |
191 | static struct f7188x_gpio_bank f71889a_gpio_bank[] = { |
192 | F7188X_GPIO_BANK(0, 7, 0xF0), | |
193 | F7188X_GPIO_BANK(10, 7, 0xE0), | |
194 | F7188X_GPIO_BANK(20, 8, 0xD0), | |
195 | F7188X_GPIO_BANK(30, 8, 0xC0), | |
196 | F7188X_GPIO_BANK(40, 8, 0xB0), | |
197 | F7188X_GPIO_BANK(50, 5, 0xA0), | |
198 | F7188X_GPIO_BANK(60, 8, 0x90), | |
199 | F7188X_GPIO_BANK(70, 8, 0x80), | |
200 | }; | |
201 | ||
6c17aa01 | 202 | static struct f7188x_gpio_bank f71889_gpio_bank[] = { |
38e003f4 | 203 | F7188X_GPIO_BANK(0, 7, 0xF0), |
6c17aa01 SG |
204 | F7188X_GPIO_BANK(10, 7, 0xE0), |
205 | F7188X_GPIO_BANK(20, 8, 0xD0), | |
206 | F7188X_GPIO_BANK(30, 8, 0xC0), | |
207 | F7188X_GPIO_BANK(40, 8, 0xB0), | |
208 | F7188X_GPIO_BANK(50, 5, 0xA0), | |
209 | F7188X_GPIO_BANK(60, 8, 0x90), | |
210 | F7188X_GPIO_BANK(70, 8, 0x80), | |
211 | }; | |
212 | ||
1920906f PH |
213 | static struct f7188x_gpio_bank f81866_gpio_bank[] = { |
214 | F7188X_GPIO_BANK(0, 8, 0xF0), | |
215 | F7188X_GPIO_BANK(10, 8, 0xE0), | |
216 | F7188X_GPIO_BANK(20, 8, 0xD0), | |
217 | F7188X_GPIO_BANK(30, 8, 0xC0), | |
218 | F7188X_GPIO_BANK(40, 8, 0xB0), | |
219 | F7188X_GPIO_BANK(50, 8, 0xA0), | |
220 | F7188X_GPIO_BANK(60, 8, 0x90), | |
221 | F7188X_GPIO_BANK(70, 8, 0x80), | |
222 | F7188X_GPIO_BANK(80, 8, 0x88), | |
223 | }; | |
224 | ||
b0c3e54e SK |
225 | |
226 | static struct f7188x_gpio_bank f81804_gpio_bank[] = { | |
227 | F7188X_GPIO_BANK(0, 8, 0xF0), | |
228 | F7188X_GPIO_BANK(10, 8, 0xE0), | |
229 | F7188X_GPIO_BANK(20, 8, 0xD0), | |
230 | F7188X_GPIO_BANK(50, 8, 0xA0), | |
231 | F7188X_GPIO_BANK(60, 8, 0x90), | |
232 | F7188X_GPIO_BANK(70, 8, 0x80), | |
233 | F7188X_GPIO_BANK(90, 8, 0x98), | |
234 | }; | |
235 | ||
236 | ||
107cdd2d | 237 | static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
238 | { | |
239 | int err; | |
35a26144 | 240 | struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); |
107cdd2d | 241 | struct f7188x_sio *sio = bank->data->sio; |
242 | u8 dir; | |
243 | ||
244 | err = superio_enter(sio->addr); | |
245 | if (err) | |
246 | return err; | |
247 | superio_select(sio->addr, SIO_LD_GPIO); | |
248 | ||
249 | dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); | |
250 | ||
251 | superio_exit(sio->addr); | |
252 | ||
253 | return !(dir & 1 << offset); | |
254 | } | |
255 | ||
6c17aa01 SG |
256 | static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset) |
257 | { | |
258 | int err; | |
f372d5f5 | 259 | struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); |
6c17aa01 SG |
260 | struct f7188x_sio *sio = bank->data->sio; |
261 | u8 dir; | |
262 | ||
263 | err = superio_enter(sio->addr); | |
264 | if (err) | |
265 | return err; | |
266 | superio_select(sio->addr, SIO_LD_GPIO); | |
267 | ||
268 | dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); | |
148c8642 | 269 | dir &= ~BIT(offset); |
6c17aa01 SG |
270 | superio_outb(sio->addr, gpio_dir(bank->regbase), dir); |
271 | ||
272 | superio_exit(sio->addr); | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
277 | static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset) | |
278 | { | |
279 | int err; | |
f372d5f5 | 280 | struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); |
6c17aa01 SG |
281 | struct f7188x_sio *sio = bank->data->sio; |
282 | u8 dir, data; | |
283 | ||
284 | err = superio_enter(sio->addr); | |
285 | if (err) | |
286 | return err; | |
287 | superio_select(sio->addr, SIO_LD_GPIO); | |
288 | ||
289 | dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); | |
148c8642 | 290 | dir = !!(dir & BIT(offset)); |
6c17aa01 SG |
291 | if (dir) |
292 | data = superio_inb(sio->addr, gpio_data_out(bank->regbase)); | |
293 | else | |
294 | data = superio_inb(sio->addr, gpio_data_in(bank->regbase)); | |
295 | ||
296 | superio_exit(sio->addr); | |
297 | ||
148c8642 | 298 | return !!(data & BIT(offset)); |
6c17aa01 SG |
299 | } |
300 | ||
301 | static int f7188x_gpio_direction_out(struct gpio_chip *chip, | |
302 | unsigned offset, int value) | |
303 | { | |
304 | int err; | |
f372d5f5 | 305 | struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); |
6c17aa01 SG |
306 | struct f7188x_sio *sio = bank->data->sio; |
307 | u8 dir, data_out; | |
308 | ||
309 | err = superio_enter(sio->addr); | |
310 | if (err) | |
311 | return err; | |
312 | superio_select(sio->addr, SIO_LD_GPIO); | |
313 | ||
314 | data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase)); | |
315 | if (value) | |
148c8642 | 316 | data_out |= BIT(offset); |
6c17aa01 | 317 | else |
148c8642 | 318 | data_out &= ~BIT(offset); |
6c17aa01 SG |
319 | superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out); |
320 | ||
321 | dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); | |
148c8642 | 322 | dir |= BIT(offset); |
6c17aa01 SG |
323 | superio_outb(sio->addr, gpio_dir(bank->regbase), dir); |
324 | ||
325 | superio_exit(sio->addr); | |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
330 | static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
331 | { | |
332 | int err; | |
f372d5f5 | 333 | struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); |
6c17aa01 SG |
334 | struct f7188x_sio *sio = bank->data->sio; |
335 | u8 data_out; | |
336 | ||
337 | err = superio_enter(sio->addr); | |
338 | if (err) | |
339 | return; | |
340 | superio_select(sio->addr, SIO_LD_GPIO); | |
341 | ||
342 | data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase)); | |
343 | if (value) | |
148c8642 | 344 | data_out |= BIT(offset); |
6c17aa01 | 345 | else |
148c8642 | 346 | data_out &= ~BIT(offset); |
6c17aa01 SG |
347 | superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out); |
348 | ||
349 | superio_exit(sio->addr); | |
350 | } | |
351 | ||
2956b5d9 MW |
352 | static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset, |
353 | unsigned long config) | |
f90c6bdb LW |
354 | { |
355 | int err; | |
2956b5d9 | 356 | enum pin_config_param param = pinconf_to_config_param(config); |
f90c6bdb LW |
357 | struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); |
358 | struct f7188x_sio *sio = bank->data->sio; | |
359 | u8 data; | |
360 | ||
2956b5d9 MW |
361 | if (param != PIN_CONFIG_DRIVE_OPEN_DRAIN && |
362 | param != PIN_CONFIG_DRIVE_PUSH_PULL) | |
f90c6bdb LW |
363 | return -ENOTSUPP; |
364 | ||
365 | err = superio_enter(sio->addr); | |
366 | if (err) | |
367 | return err; | |
368 | superio_select(sio->addr, SIO_LD_GPIO); | |
369 | ||
370 | data = superio_inb(sio->addr, gpio_out_mode(bank->regbase)); | |
2956b5d9 | 371 | if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN) |
f90c6bdb LW |
372 | data &= ~BIT(offset); |
373 | else | |
374 | data |= BIT(offset); | |
327819d1 | 375 | superio_outb(sio->addr, gpio_out_mode(bank->regbase), data); |
f90c6bdb LW |
376 | |
377 | superio_exit(sio->addr); | |
378 | return 0; | |
379 | } | |
380 | ||
6c17aa01 SG |
381 | /* |
382 | * Platform device and driver. | |
383 | */ | |
384 | ||
385 | static int f7188x_gpio_probe(struct platform_device *pdev) | |
386 | { | |
387 | int err; | |
388 | int i; | |
ab128afc | 389 | struct f7188x_sio *sio = dev_get_platdata(&pdev->dev); |
6c17aa01 SG |
390 | struct f7188x_gpio_data *data; |
391 | ||
392 | data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); | |
393 | if (!data) | |
394 | return -ENOMEM; | |
395 | ||
396 | switch (sio->type) { | |
24ccef35 AB |
397 | case f71869: |
398 | data->nr_bank = ARRAY_SIZE(f71869_gpio_bank); | |
399 | data->bank = f71869_gpio_bank; | |
400 | break; | |
7e960363 AB |
401 | case f71869a: |
402 | data->nr_bank = ARRAY_SIZE(f71869a_gpio_bank); | |
403 | data->bank = f71869a_gpio_bank; | |
404 | break; | |
6c17aa01 SG |
405 | case f71882fg: |
406 | data->nr_bank = ARRAY_SIZE(f71882_gpio_bank); | |
407 | data->bank = f71882_gpio_bank; | |
408 | break; | |
d69843e4 MP |
409 | case f71889a: |
410 | data->nr_bank = ARRAY_SIZE(f71889a_gpio_bank); | |
411 | data->bank = f71889a_gpio_bank; | |
b86c86aa | 412 | break; |
6c17aa01 SG |
413 | case f71889f: |
414 | data->nr_bank = ARRAY_SIZE(f71889_gpio_bank); | |
415 | data->bank = f71889_gpio_bank; | |
416 | break; | |
1920906f PH |
417 | case f81866: |
418 | data->nr_bank = ARRAY_SIZE(f81866_gpio_bank); | |
419 | data->bank = f81866_gpio_bank; | |
420 | break; | |
b0c3e54e SK |
421 | case f81804: |
422 | data->nr_bank = ARRAY_SIZE(f81804_gpio_bank); | |
423 | data->bank = f81804_gpio_bank; | |
424 | break; | |
6c17aa01 SG |
425 | default: |
426 | return -ENODEV; | |
427 | } | |
428 | data->sio = sio; | |
429 | ||
430 | platform_set_drvdata(pdev, data); | |
431 | ||
432 | /* For each GPIO bank, register a GPIO chip. */ | |
433 | for (i = 0; i < data->nr_bank; i++) { | |
434 | struct f7188x_gpio_bank *bank = &data->bank[i]; | |
435 | ||
58383c78 | 436 | bank->chip.parent = &pdev->dev; |
6c17aa01 SG |
437 | bank->data = data; |
438 | ||
330f4e56 | 439 | err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank); |
6c17aa01 SG |
440 | if (err) { |
441 | dev_err(&pdev->dev, | |
442 | "Failed to register gpiochip %d: %d\n", | |
443 | i, err); | |
330f4e56 | 444 | return err; |
6c17aa01 SG |
445 | } |
446 | } | |
447 | ||
6c17aa01 SG |
448 | return 0; |
449 | } | |
450 | ||
451 | static int __init f7188x_find(int addr, struct f7188x_sio *sio) | |
452 | { | |
453 | int err; | |
454 | u16 devid; | |
455 | ||
456 | err = superio_enter(addr); | |
457 | if (err) | |
458 | return err; | |
459 | ||
460 | err = -ENODEV; | |
461 | devid = superio_inw(addr, SIO_MANID); | |
462 | if (devid != SIO_FINTEK_ID) { | |
463 | pr_debug(DRVNAME ": Not a Fintek device at 0x%08x\n", addr); | |
464 | goto err; | |
465 | } | |
466 | ||
467 | devid = superio_inw(addr, SIO_DEVID); | |
468 | switch (devid) { | |
24ccef35 AB |
469 | case SIO_F71869_ID: |
470 | sio->type = f71869; | |
471 | break; | |
7e960363 AB |
472 | case SIO_F71869A_ID: |
473 | sio->type = f71869a; | |
474 | break; | |
6c17aa01 SG |
475 | case SIO_F71882_ID: |
476 | sio->type = f71882fg; | |
477 | break; | |
d69843e4 MP |
478 | case SIO_F71889A_ID: |
479 | sio->type = f71889a; | |
480 | break; | |
6c17aa01 SG |
481 | case SIO_F71889_ID: |
482 | sio->type = f71889f; | |
483 | break; | |
1920906f PH |
484 | case SIO_F81866_ID: |
485 | sio->type = f81866; | |
486 | break; | |
b0c3e54e SK |
487 | case SIO_F81804_ID: |
488 | sio->type = f81804; | |
489 | break; | |
6c17aa01 SG |
490 | default: |
491 | pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid); | |
492 | goto err; | |
493 | } | |
494 | sio->addr = addr; | |
495 | err = 0; | |
496 | ||
497 | pr_info(DRVNAME ": Found %s at %#x, revision %d\n", | |
498 | f7188x_names[sio->type], | |
499 | (unsigned int) addr, | |
500 | (int) superio_inb(addr, SIO_DEVREV)); | |
501 | ||
502 | err: | |
503 | superio_exit(addr); | |
504 | return err; | |
505 | } | |
506 | ||
507 | static struct platform_device *f7188x_gpio_pdev; | |
508 | ||
509 | static int __init | |
510 | f7188x_gpio_device_add(const struct f7188x_sio *sio) | |
511 | { | |
512 | int err; | |
513 | ||
514 | f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1); | |
515 | if (!f7188x_gpio_pdev) | |
516 | return -ENOMEM; | |
517 | ||
518 | err = platform_device_add_data(f7188x_gpio_pdev, | |
519 | sio, sizeof(*sio)); | |
520 | if (err) { | |
521 | pr_err(DRVNAME "Platform data allocation failed\n"); | |
522 | goto err; | |
523 | } | |
524 | ||
525 | err = platform_device_add(f7188x_gpio_pdev); | |
526 | if (err) { | |
527 | pr_err(DRVNAME "Device addition failed\n"); | |
528 | goto err; | |
529 | } | |
530 | ||
531 | return 0; | |
532 | ||
533 | err: | |
534 | platform_device_put(f7188x_gpio_pdev); | |
535 | ||
536 | return err; | |
537 | } | |
538 | ||
539 | /* | |
3f8f4f19 | 540 | * Try to match a supported Fintek device by reading the (hard-wired) |
6c17aa01 SG |
541 | * configuration I/O ports. If available, then register both the platform |
542 | * device and driver to support the GPIOs. | |
543 | */ | |
544 | ||
545 | static struct platform_driver f7188x_gpio_driver = { | |
546 | .driver = { | |
6c17aa01 SG |
547 | .name = DRVNAME, |
548 | }, | |
549 | .probe = f7188x_gpio_probe, | |
6c17aa01 SG |
550 | }; |
551 | ||
552 | static int __init f7188x_gpio_init(void) | |
553 | { | |
554 | int err; | |
555 | struct f7188x_sio sio; | |
556 | ||
557 | if (f7188x_find(0x2e, &sio) && | |
558 | f7188x_find(0x4e, &sio)) | |
559 | return -ENODEV; | |
560 | ||
561 | err = platform_driver_register(&f7188x_gpio_driver); | |
562 | if (!err) { | |
563 | err = f7188x_gpio_device_add(&sio); | |
564 | if (err) | |
565 | platform_driver_unregister(&f7188x_gpio_driver); | |
566 | } | |
567 | ||
568 | return err; | |
569 | } | |
570 | subsys_initcall(f7188x_gpio_init); | |
571 | ||
572 | static void __exit f7188x_gpio_exit(void) | |
573 | { | |
574 | platform_device_unregister(f7188x_gpio_pdev); | |
575 | platform_driver_unregister(&f7188x_gpio_driver); | |
576 | } | |
577 | module_exit(f7188x_gpio_exit); | |
578 | ||
d69843e4 | 579 | MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71869, F71869A, F71882FG, F71889A, F71889F and F81866"); |
6c17aa01 SG |
580 | MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>"); |
581 | MODULE_LICENSE("GPL"); |