[linux-block.git] / drivers / gpio / gpio-f7188x.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * GPIO driver for Fintek and Nuvoton Super-I/O chips
 *
 * Copyright (C) 2010-2013 LaCie
 *
 * Author: Simon Guinot <simon.guinot@sequanux.org>
 */

#define DRVNAME "gpio-f7188x"
#define pr_fmt(fmt) DRVNAME ": " fmt

#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio/driver.h>
#include <linux/bitops.h>

/*
 * Super-I/O registers
 */
#define SIO_LDSEL		0x07	/* Logical device select */
#define SIO_DEVID		0x20	/* Device ID (2 bytes) */

#define SIO_UNLOCK_KEY		0x87	/* Key to enable Super-I/O */
#define SIO_LOCK_KEY		0xAA	/* Key to disable Super-I/O */

/*
 * Fintek devices.
 */
#define SIO_FINTEK_DEVREV	0x22	/* Fintek Device revision */
#define SIO_FINTEK_MANID	0x23    /* Fintek ID (2 bytes) */

#define SIO_FINTEK_ID		0x1934  /* Manufacturer ID */

#define SIO_F71869_ID		0x0814	/* F71869 chipset ID */
#define SIO_F71869A_ID		0x1007	/* F71869A chipset ID */
#define SIO_F71882_ID		0x0541	/* F71882 chipset ID */
#define SIO_F71889_ID		0x0909	/* F71889 chipset ID */
#define SIO_F71889A_ID		0x1005	/* F71889A chipset ID */
#define SIO_F81866_ID		0x1010	/* F81866 chipset ID */
#define SIO_F81804_ID		0x1502  /* F81804 chipset ID, same for F81966 */
#define SIO_F81865_ID		0x0704	/* F81865 chipset ID */

#define SIO_LD_GPIO_FINTEK	0x06	/* GPIO logical device */

/*
 * Nuvoton devices.
 */
#define SIO_NCT6126D_ID		0xD283  /* NCT6126D chipset ID */

#define SIO_LD_GPIO_NUVOTON	0x07	/* GPIO logical device */


enum chips {
	f71869,
	f71869a,
	f71882fg,
	f71889a,
	f71889f,
	f81866,
	f81804,
	f81865,
	nct6126d,
};

static const char * const f7188x_names[] = {
	"f71869",
	"f71869a",
	"f71882fg",
	"f71889a",
	"f71889f",
	"f81866",
	"f81804",
	"f81865",
	"nct6126d",
};

struct f7188x_sio {
	int addr;
	int device;
	enum chips type;
};

struct f7188x_gpio_bank {
	struct gpio_chip chip;
	unsigned int regbase;
	struct f7188x_gpio_data *data;
};

struct f7188x_gpio_data {
	struct f7188x_sio *sio;
	int nr_bank;
	struct f7188x_gpio_bank *bank;
};

/*
 * Super-I/O functions.
 */

static inline int superio_inb(int base, int reg)
{
	outb(reg, base);
	return inb(base + 1);
}

static int superio_inw(int base, int reg)
{
	int val;

	outb(reg++, base);
	val = inb(base + 1) << 8;
	outb(reg, base);
	val |= inb(base + 1);

	return val;
}

static inline void superio_outb(int base, int reg, int val)
{
	outb(reg, base);
	outb(val, base + 1);
}

static inline int superio_enter(int base)
{
	/* Don't step on other drivers' I/O space by accident. */
	if (!request_muxed_region(base, 2, DRVNAME)) {
		pr_err("I/O address 0x%04x already in use\n", base);
		return -EBUSY;
	}

	/* According to the datasheet the key must be send twice. */
	outb(SIO_UNLOCK_KEY, base);
	outb(SIO_UNLOCK_KEY, base);

	return 0;
}

static inline void superio_select(int base, int ld)
{
	outb(SIO_LDSEL, base);
	outb(ld, base + 1);
}

static inline void superio_exit(int base)
{
	outb(SIO_LOCK_KEY, base);
	release_region(base, 2);
}

/*
 * GPIO chip.
 */

static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset);
static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset);
static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset);
static int f7188x_gpio_direction_out(struct gpio_chip *chip,
				     unsigned offset, int value);
static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value);
static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
				  unsigned long config);

#define F7188X_GPIO_BANK(_ngpio, _regbase, _label)			\
	{								\
		.chip = {						\
			.label            = _label,			\
			.owner            = THIS_MODULE,		\
			.get_direction    = f7188x_gpio_get_direction,	\
			.direction_input  = f7188x_gpio_direction_in,	\
			.get              = f7188x_gpio_get,		\
			.direction_output = f7188x_gpio_direction_out,	\
			.set              = f7188x_gpio_set,		\
			.set_config	  = f7188x_gpio_set_config,	\
			.base             = -1,				\
			.ngpio            = _ngpio,			\
			.can_sleep        = true,			\
		},							\
		.regbase = _regbase,					\
	}

#define f7188x_gpio_dir(base) ((base) + 0)
#define f7188x_gpio_data_out(base) ((base) + 1)
#define f7188x_gpio_data_in(base) ((base) + 2)
/* Output mode register (0:open drain 1:push-pull). */
#define f7188x_gpio_out_mode(base) ((base) + 3)

#define f7188x_gpio_dir_invert(type)	((type) == nct6126d)
#define f7188x_gpio_data_single(type)	((type) == nct6126d)

static struct f7188x_gpio_bank f71869_gpio_bank[] = {
	F7188X_GPIO_BANK(6, 0xF0, DRVNAME "-0"),
	F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-1"),
	F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
	F7188X_GPIO_BANK(8, 0xC0, DRVNAME "-3"),
	F7188X_GPIO_BANK(8, 0xB0, DRVNAME "-4"),
	F7188X_GPIO_BANK(5, 0xA0, DRVNAME "-5"),
	F7188X_GPIO_BANK(6, 0x90, DRVNAME "-6"),
};

static struct f7188x_gpio_bank f71869a_gpio_bank[] = {
	F7188X_GPIO_BANK(6, 0xF0, DRVNAME "-0"),
	F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-1"),
	F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
	F7188X_GPIO_BANK(8, 0xC0, DRVNAME "-3"),
	F7188X_GPIO_BANK(8, 0xB0, DRVNAME "-4"),
	F7188X_GPIO_BANK(5, 0xA0, DRVNAME "-5"),
	F7188X_GPIO_BANK(8, 0x90, DRVNAME "-6"),
	F7188X_GPIO_BANK(8, 0x80, DRVNAME "-7"),
};

static struct f7188x_gpio_bank f71882_gpio_bank[] = {
	F7188X_GPIO_BANK(8, 0xF0, DRVNAME "-0"),
	F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-1"),
	F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
	F7188X_GPIO_BANK(4, 0xC0, DRVNAME "-3"),
	F7188X_GPIO_BANK(4, 0xB0, DRVNAME "-4"),
};

static struct f7188x_gpio_bank f71889a_gpio_bank[] = {
	F7188X_GPIO_BANK(7, 0xF0, DRVNAME "-0"),
	F7188X_GPIO_BANK(7, 0xE0, DRVNAME "-1"),
	F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
	F7188X_GPIO_BANK(8, 0xC0, DRVNAME "-3"),
	F7188X_GPIO_BANK(8, 0xB0, DRVNAME "-4"),
	F7188X_GPIO_BANK(5, 0xA0, DRVNAME "-5"),
	F7188X_GPIO_BANK(8, 0x90, DRVNAME "-6"),
	F7188X_GPIO_BANK(8, 0x80, DRVNAME "-7"),
};

static struct f7188x_gpio_bank f71889_gpio_bank[] = {
	F7188X_GPIO_BANK(7, 0xF0, DRVNAME "-0"),
	F7188X_GPIO_BANK(7, 0xE0, DRVNAME "-1"),
	F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
	F7188X_GPIO_BANK(8, 0xC0, DRVNAME "-3"),
	F7188X_GPIO_BANK(8, 0xB0, DRVNAME "-4"),
	F7188X_GPIO_BANK(5, 0xA0, DRVNAME "-5"),
	F7188X_GPIO_BANK(8, 0x90, DRVNAME "-6"),
	F7188X_GPIO_BANK(8, 0x80, DRVNAME "-7"),
};

static struct f7188x_gpio_bank f81866_gpio_bank[] = {
	F7188X_GPIO_BANK(8, 0xF0, DRVNAME "-0"),
	F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-1"),
	F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
	F7188X_GPIO_BANK(8, 0xC0, DRVNAME "-3"),
	F7188X_GPIO_BANK(8, 0xB0, DRVNAME "-4"),
	F7188X_GPIO_BANK(8, 0xA0, DRVNAME "-5"),
	F7188X_GPIO_BANK(8, 0x90, DRVNAME "-6"),
	F7188X_GPIO_BANK(8, 0x80, DRVNAME "-7"),
	F7188X_GPIO_BANK(8, 0x88, DRVNAME "-8"),
};


static struct f7188x_gpio_bank f81804_gpio_bank[] = {
	F7188X_GPIO_BANK(8, 0xF0, DRVNAME "-0"),
	F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-1"),
	F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
	F7188X_GPIO_BANK(8, 0xA0, DRVNAME "-3"),
	F7188X_GPIO_BANK(8, 0x90, DRVNAME "-4"),
	F7188X_GPIO_BANK(8, 0x80, DRVNAME "-5"),
	F7188X_GPIO_BANK(8, 0x98, DRVNAME "-6"),
};

static struct f7188x_gpio_bank f81865_gpio_bank[] = {
	F7188X_GPIO_BANK(8, 0xF0, DRVNAME "-0"),
	F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-1"),
	F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
	F7188X_GPIO_BANK(8, 0xC0, DRVNAME "-3"),
	F7188X_GPIO_BANK(8, 0xB0, DRVNAME "-4"),
	F7188X_GPIO_BANK(8, 0xA0, DRVNAME "-5"),
	F7188X_GPIO_BANK(5, 0x90, DRVNAME "-6"),
};

static struct f7188x_gpio_bank nct6126d_gpio_bank[] = {
	F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-0"),
	F7188X_GPIO_BANK(8, 0xE4, DRVNAME "-1"),
	F7188X_GPIO_BANK(8, 0xE8, DRVNAME "-2"),
	F7188X_GPIO_BANK(8, 0xEC, DRVNAME "-3"),
	F7188X_GPIO_BANK(8, 0xF0, DRVNAME "-4"),
	F7188X_GPIO_BANK(8, 0xF4, DRVNAME "-5"),
	F7188X_GPIO_BANK(8, 0xF8, DRVNAME "-6"),
	F7188X_GPIO_BANK(8, 0xFC, DRVNAME "-7"),
};

static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
	int err;
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 dir;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, sio->device);

	dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));

	superio_exit(sio->addr);

	if (f7188x_gpio_dir_invert(sio->type))
		dir = ~dir;

	if (dir & BIT(offset))
		return GPIO_LINE_DIRECTION_OUT;

	return GPIO_LINE_DIRECTION_IN;
}

static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
{
	int err;
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 dir;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, sio->device);

	dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));

	if (f7188x_gpio_dir_invert(sio->type))
		dir |= BIT(offset);
	else
		dir &= ~BIT(offset);
	superio_outb(sio->addr, f7188x_gpio_dir(bank->regbase), dir);

	superio_exit(sio->addr);

	return 0;
}

static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	int err;
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 dir, data;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, sio->device);

	dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));
	dir = !!(dir & BIT(offset));
	if (f7188x_gpio_data_single(sio->type) || dir)
		data = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase));
	else
		data = superio_inb(sio->addr, f7188x_gpio_data_in(bank->regbase));

	superio_exit(sio->addr);

	return !!(data & BIT(offset));
}

static int f7188x_gpio_direction_out(struct gpio_chip *chip,
				     unsigned offset, int value)
{
	int err;
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 dir, data_out;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, sio->device);

	data_out = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase));
	if (value)
		data_out |= BIT(offset);
	else
		data_out &= ~BIT(offset);
	superio_outb(sio->addr, f7188x_gpio_data_out(bank->regbase), data_out);

	dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));
	if (f7188x_gpio_dir_invert(sio->type))
		dir &= ~BIT(offset);
	else
		dir |= BIT(offset);
	superio_outb(sio->addr, f7188x_gpio_dir(bank->regbase), dir);

	superio_exit(sio->addr);

	return 0;
}

static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	int err;
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 data_out;

	err = superio_enter(sio->addr);
	if (err)
		return;
	superio_select(sio->addr, sio->device);

	data_out = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase));
	if (value)
		data_out |= BIT(offset);
	else
		data_out &= ~BIT(offset);
	superio_outb(sio->addr, f7188x_gpio_data_out(bank->regbase), data_out);

	superio_exit(sio->addr);
}

static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
				  unsigned long config)
{
	int err;
	enum pin_config_param param = pinconf_to_config_param(config);
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 data;

	if (param != PIN_CONFIG_DRIVE_OPEN_DRAIN &&
	    param != PIN_CONFIG_DRIVE_PUSH_PULL)
		return -ENOTSUPP;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, sio->device);

	data = superio_inb(sio->addr, f7188x_gpio_out_mode(bank->regbase));
	if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN)
		data &= ~BIT(offset);
	else
		data |= BIT(offset);
	superio_outb(sio->addr, f7188x_gpio_out_mode(bank->regbase), data);

	superio_exit(sio->addr);
	return 0;
}

/*
 * Platform device and driver.
 */

static int f7188x_gpio_probe(struct platform_device *pdev)
{
	int err;
	int i;
	struct f7188x_sio *sio = dev_get_platdata(&pdev->dev);
	struct f7188x_gpio_data *data;

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	switch (sio->type) {
	case f71869:
		data->nr_bank = ARRAY_SIZE(f71869_gpio_bank);
		data->bank = f71869_gpio_bank;
		break;
	case f71869a:
		data->nr_bank = ARRAY_SIZE(f71869a_gpio_bank);
		data->bank = f71869a_gpio_bank;
		break;
	case f71882fg:
		data->nr_bank = ARRAY_SIZE(f71882_gpio_bank);
		data->bank = f71882_gpio_bank;
		break;
	case f71889a:
		data->nr_bank = ARRAY_SIZE(f71889a_gpio_bank);
		data->bank = f71889a_gpio_bank;
		break;
	case f71889f:
		data->nr_bank = ARRAY_SIZE(f71889_gpio_bank);
		data->bank = f71889_gpio_bank;
		break;
	case f81866:
		data->nr_bank = ARRAY_SIZE(f81866_gpio_bank);
		data->bank = f81866_gpio_bank;
		break;
	case  f81804:
		data->nr_bank = ARRAY_SIZE(f81804_gpio_bank);
		data->bank = f81804_gpio_bank;
		break;
	case f81865:
		data->nr_bank = ARRAY_SIZE(f81865_gpio_bank);
		data->bank = f81865_gpio_bank;
		break;
	case nct6126d:
		data->nr_bank = ARRAY_SIZE(nct6126d_gpio_bank);
		data->bank = nct6126d_gpio_bank;
		break;
	default:
		return -ENODEV;
	}
	data->sio = sio;

	platform_set_drvdata(pdev, data);

	/* For each GPIO bank, register a GPIO chip. */
	for (i = 0; i < data->nr_bank; i++) {
		struct f7188x_gpio_bank *bank = &data->bank[i];

		bank->chip.parent = &pdev->dev;
		bank->data = data;

		err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
		if (err) {
			dev_err(&pdev->dev,
				"Failed to register gpiochip %d: %d\n",
				i, err);
			return err;
		}
	}

	return 0;
}

static int __init f7188x_find(int addr, struct f7188x_sio *sio)
{
	int err;
	u16 devid;
	u16 manid;

	err = superio_enter(addr);
	if (err)
		return err;

	err = -ENODEV;

	sio->device = SIO_LD_GPIO_FINTEK;
	devid = superio_inw(addr, SIO_DEVID);
	switch (devid) {
	case SIO_F71869_ID:
		sio->type = f71869;
		break;
	case SIO_F71869A_ID:
		sio->type = f71869a;
		break;
	case SIO_F71882_ID:
		sio->type = f71882fg;
		break;
	case SIO_F71889A_ID:
		sio->type = f71889a;
		break;
	case SIO_F71889_ID:
		sio->type = f71889f;
		break;
	case SIO_F81866_ID:
		sio->type = f81866;
		break;
	case SIO_F81804_ID:
		sio->type = f81804;
		break;
	case SIO_F81865_ID:
		sio->type = f81865;
		break;
	case SIO_NCT6126D_ID:
		sio->device = SIO_LD_GPIO_NUVOTON;
		sio->type = nct6126d;
		break;
	default:
		pr_info("Unsupported Fintek device 0x%04x\n", devid);
		goto err;
	}

	/* double check manufacturer where possible */
	if (sio->type != nct6126d) {
		manid = superio_inw(addr, SIO_FINTEK_MANID);
		if (manid != SIO_FINTEK_ID) {
			pr_debug("Not a Fintek device at 0x%08x\n", addr);
			goto err;
		}
	}

	sio->addr = addr;
	err = 0;

	pr_info("Found %s at %#x\n", f7188x_names[sio->type], (unsigned int)addr);
	if (sio->type != nct6126d)
		pr_info("   revision %d\n", superio_inb(addr, SIO_FINTEK_DEVREV));

err:
	superio_exit(addr);
	return err;
}

static struct platform_device *f7188x_gpio_pdev;

static int __init
f7188x_gpio_device_add(const struct f7188x_sio *sio)
{
	int err;

	f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1);
	if (!f7188x_gpio_pdev)
		return -ENOMEM;

	err = platform_device_add_data(f7188x_gpio_pdev,
				       sio, sizeof(*sio));
	if (err) {
		pr_err("Platform data allocation failed\n");
		goto err;
	}

	err = platform_device_add(f7188x_gpio_pdev);
	if (err) {
		pr_err("Device addition failed\n");
		goto err;
	}

	return 0;

err:
	platform_device_put(f7188x_gpio_pdev);

	return err;
}

/*
 * Try to match a supported Fintek device by reading the (hard-wired)
 * configuration I/O ports. If available, then register both the platform
 * device and driver to support the GPIOs.
 */

static struct platform_driver f7188x_gpio_driver = {
	.driver = {
		.name	= DRVNAME,
	},
	.probe		= f7188x_gpio_probe,
};

static int __init f7188x_gpio_init(void)
{
	int err;
	struct f7188x_sio sio;

	if (f7188x_find(0x2e, &sio) &&
	    f7188x_find(0x4e, &sio))
		return -ENODEV;

	err = platform_driver_register(&f7188x_gpio_driver);
	if (!err) {
		err = f7188x_gpio_device_add(&sio);
		if (err)
			platform_driver_unregister(&f7188x_gpio_driver);
	}

	return err;
}
subsys_initcall(f7188x_gpio_init);

static void __exit f7188x_gpio_exit(void)
{
	platform_device_unregister(f7188x_gpio_pdev);
	platform_driver_unregister(&f7188x_gpio_driver);
}
module_exit(f7188x_gpio_exit);

MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71869, F71869A, F71882FG, F71889A, F71889F and F81866");
MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
6c17aa01	2	/*
d0918a84	3	* GPIO driver for Fintek and Nuvoton Super-I/O chips
6c17aa01 SG	4	*
	5	* Copyright (C) 2010-2013 LaCie
	6	*
	7	* Author: Simon Guinot <simon.guinot@sequanux.org>
6c17aa01 SG	8	*/
6c17aa01 SG	9
821d9e1d HS	10	#define DRVNAME "gpio-f7188x"
	11	#define pr_fmt(fmt) DRVNAME ": " fmt
	12
6c17aa01 SG	13	#include <linux/module.h>
	14	#include <linux/init.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/io.h>
148c8642 LW	17	#include <linux/gpio/driver.h>
148c8642 LW	18	#include <linux/bitops.h>
6c17aa01	19
6c17aa01 SG	20	/*
	21	* Super-I/O registers
	22	*/
	23	#define SIO_LDSEL 0x07 /* Logical device select */
	24	#define SIO_DEVID 0x20 /* Device ID (2 bytes) */
6c17aa01	25
6c17aa01 SG	26	#define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
	27	#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
	28
d0918a84 HS	29	/*
	30	* Fintek devices.
	31	*/
	32	#define SIO_FINTEK_DEVREV 0x22 /* Fintek Device revision */
	33	#define SIO_FINTEK_MANID 0x23 /* Fintek ID (2 bytes) */
	34
	35	#define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */
	36
24ccef35	37	#define SIO_F71869_ID 0x0814 /* F71869 chipset ID */
7e960363	38	#define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */
6c17aa01 SG	39	#define SIO_F71882_ID 0x0541 /* F71882 chipset ID */
6c17aa01 SG	40	#define SIO_F71889_ID 0x0909 /* F71889 chipset ID */
d69843e4	41	#define SIO_F71889A_ID 0x1005 /* F71889A chipset ID */
1920906f	42	#define SIO_F81866_ID 0x1010 /* F81866 chipset ID */
d0918a84	43	#define SIO_F81804_ID 0x1502 /* F81804 chipset ID, same for F81966 */
17f96ee2 PJ	44	#define SIO_F81865_ID 0x0704 /* F81865 chipset ID */
17f96ee2 PJ	45
d0918a84 HS	46	#define SIO_LD_GPIO_FINTEK 0x06 /* GPIO logical device */
	47
	48	/*
	49	* Nuvoton devices.
	50	*/
3002b864	51	#define SIO_NCT6126D_ID 0xD283 /* NCT6126D chipset ID */
d0918a84 HS	52
	53	#define SIO_LD_GPIO_NUVOTON 0x07 /* GPIO logical device */
	54
17f96ee2 PJ	55
	56	enum chips {
	57	f71869,
	58	f71869a,
	59	f71882fg,
	60	f71889a,
	61	f71889f,
	62	f81866,
	63	f81804,
	64	f81865,
3002b864	65	nct6126d,
17f96ee2	66	};
6c17aa01 SG	67
6c17aa01 SG	68	static const char * const f7188x_names[] = {
24ccef35	69	"f71869",
7e960363	70	"f71869a",
6c17aa01	71	"f71882fg",
d69843e4	72	"f71889a",
6c17aa01	73	"f71889f",
1920906f	74	"f81866",
b0c3e54e	75	"f81804",
17f96ee2	76	"f81865",
3002b864	77	"nct6126d",
6c17aa01 SG	78	};
	79
	80	struct f7188x_sio {
	81	int addr;
d0918a84	82	int device;
6c17aa01 SG	83	enum chips type;
	84	};
	85
	86	struct f7188x_gpio_bank {
	87	struct gpio_chip chip;
	88	unsigned int regbase;
	89	struct f7188x_gpio_data *data;
	90	};
	91
	92	struct f7188x_gpio_data {
	93	struct f7188x_sio *sio;
	94	int nr_bank;
	95	struct f7188x_gpio_bank *bank;
	96	};
	97
	98	/*
	99	* Super-I/O functions.
	100	*/
	101
	102	static inline int superio_inb(int base, int reg)
	103	{
	104	outb(reg, base);
	105	return inb(base + 1);
	106	}
	107
	108	static int superio_inw(int base, int reg)
	109	{
	110	int val;
	111
	112	outb(reg++, base);
	113	val = inb(base + 1) << 8;
	114	outb(reg, base);
	115	val \|= inb(base + 1);
	116
	117	return val;
	118	}
	119
	120	static inline void superio_outb(int base, int reg, int val)
	121	{
	122	outb(reg, base);
	123	outb(val, base + 1);
	124	}
	125
	126	static inline int superio_enter(int base)
	127	{
	128	/* Don't step on other drivers' I/O space by accident. */
	129	if (!request_muxed_region(base, 2, DRVNAME)) {
821d9e1d	130	pr_err("I/O address 0x%04x already in use\n", base);
6c17aa01 SG	131	return -EBUSY;
	132	}
	133
	134	/* According to the datasheet the key must be send twice. */
	135	outb(SIO_UNLOCK_KEY, base);
	136	outb(SIO_UNLOCK_KEY, base);
	137
	138	return 0;
	139	}
	140
	141	static inline void superio_select(int base, int ld)
	142	{
	143	outb(SIO_LDSEL, base);
	144	outb(ld, base + 1);
	145	}
	146
	147	static inline void superio_exit(int base)
	148	{
	149	outb(SIO_LOCK_KEY, base);
	150	release_region(base, 2);
	151	}
	152
	153	/*
	154	* GPIO chip.
	155	*/
	156
107cdd2d	157	static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset);
6c17aa01 SG	158	static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset);
	159	static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset);
	160	static int f7188x_gpio_direction_out(struct gpio_chip *chip,
	161	unsigned offset, int value);
	162	static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value);
2956b5d9 MW	163	static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
2956b5d9 MW	164	unsigned long config);
6c17aa01	165
3d15d17f	166	#define F7188X_GPIO_BANK(_ngpio, _regbase, _label) \
6c17aa01 SG	167	{ \
6c17aa01 SG	168	.chip = { \
26d88a68	169	.label = _label, \
6c17aa01	170	.owner = THIS_MODULE, \
107cdd2d	171	.get_direction = f7188x_gpio_get_direction, \
6c17aa01 SG	172	.direction_input = f7188x_gpio_direction_in, \
	173	.get = f7188x_gpio_get, \
	174	.direction_output = f7188x_gpio_direction_out, \
	175	.set = f7188x_gpio_set, \
2956b5d9	176	.set_config = f7188x_gpio_set_config, \
3d15d17f	177	.base = -1, \
6c17aa01	178	.ngpio = _ngpio, \
aeccc1b4	179	.can_sleep = true, \
6c17aa01 SG	180	}, \
	181	.regbase = _regbase, \
	182	}
	183
470308d9 HS	184	#define f7188x_gpio_dir(base) ((base) + 0)
	185	#define f7188x_gpio_data_out(base) ((base) + 1)
	186	#define f7188x_gpio_data_in(base) ((base) + 2)
6c17aa01	187	/* Output mode register (0:open drain 1:push-pull). */
470308d9	188	#define f7188x_gpio_out_mode(base) ((base) + 3)
6c17aa01	189
3002b864 HS	190	#define f7188x_gpio_dir_invert(type) ((type) == nct6126d)
3002b864 HS	191	#define f7188x_gpio_data_single(type) ((type) == nct6126d)
d0918a84	192
24ccef35	193	static struct f7188x_gpio_bank f71869_gpio_bank[] = {
3d15d17f	194	F7188X_GPIO_BANK(6, 0xF0, DRVNAME "-0"),
	195	F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-1"),
	196	F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
	197	F7188X_GPIO_BANK(8, 0xC0, DRVNAME "-3"),
	198	F7188X_GPIO_BANK(8, 0xB0, DRVNAME "-4"),
	199	F7188X_GPIO_BANK(5, 0xA0, DRVNAME "-5"),
	200	F7188X_GPIO_BANK(6, 0x90, DRVNAME "-6"),
24ccef35 AB	201	};
24ccef35 AB	202
7e960363	203	static struct f7188x_gpio_bank f71869a_gpio_bank[] = {
3d15d17f	204	F7188X_GPIO_BANK(6, 0xF0, DRVNAME "-0"),
	205	F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-1"),
	206	F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
	207	F7188X_GPIO_BANK(8, 0xC0, DRVNAME "-3"),
	208	F7188X_GPIO_BANK(8, 0xB0, DRVNAME "-4"),
	209	F7188X_GPIO_BANK(5, 0xA0, DRVNAME "-5"),
	210	F7188X_GPIO_BANK(8, 0x90, DRVNAME "-6"),
	211	F7188X_GPIO_BANK(8, 0x80, DRVNAME "-7"),
7e960363 AB	212	};
7e960363 AB	213
6c17aa01	214	static struct f7188x_gpio_bank f71882_gpio_bank[] = {
3d15d17f	215	F7188X_GPIO_BANK(8, 0xF0, DRVNAME "-0"),
	216	F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-1"),
	217	F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
	218	F7188X_GPIO_BANK(4, 0xC0, DRVNAME "-3"),
	219	F7188X_GPIO_BANK(4, 0xB0, DRVNAME "-4"),
6c17aa01 SG	220	};
6c17aa01 SG	221
d69843e4	222	static struct f7188x_gpio_bank f71889a_gpio_bank[] = {
3d15d17f	223	F7188X_GPIO_BANK(7, 0xF0, DRVNAME "-0"),
	224	F7188X_GPIO_BANK(7, 0xE0, DRVNAME "-1"),
	225	F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
	226	F7188X_GPIO_BANK(8, 0xC0, DRVNAME "-3"),
	227	F7188X_GPIO_BANK(8, 0xB0, DRVNAME "-4"),
	228	F7188X_GPIO_BANK(5, 0xA0, DRVNAME "-5"),
	229	F7188X_GPIO_BANK(8, 0x90, DRVNAME "-6"),
	230	F7188X_GPIO_BANK(8, 0x80, DRVNAME "-7"),
d69843e4 MP	231	};
d69843e4 MP	232
6c17aa01	233	static struct f7188x_gpio_bank f71889_gpio_bank[] = {
3d15d17f	234	F7188X_GPIO_BANK(7, 0xF0, DRVNAME "-0"),
	235	F7188X_GPIO_BANK(7, 0xE0, DRVNAME "-1"),
	236	F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
	237	F7188X_GPIO_BANK(8, 0xC0, DRVNAME "-3"),
	238	F7188X_GPIO_BANK(8, 0xB0, DRVNAME "-4"),
	239	F7188X_GPIO_BANK(5, 0xA0, DRVNAME "-5"),
	240	F7188X_GPIO_BANK(8, 0x90, DRVNAME "-6"),
	241	F7188X_GPIO_BANK(8, 0x80, DRVNAME "-7"),
6c17aa01 SG	242	};
6c17aa01 SG	243
1920906f	244	static struct f7188x_gpio_bank f81866_gpio_bank[] = {
3d15d17f	245	F7188X_GPIO_BANK(8, 0xF0, DRVNAME "-0"),
	246	F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-1"),
	247	F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
	248	F7188X_GPIO_BANK(8, 0xC0, DRVNAME "-3"),
	249	F7188X_GPIO_BANK(8, 0xB0, DRVNAME "-4"),
	250	F7188X_GPIO_BANK(8, 0xA0, DRVNAME "-5"),
	251	F7188X_GPIO_BANK(8, 0x90, DRVNAME "-6"),
	252	F7188X_GPIO_BANK(8, 0x80, DRVNAME "-7"),
	253	F7188X_GPIO_BANK(8, 0x88, DRVNAME "-8"),
1920906f PH	254	};
1920906f PH	255
b0c3e54e SK	256
b0c3e54e SK	257	static struct f7188x_gpio_bank f81804_gpio_bank[] = {
3d15d17f	258	F7188X_GPIO_BANK(8, 0xF0, DRVNAME "-0"),
	259	F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-1"),
	260	F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
	261	F7188X_GPIO_BANK(8, 0xA0, DRVNAME "-3"),
	262	F7188X_GPIO_BANK(8, 0x90, DRVNAME "-4"),
	263	F7188X_GPIO_BANK(8, 0x80, DRVNAME "-5"),
	264	F7188X_GPIO_BANK(8, 0x98, DRVNAME "-6"),
b0c3e54e SK	265	};
b0c3e54e SK	266
17f96ee2	267	static struct f7188x_gpio_bank f81865_gpio_bank[] = {
3d15d17f	268	F7188X_GPIO_BANK(8, 0xF0, DRVNAME "-0"),
	269	F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-1"),
	270	F7188X_GPIO_BANK(8, 0xD0, DRVNAME "-2"),
	271	F7188X_GPIO_BANK(8, 0xC0, DRVNAME "-3"),
	272	F7188X_GPIO_BANK(8, 0xB0, DRVNAME "-4"),
	273	F7188X_GPIO_BANK(8, 0xA0, DRVNAME "-5"),
	274	F7188X_GPIO_BANK(5, 0x90, DRVNAME "-6"),
17f96ee2	275	};
b0c3e54e	276
3002b864	277	static struct f7188x_gpio_bank nct6126d_gpio_bank[] = {
3d15d17f	278	F7188X_GPIO_BANK(8, 0xE0, DRVNAME "-0"),
	279	F7188X_GPIO_BANK(8, 0xE4, DRVNAME "-1"),
	280	F7188X_GPIO_BANK(8, 0xE8, DRVNAME "-2"),
	281	F7188X_GPIO_BANK(8, 0xEC, DRVNAME "-3"),
	282	F7188X_GPIO_BANK(8, 0xF0, DRVNAME "-4"),
	283	F7188X_GPIO_BANK(8, 0xF4, DRVNAME "-5"),
	284	F7188X_GPIO_BANK(8, 0xF8, DRVNAME "-6"),
	285	F7188X_GPIO_BANK(8, 0xFC, DRVNAME "-7"),
d0918a84 HS	286	};
d0918a84 HS	287
107cdd2d	288	static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
	289	{
	290	int err;
35a26144	291	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
107cdd2d	292	struct f7188x_sio *sio = bank->data->sio;
	293	u8 dir;
	294
	295	err = superio_enter(sio->addr);
	296	if (err)
	297	return err;
d0918a84	298	superio_select(sio->addr, sio->device);
107cdd2d	299
470308d9	300	dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));
107cdd2d	301
	302	superio_exit(sio->addr);
	303
d0918a84 HS	304	if (f7188x_gpio_dir_invert(sio->type))
	305	dir = ~dir;
	306
	307	if (dir & BIT(offset))
e42615ec MV	308	return GPIO_LINE_DIRECTION_OUT;
	309
	310	return GPIO_LINE_DIRECTION_IN;
107cdd2d	311	}
107cdd2d	312
6c17aa01 SG	313	static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
	314	{
	315	int err;
f372d5f5	316	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
6c17aa01 SG	317	struct f7188x_sio *sio = bank->data->sio;
	318	u8 dir;
	319
	320	err = superio_enter(sio->addr);
	321	if (err)
	322	return err;
d0918a84	323	superio_select(sio->addr, sio->device);
6c17aa01	324
470308d9	325	dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));
d0918a84 HS	326
	327	if (f7188x_gpio_dir_invert(sio->type))
	328	dir \|= BIT(offset);
	329	else
	330	dir &= ~BIT(offset);
470308d9	331	superio_outb(sio->addr, f7188x_gpio_dir(bank->regbase), dir);
6c17aa01 SG	332
	333	superio_exit(sio->addr);
	334
	335	return 0;
	336	}
	337
	338	static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
	339	{
	340	int err;
f372d5f5	341	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
6c17aa01 SG	342	struct f7188x_sio *sio = bank->data->sio;
	343	u8 dir, data;
	344
	345	err = superio_enter(sio->addr);
	346	if (err)
	347	return err;
d0918a84	348	superio_select(sio->addr, sio->device);
6c17aa01	349
470308d9	350	dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));
148c8642	351	dir = !!(dir & BIT(offset));
d0918a84	352	if (f7188x_gpio_data_single(sio->type) \|\| dir)
470308d9	353	data = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase));
6c17aa01	354	else
470308d9	355	data = superio_inb(sio->addr, f7188x_gpio_data_in(bank->regbase));
6c17aa01 SG	356
	357	superio_exit(sio->addr);
	358
148c8642	359	return !!(data & BIT(offset));
6c17aa01 SG	360	}
	361
	362	static int f7188x_gpio_direction_out(struct gpio_chip *chip,
	363	unsigned offset, int value)
	364	{
	365	int err;
f372d5f5	366	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
6c17aa01 SG	367	struct f7188x_sio *sio = bank->data->sio;
	368	u8 dir, data_out;
	369
	370	err = superio_enter(sio->addr);
	371	if (err)
	372	return err;
d0918a84	373	superio_select(sio->addr, sio->device);
6c17aa01	374
470308d9	375	data_out = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase));
6c17aa01	376	if (value)
148c8642	377	data_out \|= BIT(offset);
6c17aa01	378	else
148c8642	379	data_out &= ~BIT(offset);
470308d9	380	superio_outb(sio->addr, f7188x_gpio_data_out(bank->regbase), data_out);
6c17aa01	381
470308d9	382	dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));
d0918a84 HS	383	if (f7188x_gpio_dir_invert(sio->type))
	384	dir &= ~BIT(offset);
	385	else
	386	dir \|= BIT(offset);
470308d9	387	superio_outb(sio->addr, f7188x_gpio_dir(bank->regbase), dir);
6c17aa01 SG	388
	389	superio_exit(sio->addr);
	390
	391	return 0;
	392	}
	393
	394	static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	395	{
	396	int err;
f372d5f5	397	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
6c17aa01 SG	398	struct f7188x_sio *sio = bank->data->sio;
	399	u8 data_out;
	400
	401	err = superio_enter(sio->addr);
	402	if (err)
	403	return;
d0918a84	404	superio_select(sio->addr, sio->device);
6c17aa01	405
470308d9	406	data_out = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase));
6c17aa01	407	if (value)
148c8642	408	data_out \|= BIT(offset);
6c17aa01	409	else
148c8642	410	data_out &= ~BIT(offset);
470308d9	411	superio_outb(sio->addr, f7188x_gpio_data_out(bank->regbase), data_out);
6c17aa01 SG	412
	413	superio_exit(sio->addr);
	414	}
	415
2956b5d9 MW	416	static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
2956b5d9 MW	417	unsigned long config)
f90c6bdb LW	418	{
f90c6bdb LW	419	int err;
2956b5d9	420	enum pin_config_param param = pinconf_to_config_param(config);
f90c6bdb LW	421	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	422	struct f7188x_sio *sio = bank->data->sio;
	423	u8 data;
	424
2956b5d9 MW	425	if (param != PIN_CONFIG_DRIVE_OPEN_DRAIN &&
2956b5d9 MW	426	param != PIN_CONFIG_DRIVE_PUSH_PULL)
f90c6bdb LW	427	return -ENOTSUPP;
	428
	429	err = superio_enter(sio->addr);
	430	if (err)
	431	return err;
d0918a84	432	superio_select(sio->addr, sio->device);
f90c6bdb	433
470308d9	434	data = superio_inb(sio->addr, f7188x_gpio_out_mode(bank->regbase));
2956b5d9	435	if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN)
f90c6bdb LW	436	data &= ~BIT(offset);
	437	else
	438	data \|= BIT(offset);
470308d9	439	superio_outb(sio->addr, f7188x_gpio_out_mode(bank->regbase), data);
f90c6bdb LW	440
	441	superio_exit(sio->addr);
	442	return 0;
	443	}
	444
6c17aa01 SG	445	/*
	446	* Platform device and driver.
	447	*/
	448
	449	static int f7188x_gpio_probe(struct platform_device *pdev)
	450	{
	451	int err;
	452	int i;
ab128afc	453	struct f7188x_sio *sio = dev_get_platdata(&pdev->dev);
6c17aa01 SG	454	struct f7188x_gpio_data *data;
	455
	456	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	457	if (!data)
	458	return -ENOMEM;
	459
	460	switch (sio->type) {
24ccef35 AB	461	case f71869:
	462	data->nr_bank = ARRAY_SIZE(f71869_gpio_bank);
	463	data->bank = f71869_gpio_bank;
	464	break;
7e960363 AB	465	case f71869a:
	466	data->nr_bank = ARRAY_SIZE(f71869a_gpio_bank);
	467	data->bank = f71869a_gpio_bank;
	468	break;
6c17aa01 SG	469	case f71882fg:
	470	data->nr_bank = ARRAY_SIZE(f71882_gpio_bank);
	471	data->bank = f71882_gpio_bank;
	472	break;
d69843e4 MP	473	case f71889a:
	474	data->nr_bank = ARRAY_SIZE(f71889a_gpio_bank);
	475	data->bank = f71889a_gpio_bank;
b86c86aa	476	break;
6c17aa01 SG	477	case f71889f:
	478	data->nr_bank = ARRAY_SIZE(f71889_gpio_bank);
	479	data->bank = f71889_gpio_bank;
	480	break;
1920906f PH	481	case f81866:
	482	data->nr_bank = ARRAY_SIZE(f81866_gpio_bank);
	483	data->bank = f81866_gpio_bank;
	484	break;
b0c3e54e SK	485	case f81804:
	486	data->nr_bank = ARRAY_SIZE(f81804_gpio_bank);
	487	data->bank = f81804_gpio_bank;
	488	break;
17f96ee2 PJ	489	case f81865:
	490	data->nr_bank = ARRAY_SIZE(f81865_gpio_bank);
	491	data->bank = f81865_gpio_bank;
	492	break;
3002b864 HS	493	case nct6126d:
	494	data->nr_bank = ARRAY_SIZE(nct6126d_gpio_bank);
	495	data->bank = nct6126d_gpio_bank;
d0918a84	496	break;
6c17aa01 SG	497	default:
	498	return -ENODEV;
	499	}
	500	data->sio = sio;
	501
	502	platform_set_drvdata(pdev, data);
	503
	504	/* For each GPIO bank, register a GPIO chip. */
	505	for (i = 0; i < data->nr_bank; i++) {
	506	struct f7188x_gpio_bank *bank = &data->bank[i];
	507
58383c78	508	bank->chip.parent = &pdev->dev;
6c17aa01 SG	509	bank->data = data;
6c17aa01 SG	510
330f4e56	511	err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
6c17aa01 SG	512	if (err) {
	513	dev_err(&pdev->dev,
	514	"Failed to register gpiochip %d: %d\n",
	515	i, err);
330f4e56	516	return err;
6c17aa01 SG	517	}
	518	}
	519
6c17aa01 SG	520	return 0;
	521	}
	522
	523	static int __init f7188x_find(int addr, struct f7188x_sio *sio)
	524	{
	525	int err;
	526	u16 devid;
d0918a84	527	u16 manid;
6c17aa01 SG	528
	529	err = superio_enter(addr);
	530	if (err)
	531	return err;
	532
	533	err = -ENODEV;
6c17aa01	534
d0918a84	535	sio->device = SIO_LD_GPIO_FINTEK;
6c17aa01 SG	536	devid = superio_inw(addr, SIO_DEVID);
6c17aa01 SG	537	switch (devid) {
24ccef35 AB	538	case SIO_F71869_ID:
	539	sio->type = f71869;
	540	break;
7e960363 AB	541	case SIO_F71869A_ID:
	542	sio->type = f71869a;
	543	break;
6c17aa01 SG	544	case SIO_F71882_ID:
	545	sio->type = f71882fg;
	546	break;
d69843e4 MP	547	case SIO_F71889A_ID:
	548	sio->type = f71889a;
	549	break;
6c17aa01 SG	550	case SIO_F71889_ID:
	551	sio->type = f71889f;
	552	break;
1920906f PH	553	case SIO_F81866_ID:
	554	sio->type = f81866;
	555	break;
b0c3e54e SK	556	case SIO_F81804_ID:
	557	sio->type = f81804;
	558	break;
17f96ee2 PJ	559	case SIO_F81865_ID:
	560	sio->type = f81865;
	561	break;
3002b864	562	case SIO_NCT6126D_ID:
d0918a84	563	sio->device = SIO_LD_GPIO_NUVOTON;
3002b864	564	sio->type = nct6126d;
d0918a84	565	break;
6c17aa01	566	default:
821d9e1d	567	pr_info("Unsupported Fintek device 0x%04x\n", devid);
6c17aa01 SG	568	goto err;
6c17aa01 SG	569	}
d0918a84 HS	570
d0918a84 HS	571	/* double check manufacturer where possible */
3002b864	572	if (sio->type != nct6126d) {
d0918a84 HS	573	manid = superio_inw(addr, SIO_FINTEK_MANID);
	574	if (manid != SIO_FINTEK_ID) {
	575	pr_debug("Not a Fintek device at 0x%08x\n", addr);
	576	goto err;
	577	}
	578	}
	579
6c17aa01 SG	580	sio->addr = addr;
	581	err = 0;
	582
d0918a84	583	pr_info("Found %s at %#x\n", f7188x_names[sio->type], (unsigned int)addr);
3002b864	584	if (sio->type != nct6126d)
d0918a84	585	pr_info(" revision %d\n", superio_inb(addr, SIO_FINTEK_DEVREV));
6c17aa01 SG	586
	587	err:
	588	superio_exit(addr);
	589	return err;
	590	}
	591
	592	static struct platform_device *f7188x_gpio_pdev;
	593
	594	static int __init
	595	f7188x_gpio_device_add(const struct f7188x_sio *sio)
	596	{
	597	int err;
	598
	599	f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1);
	600	if (!f7188x_gpio_pdev)
	601	return -ENOMEM;
	602
	603	err = platform_device_add_data(f7188x_gpio_pdev,
	604	sio, sizeof(*sio));
	605	if (err) {
821d9e1d	606	pr_err("Platform data allocation failed\n");
6c17aa01 SG	607	goto err;
	608	}
	609
	610	err = platform_device_add(f7188x_gpio_pdev);
	611	if (err) {
821d9e1d	612	pr_err("Device addition failed\n");
6c17aa01 SG	613	goto err;
	614	}
	615
	616	return 0;
	617
	618	err:
	619	platform_device_put(f7188x_gpio_pdev);
	620
	621	return err;
	622	}
	623
	624	/*
3f8f4f19	625	* Try to match a supported Fintek device by reading the (hard-wired)
6c17aa01 SG	626	* configuration I/O ports. If available, then register both the platform
	627	* device and driver to support the GPIOs.
	628	*/
	629
	630	static struct platform_driver f7188x_gpio_driver = {
	631	.driver = {
6c17aa01 SG	632	.name = DRVNAME,
	633	},
	634	.probe = f7188x_gpio_probe,
6c17aa01 SG	635	};
	636
	637	static int __init f7188x_gpio_init(void)
	638	{
	639	int err;
	640	struct f7188x_sio sio;
	641
	642	if (f7188x_find(0x2e, &sio) &&
	643	f7188x_find(0x4e, &sio))
	644	return -ENODEV;
	645
	646	err = platform_driver_register(&f7188x_gpio_driver);
	647	if (!err) {
	648	err = f7188x_gpio_device_add(&sio);
	649	if (err)
	650	platform_driver_unregister(&f7188x_gpio_driver);
	651	}
	652
	653	return err;
	654	}
	655	subsys_initcall(f7188x_gpio_init);
	656
	657	static void __exit f7188x_gpio_exit(void)
	658	{
	659	platform_device_unregister(f7188x_gpio_pdev);
	660	platform_driver_unregister(&f7188x_gpio_driver);
	661	}
	662	module_exit(f7188x_gpio_exit);
	663
d69843e4	664	MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71869, F71869A, F71882FG, F71889A, F71889F and F81866");
6c17aa01 SG	665	MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>");
6c17aa01 SG	666	MODULE_LICENSE("GPL");