[linux-2.6-block.git] / drivers / gpio / gpio-f7188x.c

/*
 * GPIO driver for Fintek Super-I/O F71882 and F71889
 *
 * Copyright (C) 2010-2013 LaCie
 *
 * Author: Simon Guinot <simon.guinot@sequanux.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio.h>

#define DRVNAME "gpio-f7188x"

/*
 * Super-I/O registers
 */
#define SIO_LDSEL		0x07	/* Logical device select */
#define SIO_DEVID		0x20	/* Device ID (2 bytes) */
#define SIO_DEVREV		0x22	/* Device revision */
#define SIO_MANID		0x23	/* Fintek ID (2 bytes) */

#define SIO_LD_GPIO		0x06	/* GPIO logical device */
#define SIO_UNLOCK_KEY		0x87	/* Key to enable Super-I/O */
#define SIO_LOCK_KEY		0xAA	/* Key to disable Super-I/O */

#define SIO_FINTEK_ID		0x1934	/* Manufacturer ID */
#define SIO_F71882_ID		0x0541	/* F71882 chipset ID */
#define SIO_F71889_ID		0x0909	/* F71889 chipset ID */

enum chips { f71882fg, f71889f };

static const char * const f7188x_names[] = {
	"f71882fg",
	"f71889f",
};

struct f7188x_sio {
	int addr;
	enum chips type;
};

struct f7188x_gpio_bank {
	struct gpio_chip chip;
	unsigned int regbase;
	struct f7188x_gpio_data *data;
};

struct f7188x_gpio_data {
	struct f7188x_sio *sio;
	int nr_bank;
	struct f7188x_gpio_bank *bank;
};

/*
 * Super-I/O functions.
 */

static inline int superio_inb(int base, int reg)
{
	outb(reg, base);
	return inb(base + 1);
}

static int superio_inw(int base, int reg)
{
	int val;

	outb(reg++, base);
	val = inb(base + 1) << 8;
	outb(reg, base);
	val |= inb(base + 1);

	return val;
}

static inline void superio_outb(int base, int reg, int val)
{
	outb(reg, base);
	outb(val, base + 1);
}

static inline int superio_enter(int base)
{
	/* Don't step on other drivers' I/O space by accident. */
	if (!request_muxed_region(base, 2, DRVNAME)) {
		pr_err(DRVNAME "I/O address 0x%04x already in use\n", base);
		return -EBUSY;
	}

	/* According to the datasheet the key must be send twice. */
	outb(SIO_UNLOCK_KEY, base);
	outb(SIO_UNLOCK_KEY, base);

	return 0;
}

static inline void superio_select(int base, int ld)
{
	outb(SIO_LDSEL, base);
	outb(ld, base + 1);
}

static inline void superio_exit(int base)
{
	outb(SIO_LOCK_KEY, base);
	release_region(base, 2);
}

/*
 * GPIO chip.
 */

static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset);
static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset);
static int f7188x_gpio_direction_out(struct gpio_chip *chip,
				     unsigned offset, int value);
static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value);

#define F7188X_GPIO_BANK(_base, _ngpio, _regbase)			\
	{								\
		.chip = {						\
			.label            = DRVNAME,			\
			.owner            = THIS_MODULE,		\
			.direction_input  = f7188x_gpio_direction_in,	\
			.get              = f7188x_gpio_get,		\
			.direction_output = f7188x_gpio_direction_out,	\
			.set              = f7188x_gpio_set,		\
			.base             = _base,			\
			.ngpio            = _ngpio,			\
			.can_sleep        = true,			\
		},							\
		.regbase = _regbase,					\
	}

#define gpio_dir(base) (base + 0)
#define gpio_data_out(base) (base + 1)
#define gpio_data_in(base) (base + 2)
/* Output mode register (0:open drain 1:push-pull). */
#define gpio_out_mode(base) (base + 3)

static struct f7188x_gpio_bank f71882_gpio_bank[] = {
	F7188X_GPIO_BANK(0 , 8, 0xF0),
	F7188X_GPIO_BANK(10, 8, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(30, 4, 0xC0),
	F7188X_GPIO_BANK(40, 4, 0xB0),
};

static struct f7188x_gpio_bank f71889_gpio_bank[] = {
	F7188X_GPIO_BANK(0 , 7, 0xF0),
	F7188X_GPIO_BANK(10, 7, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(30, 8, 0xC0),
	F7188X_GPIO_BANK(40, 8, 0xB0),
	F7188X_GPIO_BANK(50, 5, 0xA0),
	F7188X_GPIO_BANK(60, 8, 0x90),
	F7188X_GPIO_BANK(70, 8, 0x80),
};

static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
{
	int err;
	struct f7188x_gpio_bank *bank =
		container_of(chip, struct f7188x_gpio_bank, chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 dir;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, SIO_LD_GPIO);

	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
	dir &= ~(1 << offset);
	superio_outb(sio->addr, gpio_dir(bank->regbase), dir);

	superio_exit(sio->addr);

	return 0;
}

static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	int err;
	struct f7188x_gpio_bank *bank =
		container_of(chip, struct f7188x_gpio_bank, chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 dir, data;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, SIO_LD_GPIO);

	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
	dir = !!(dir & (1 << offset));
	if (dir)
		data = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	else
		data = superio_inb(sio->addr, gpio_data_in(bank->regbase));

	superio_exit(sio->addr);

	return !!(data & 1 << offset);
}

static int f7188x_gpio_direction_out(struct gpio_chip *chip,
				     unsigned offset, int value)
{
	int err;
	struct f7188x_gpio_bank *bank =
		container_of(chip, struct f7188x_gpio_bank, chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 dir, data_out;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, SIO_LD_GPIO);

	data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	if (value)
		data_out |= (1 << offset);
	else
		data_out &= ~(1 << offset);
	superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);

	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
	dir |= (1 << offset);
	superio_outb(sio->addr, gpio_dir(bank->regbase), dir);

	superio_exit(sio->addr);

	return 0;
}

static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	int err;
	struct f7188x_gpio_bank *bank =
		container_of(chip, struct f7188x_gpio_bank, chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 data_out;

	err = superio_enter(sio->addr);
	if (err)
		return;
	superio_select(sio->addr, SIO_LD_GPIO);

	data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	if (value)
		data_out |= (1 << offset);
	else
		data_out &= ~(1 << offset);
	superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);

	superio_exit(sio->addr);
}

/*
 * Platform device and driver.
 */

static int f7188x_gpio_probe(struct platform_device *pdev)
{
	int err;
	int i;
	struct f7188x_sio *sio = pdev->dev.platform_data;
	struct f7188x_gpio_data *data;

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	switch (sio->type) {
	case f71882fg:
		data->nr_bank = ARRAY_SIZE(f71882_gpio_bank);
		data->bank = f71882_gpio_bank;
		break;
	case f71889f:
		data->nr_bank = ARRAY_SIZE(f71889_gpio_bank);
		data->bank = f71889_gpio_bank;
		break;
	default:
		return -ENODEV;
	}
	data->sio = sio;

	platform_set_drvdata(pdev, data);

	/* For each GPIO bank, register a GPIO chip. */
	for (i = 0; i < data->nr_bank; i++) {
		struct f7188x_gpio_bank *bank = &data->bank[i];

		bank->chip.dev = &pdev->dev;
		bank->data = data;

		err = gpiochip_add(&bank->chip);
		if (err) {
			dev_err(&pdev->dev,
				"Failed to register gpiochip %d: %d\n",
				i, err);
			goto err_gpiochip;
		}
	}

	return 0;

err_gpiochip:
	for (i = i - 1; i >= 0; i--) {
		struct f7188x_gpio_bank *bank = &data->bank[i];
		gpiochip_remove(&bank->chip);
	}

	return err;
}

static int f7188x_gpio_remove(struct platform_device *pdev)
{
	int i;
	struct f7188x_gpio_data *data = platform_get_drvdata(pdev);

	for (i = 0; i < data->nr_bank; i++) {
		struct f7188x_gpio_bank *bank = &data->bank[i];
		gpiochip_remove(&bank->chip);
	}

	return 0;
}

static int __init f7188x_find(int addr, struct f7188x_sio *sio)
{
	int err;
	u16 devid;

	err = superio_enter(addr);
	if (err)
		return err;

	err = -ENODEV;
	devid = superio_inw(addr, SIO_MANID);
	if (devid != SIO_FINTEK_ID) {
		pr_debug(DRVNAME ": Not a Fintek device at 0x%08x\n", addr);
		goto err;
	}

	devid = superio_inw(addr, SIO_DEVID);
	switch (devid) {
	case SIO_F71882_ID:
		sio->type = f71882fg;
		break;
	case SIO_F71889_ID:
		sio->type = f71889f;
		break;
	default:
		pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid);
		goto err;
	}
	sio->addr = addr;
	err = 0;

	pr_info(DRVNAME ": Found %s at %#x, revision %d\n",
		f7188x_names[sio->type],
		(unsigned int) addr,
		(int) superio_inb(addr, SIO_DEVREV));

err:
	superio_exit(addr);
	return err;
}

static struct platform_device *f7188x_gpio_pdev;

static int __init
f7188x_gpio_device_add(const struct f7188x_sio *sio)
{
	int err;

	f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1);
	if (!f7188x_gpio_pdev)
		return -ENOMEM;

	err = platform_device_add_data(f7188x_gpio_pdev,
				       sio, sizeof(*sio));
	if (err) {
		pr_err(DRVNAME "Platform data allocation failed\n");
		goto err;
	}

	err = platform_device_add(f7188x_gpio_pdev);
	if (err) {
		pr_err(DRVNAME "Device addition failed\n");
		goto err;
	}

	return 0;

err:
	platform_device_put(f7188x_gpio_pdev);

	return err;
}

/*
 * Try to match a supported Fintech device by reading the (hard-wired)
 * configuration I/O ports. If available, then register both the platform
 * device and driver to support the GPIOs.
 */

static struct platform_driver f7188x_gpio_driver = {
	.driver = {
		.name	= DRVNAME,
	},
	.probe		= f7188x_gpio_probe,
	.remove		= f7188x_gpio_remove,
};

static int __init f7188x_gpio_init(void)
{
	int err;
	struct f7188x_sio sio;

	if (f7188x_find(0x2e, &sio) &&
	    f7188x_find(0x4e, &sio))
		return -ENODEV;

	err = platform_driver_register(&f7188x_gpio_driver);
	if (!err) {
		err = f7188x_gpio_device_add(&sio);
		if (err)
			platform_driver_unregister(&f7188x_gpio_driver);
	}

	return err;
}
subsys_initcall(f7188x_gpio_init);

static void __exit f7188x_gpio_exit(void)
{
	platform_device_unregister(f7188x_gpio_pdev);
	platform_driver_unregister(&f7188x_gpio_driver);
}
module_exit(f7188x_gpio_exit);

MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71882FG and F71889F");
MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
6c17aa01 SG	1	/*
	2	* GPIO driver for Fintek Super-I/O F71882 and F71889
	3	*
	4	* Copyright (C) 2010-2013 LaCie
	5	*
	6	* Author: Simon Guinot <simon.guinot@sequanux.org>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
	13
	14	#include <linux/module.h>
	15	#include <linux/init.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/io.h>
	18	#include <linux/gpio.h>
	19
	20	#define DRVNAME "gpio-f7188x"
	21
	22	/*
	23	* Super-I/O registers
	24	*/
	25	#define SIO_LDSEL 0x07 /* Logical device select */
	26	#define SIO_DEVID 0x20 /* Device ID (2 bytes) */
	27	#define SIO_DEVREV 0x22 /* Device revision */
	28	#define SIO_MANID 0x23 /* Fintek ID (2 bytes) */
	29
	30	#define SIO_LD_GPIO 0x06 /* GPIO logical device */
	31	#define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
	32	#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
	33
	34	#define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */
	35	#define SIO_F71882_ID 0x0541 /* F71882 chipset ID */
	36	#define SIO_F71889_ID 0x0909 /* F71889 chipset ID */
	37
	38	enum chips { f71882fg, f71889f };
	39
	40	static const char * const f7188x_names[] = {
	41	"f71882fg",
	42	"f71889f",
	43	};
	44
	45	struct f7188x_sio {
	46	int addr;
	47	enum chips type;
	48	};
	49
	50	struct f7188x_gpio_bank {
	51	struct gpio_chip chip;
	52	unsigned int regbase;
	53	struct f7188x_gpio_data *data;
	54	};
	55
	56	struct f7188x_gpio_data {
	57	struct f7188x_sio *sio;
	58	int nr_bank;
	59	struct f7188x_gpio_bank *bank;
	60	};
	61
	62	/*
	63	* Super-I/O functions.
	64	*/
65
66	static inline int superio_inb(int base, int reg)
67	{
68	outb(reg, base);
69	return inb(base + 1);
70	}
71
72	static int superio_inw(int base, int reg)
73	{
74	int val;
75
76	outb(reg++, base);
77	val = inb(base + 1) << 8;
78	outb(reg, base);
79	val \|= inb(base + 1);
80
81	return val;
82	}
83
84	static inline void superio_outb(int base, int reg, int val)
85	{
86	outb(reg, base);
87	outb(val, base + 1);
88	}
89
90	static inline int superio_enter(int base)
91	{
92	/* Don't step on other drivers' I/O space by accident. */
93	if (!request_muxed_region(base, 2, DRVNAME)) {
94	pr_err(DRVNAME "I/O address 0x%04x already in use\n", base);
95	return -EBUSY;
96	}
97
98	/* According to the datasheet the key must be send twice. */
99	outb(SIO_UNLOCK_KEY, base);
100	outb(SIO_UNLOCK_KEY, base);
101
102	return 0;
103	}
104
105	static inline void superio_select(int base, int ld)
106	{
107	outb(SIO_LDSEL, base);
108	outb(ld, base + 1);
109	}
110
111	static inline void superio_exit(int base)
112	{
113	outb(SIO_LOCK_KEY, base);
114	release_region(base, 2);
115	}
116
117	/*
118	* GPIO chip.
119	*/
120
121	static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset);
122	static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset);
123	static int f7188x_gpio_direction_out(struct gpio_chip *chip,
124	unsigned offset, int value);
125	static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value);
126
127	#define F7188X_GPIO_BANK(_base, _ngpio, _regbase) \
128	{ \
129	.chip = { \
130	.label = DRVNAME, \
131	.owner = THIS_MODULE, \
132	.direction_input = f7188x_gpio_direction_in, \
133	.get = f7188x_gpio_get, \
134	.direction_output = f7188x_gpio_direction_out, \
135	.set = f7188x_gpio_set, \
136	.base = _base, \
137	.ngpio = _ngpio, \
aeccc1b4	138	.can_sleep = true, \
6c17aa01 SG	139	}, \
	140	.regbase = _regbase, \
	141	}
	142
	143	#define gpio_dir(base) (base + 0)
	144	#define gpio_data_out(base) (base + 1)
	145	#define gpio_data_in(base) (base + 2)
	146	/* Output mode register (0:open drain 1:push-pull). */
	147	#define gpio_out_mode(base) (base + 3)
	148
	149	static struct f7188x_gpio_bank f71882_gpio_bank[] = {
	150	F7188X_GPIO_BANK(0 , 8, 0xF0),
	151	F7188X_GPIO_BANK(10, 8, 0xE0),
	152	F7188X_GPIO_BANK(20, 8, 0xD0),
	153	F7188X_GPIO_BANK(30, 4, 0xC0),
	154	F7188X_GPIO_BANK(40, 4, 0xB0),
	155	};
	156
	157	static struct f7188x_gpio_bank f71889_gpio_bank[] = {
	158	F7188X_GPIO_BANK(0 , 7, 0xF0),
	159	F7188X_GPIO_BANK(10, 7, 0xE0),
	160	F7188X_GPIO_BANK(20, 8, 0xD0),
	161	F7188X_GPIO_BANK(30, 8, 0xC0),
	162	F7188X_GPIO_BANK(40, 8, 0xB0),
	163	F7188X_GPIO_BANK(50, 5, 0xA0),
	164	F7188X_GPIO_BANK(60, 8, 0x90),
	165	F7188X_GPIO_BANK(70, 8, 0x80),
	166	};
	167
	168	static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
	169	{
	170	int err;
	171	struct f7188x_gpio_bank *bank =
	172	container_of(chip, struct f7188x_gpio_bank, chip);
	173	struct f7188x_sio *sio = bank->data->sio;
	174	u8 dir;
	175
	176	err = superio_enter(sio->addr);
	177	if (err)
	178	return err;
	179	superio_select(sio->addr, SIO_LD_GPIO);
	180
	181	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
	182	dir &= ~(1 << offset);
	183	superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
	184
	185	superio_exit(sio->addr);
	186
	187	return 0;
	188	}
	189
	190	static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
	191	{
	192	int err;
	193	struct f7188x_gpio_bank *bank =
	194	container_of(chip, struct f7188x_gpio_bank, chip);
	195	struct f7188x_sio *sio = bank->data->sio;
	196	u8 dir, data;
	197
	198	err = superio_enter(sio->addr);
	199	if (err)
	200	return err;
	201	superio_select(sio->addr, SIO_LD_GPIO);
	202
203	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
204	dir = !!(dir & (1 << offset));
205	if (dir)
206	data = superio_inb(sio->addr, gpio_data_out(bank->regbase));
207	else
208	data = superio_inb(sio->addr, gpio_data_in(bank->regbase));
209
210	superio_exit(sio->addr);
211
212	return !!(data & 1 << offset);
213	}
214
215	static int f7188x_gpio_direction_out(struct gpio_chip *chip,
216	unsigned offset, int value)
217	{
218	int err;
219	struct f7188x_gpio_bank *bank =
220	container_of(chip, struct f7188x_gpio_bank, chip);
221	struct f7188x_sio *sio = bank->data->sio;
222	u8 dir, data_out;
223
224	err = superio_enter(sio->addr);
225	if (err)
226	return err;
227	superio_select(sio->addr, SIO_LD_GPIO);
228
229	data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
230	if (value)
231	data_out \|= (1 << offset);
232	else
233	data_out &= ~(1 << offset);
234	superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
235
236	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
237	dir \|= (1 << offset);
238	superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
239
240	superio_exit(sio->addr);
241
242	return 0;
243	}
244
245	static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
246	{
247	int err;
248	struct f7188x_gpio_bank *bank =
249	container_of(chip, struct f7188x_gpio_bank, chip);
250	struct f7188x_sio *sio = bank->data->sio;
251	u8 data_out;
252
253	err = superio_enter(sio->addr);
254	if (err)
255	return;
256	superio_select(sio->addr, SIO_LD_GPIO);
257
258	data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
259	if (value)
260	data_out \|= (1 << offset);
261	else
262	data_out &= ~(1 << offset);
263	superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
264
265	superio_exit(sio->addr);
266	}
267
268	/*
269	* Platform device and driver.
270	*/
271
272	static int f7188x_gpio_probe(struct platform_device *pdev)
273	{
274	int err;
275	int i;
276	struct f7188x_sio *sio = pdev->dev.platform_data;
277	struct f7188x_gpio_data *data;
278
279	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
280	if (!data)
281	return -ENOMEM;
282
283	switch (sio->type) {
284	case f71882fg:
285	data->nr_bank = ARRAY_SIZE(f71882_gpio_bank);
286	data->bank = f71882_gpio_bank;
287	break;
288	case f71889f:
289	data->nr_bank = ARRAY_SIZE(f71889_gpio_bank);
290	data->bank = f71889_gpio_bank;
291	break;
292	default:
293	return -ENODEV;
294	}
295	data->sio = sio;
296
297	platform_set_drvdata(pdev, data);
298
299	/* For each GPIO bank, register a GPIO chip. */
300	for (i = 0; i < data->nr_bank; i++) {
301	struct f7188x_gpio_bank *bank = &data->bank[i];
302
303	bank->chip.dev = &pdev->dev;
304	bank->data = data;
305
306	err = gpiochip_add(&bank->chip);
307	if (err) {
308	dev_err(&pdev->dev,
309	"Failed to register gpiochip %d: %d\n",
310	i, err);
311	goto err_gpiochip;
312	}
313	}
314
315	return 0;
316
317	err_gpiochip:
318	for (i = i - 1; i >= 0; i--) {
319	struct f7188x_gpio_bank *bank = &data->bank[i];
9f5132ae	320	gpiochip_remove(&bank->chip);
6c17aa01 SG	321	}
	322
	323	return err;
	324	}
	325
	326	static int f7188x_gpio_remove(struct platform_device *pdev)
	327	{
6c17aa01 SG	328	int i;
	329	struct f7188x_gpio_data *data = platform_get_drvdata(pdev);
	330
	331	for (i = 0; i < data->nr_bank; i++) {
	332	struct f7188x_gpio_bank *bank = &data->bank[i];
9f5132ae	333	gpiochip_remove(&bank->chip);
6c17aa01 SG	334	}
	335
	336	return 0;
	337	}
	338
	339	static int __init f7188x_find(int addr, struct f7188x_sio *sio)
	340	{
	341	int err;
	342	u16 devid;
	343
	344	err = superio_enter(addr);
	345	if (err)
	346	return err;
	347
	348	err = -ENODEV;
	349	devid = superio_inw(addr, SIO_MANID);
	350	if (devid != SIO_FINTEK_ID) {
	351	pr_debug(DRVNAME ": Not a Fintek device at 0x%08x\n", addr);
	352	goto err;
	353	}
	354
	355	devid = superio_inw(addr, SIO_DEVID);
	356	switch (devid) {
	357	case SIO_F71882_ID:
	358	sio->type = f71882fg;
	359	break;
	360	case SIO_F71889_ID:
	361	sio->type = f71889f;
	362	break;
	363	default:
	364	pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid);
	365	goto err;
	366	}
	367	sio->addr = addr;
	368	err = 0;
	369
	370	pr_info(DRVNAME ": Found %s at %#x, revision %d\n",
	371	f7188x_names[sio->type],
	372	(unsigned int) addr,
	373	(int) superio_inb(addr, SIO_DEVREV));
	374
	375	err:
	376	superio_exit(addr);
	377	return err;
	378	}
	379
	380	static struct platform_device *f7188x_gpio_pdev;
	381
	382	static int __init
	383	f7188x_gpio_device_add(const struct f7188x_sio *sio)
	384	{
	385	int err;
	386
	387	f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1);
	388	if (!f7188x_gpio_pdev)
	389	return -ENOMEM;
	390
	391	err = platform_device_add_data(f7188x_gpio_pdev,
	392	sio, sizeof(*sio));
	393	if (err) {
	394	pr_err(DRVNAME "Platform data allocation failed\n");
	395	goto err;
	396	}
	397
398	err = platform_device_add(f7188x_gpio_pdev);
399	if (err) {
400	pr_err(DRVNAME "Device addition failed\n");
401	goto err;
402	}
403
404	return 0;
405
406	err:
407	platform_device_put(f7188x_gpio_pdev);
408
409	return err;
410	}
411
412	/*
413	* Try to match a supported Fintech device by reading the (hard-wired)
414	* configuration I/O ports. If available, then register both the platform
415	* device and driver to support the GPIOs.
416	*/
417
418	static struct platform_driver f7188x_gpio_driver = {
419	.driver = {
6c17aa01 SG	420	.name = DRVNAME,
	421	},
	422	.probe = f7188x_gpio_probe,
	423	.remove = f7188x_gpio_remove,
	424	};
	425
	426	static int __init f7188x_gpio_init(void)
	427	{
	428	int err;
	429	struct f7188x_sio sio;
	430
	431	if (f7188x_find(0x2e, &sio) &&
	432	f7188x_find(0x4e, &sio))
	433	return -ENODEV;
	434
	435	err = platform_driver_register(&f7188x_gpio_driver);
	436	if (!err) {
	437	err = f7188x_gpio_device_add(&sio);
	438	if (err)
	439	platform_driver_unregister(&f7188x_gpio_driver);
	440	}
	441
	442	return err;
	443	}
	444	subsys_initcall(f7188x_gpio_init);
	445
	446	static void __exit f7188x_gpio_exit(void)
	447	{
	448	platform_device_unregister(f7188x_gpio_pdev);
	449	platform_driver_unregister(&f7188x_gpio_driver);
	450	}
	451	module_exit(f7188x_gpio_exit);
	452
	453	MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71882FG and F71889F");
	454	MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>");
	455	MODULE_LICENSE("GPL");