[linux-2.6-block.git] / drivers / gpio / gpio-f7188x.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * GPIO driver for Fintek Super-I/O F71869, F71869A, F71882, F71889 and F81866
 *
 * Copyright (C) 2010-2013 LaCie
 *
 * Author: Simon Guinot <simon.guinot@sequanux.org>
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio/driver.h>
#include <linux/bitops.h>

#define DRVNAME "gpio-f7188x"

/*
 * Super-I/O registers
 */
#define SIO_LDSEL		0x07	/* Logical device select */
#define SIO_DEVID		0x20	/* Device ID (2 bytes) */
#define SIO_DEVREV		0x22	/* Device revision */
#define SIO_MANID		0x23	/* Fintek ID (2 bytes) */

#define SIO_LD_GPIO		0x06	/* GPIO logical device */
#define SIO_UNLOCK_KEY		0x87	/* Key to enable Super-I/O */
#define SIO_LOCK_KEY		0xAA	/* Key to disable Super-I/O */

#define SIO_FINTEK_ID		0x1934	/* Manufacturer ID */
#define SIO_F71869_ID		0x0814	/* F71869 chipset ID */
#define SIO_F71869A_ID		0x1007	/* F71869A chipset ID */
#define SIO_F71882_ID		0x0541	/* F71882 chipset ID */
#define SIO_F71889_ID		0x0909	/* F71889 chipset ID */
#define SIO_F71889A_ID		0x1005	/* F71889A chipset ID */
#define SIO_F81866_ID		0x1010	/* F81866 chipset ID */
#define SIO_F81804_ID		0x1502  /* F81804 chipset ID, same for f81966 */
#define SIO_F81865_ID		0x0704	/* F81865 chipset ID */


enum chips {
	f71869,
	f71869a,
	f71882fg,
	f71889a,
	f71889f,
	f81866,
	f81804,
	f81865,
};

static const char * const f7188x_names[] = {
	"f71869",
	"f71869a",
	"f71882fg",
	"f71889a",
	"f71889f",
	"f81866",
	"f81804",
	"f81865",
};

struct f7188x_sio {
	int addr;
	enum chips type;
};

struct f7188x_gpio_bank {
	struct gpio_chip chip;
	unsigned int regbase;
	struct f7188x_gpio_data *data;
};

struct f7188x_gpio_data {
	struct f7188x_sio *sio;
	int nr_bank;
	struct f7188x_gpio_bank *bank;
};

/*
 * Super-I/O functions.
 */

static inline int superio_inb(int base, int reg)
{
	outb(reg, base);
	return inb(base + 1);
}

static int superio_inw(int base, int reg)
{
	int val;

	outb(reg++, base);
	val = inb(base + 1) << 8;
	outb(reg, base);
	val |= inb(base + 1);

	return val;
}

static inline void superio_outb(int base, int reg, int val)
{
	outb(reg, base);
	outb(val, base + 1);
}

static inline int superio_enter(int base)
{
	/* Don't step on other drivers' I/O space by accident. */
	if (!request_muxed_region(base, 2, DRVNAME)) {
		pr_err(DRVNAME "I/O address 0x%04x already in use\n", base);
		return -EBUSY;
	}

	/* According to the datasheet the key must be send twice. */
	outb(SIO_UNLOCK_KEY, base);
	outb(SIO_UNLOCK_KEY, base);

	return 0;
}

static inline void superio_select(int base, int ld)
{
	outb(SIO_LDSEL, base);
	outb(ld, base + 1);
}

static inline void superio_exit(int base)
{
	outb(SIO_LOCK_KEY, base);
	release_region(base, 2);
}

/*
 * GPIO chip.
 */

static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset);
static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset);
static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset);
static int f7188x_gpio_direction_out(struct gpio_chip *chip,
				     unsigned offset, int value);
static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value);
static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
				  unsigned long config);

#define F7188X_GPIO_BANK(_base, _ngpio, _regbase)			\
	{								\
		.chip = {						\
			.label            = DRVNAME,			\
			.owner            = THIS_MODULE,		\
			.get_direction    = f7188x_gpio_get_direction,	\
			.direction_input  = f7188x_gpio_direction_in,	\
			.get              = f7188x_gpio_get,		\
			.direction_output = f7188x_gpio_direction_out,	\
			.set              = f7188x_gpio_set,		\
			.set_config	  = f7188x_gpio_set_config,	\
			.base             = _base,			\
			.ngpio            = _ngpio,			\
			.can_sleep        = true,			\
		},							\
		.regbase = _regbase,					\
	}

#define gpio_dir(base) (base + 0)
#define gpio_data_out(base) (base + 1)
#define gpio_data_in(base) (base + 2)
/* Output mode register (0:open drain 1:push-pull). */
#define gpio_out_mode(base) (base + 3)

static struct f7188x_gpio_bank f71869_gpio_bank[] = {
	F7188X_GPIO_BANK(0, 6, 0xF0),
	F7188X_GPIO_BANK(10, 8, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(30, 8, 0xC0),
	F7188X_GPIO_BANK(40, 8, 0xB0),
	F7188X_GPIO_BANK(50, 5, 0xA0),
	F7188X_GPIO_BANK(60, 6, 0x90),
};

static struct f7188x_gpio_bank f71869a_gpio_bank[] = {
	F7188X_GPIO_BANK(0, 6, 0xF0),
	F7188X_GPIO_BANK(10, 8, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(30, 8, 0xC0),
	F7188X_GPIO_BANK(40, 8, 0xB0),
	F7188X_GPIO_BANK(50, 5, 0xA0),
	F7188X_GPIO_BANK(60, 8, 0x90),
	F7188X_GPIO_BANK(70, 8, 0x80),
};

static struct f7188x_gpio_bank f71882_gpio_bank[] = {
	F7188X_GPIO_BANK(0, 8, 0xF0),
	F7188X_GPIO_BANK(10, 8, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(30, 4, 0xC0),
	F7188X_GPIO_BANK(40, 4, 0xB0),
};

static struct f7188x_gpio_bank f71889a_gpio_bank[] = {
	F7188X_GPIO_BANK(0, 7, 0xF0),
	F7188X_GPIO_BANK(10, 7, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(30, 8, 0xC0),
	F7188X_GPIO_BANK(40, 8, 0xB0),
	F7188X_GPIO_BANK(50, 5, 0xA0),
	F7188X_GPIO_BANK(60, 8, 0x90),
	F7188X_GPIO_BANK(70, 8, 0x80),
};

static struct f7188x_gpio_bank f71889_gpio_bank[] = {
	F7188X_GPIO_BANK(0, 7, 0xF0),
	F7188X_GPIO_BANK(10, 7, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(30, 8, 0xC0),
	F7188X_GPIO_BANK(40, 8, 0xB0),
	F7188X_GPIO_BANK(50, 5, 0xA0),
	F7188X_GPIO_BANK(60, 8, 0x90),
	F7188X_GPIO_BANK(70, 8, 0x80),
};

static struct f7188x_gpio_bank f81866_gpio_bank[] = {
	F7188X_GPIO_BANK(0, 8, 0xF0),
	F7188X_GPIO_BANK(10, 8, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(30, 8, 0xC0),
	F7188X_GPIO_BANK(40, 8, 0xB0),
	F7188X_GPIO_BANK(50, 8, 0xA0),
	F7188X_GPIO_BANK(60, 8, 0x90),
	F7188X_GPIO_BANK(70, 8, 0x80),
	F7188X_GPIO_BANK(80, 8, 0x88),
};


static struct f7188x_gpio_bank f81804_gpio_bank[] = {
	F7188X_GPIO_BANK(0, 8, 0xF0),
	F7188X_GPIO_BANK(10, 8, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(50, 8, 0xA0),
	F7188X_GPIO_BANK(60, 8, 0x90),
	F7188X_GPIO_BANK(70, 8, 0x80),
	F7188X_GPIO_BANK(90, 8, 0x98),
};

static struct f7188x_gpio_bank f81865_gpio_bank[] = {
	F7188X_GPIO_BANK(0, 8, 0xF0),
	F7188X_GPIO_BANK(10, 8, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(30, 8, 0xC0),
	F7188X_GPIO_BANK(40, 8, 0xB0),
	F7188X_GPIO_BANK(50, 8, 0xA0),
	F7188X_GPIO_BANK(60, 5, 0x90),
};

static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
	int err;
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 dir;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, SIO_LD_GPIO);

	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));

	superio_exit(sio->addr);

	if (dir & 1 << offset)
		return GPIO_LINE_DIRECTION_OUT;

	return GPIO_LINE_DIRECTION_IN;
}

static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
{
	int err;
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 dir;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, SIO_LD_GPIO);

	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
	dir &= ~BIT(offset);
	superio_outb(sio->addr, gpio_dir(bank->regbase), dir);

	superio_exit(sio->addr);

	return 0;
}

static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	int err;
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 dir, data;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, SIO_LD_GPIO);

	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
	dir = !!(dir & BIT(offset));
	if (dir)
		data = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	else
		data = superio_inb(sio->addr, gpio_data_in(bank->regbase));

	superio_exit(sio->addr);

	return !!(data & BIT(offset));
}

static int f7188x_gpio_direction_out(struct gpio_chip *chip,
				     unsigned offset, int value)
{
	int err;
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 dir, data_out;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, SIO_LD_GPIO);

	data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	if (value)
		data_out |= BIT(offset);
	else
		data_out &= ~BIT(offset);
	superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);

	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
	dir |= BIT(offset);
	superio_outb(sio->addr, gpio_dir(bank->regbase), dir);

	superio_exit(sio->addr);

	return 0;
}

static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	int err;
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 data_out;

	err = superio_enter(sio->addr);
	if (err)
		return;
	superio_select(sio->addr, SIO_LD_GPIO);

	data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	if (value)
		data_out |= BIT(offset);
	else
		data_out &= ~BIT(offset);
	superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);

	superio_exit(sio->addr);
}

static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
				  unsigned long config)
{
	int err;
	enum pin_config_param param = pinconf_to_config_param(config);
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 data;

	if (param != PIN_CONFIG_DRIVE_OPEN_DRAIN &&
	    param != PIN_CONFIG_DRIVE_PUSH_PULL)
		return -ENOTSUPP;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, SIO_LD_GPIO);

	data = superio_inb(sio->addr, gpio_out_mode(bank->regbase));
	if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN)
		data &= ~BIT(offset);
	else
		data |= BIT(offset);
	superio_outb(sio->addr, gpio_out_mode(bank->regbase), data);

	superio_exit(sio->addr);
	return 0;
}

/*
 * Platform device and driver.
 */

static int f7188x_gpio_probe(struct platform_device *pdev)
{
	int err;
	int i;
	struct f7188x_sio *sio = dev_get_platdata(&pdev->dev);
	struct f7188x_gpio_data *data;

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	switch (sio->type) {
	case f71869:
		data->nr_bank = ARRAY_SIZE(f71869_gpio_bank);
		data->bank = f71869_gpio_bank;
		break;
	case f71869a:
		data->nr_bank = ARRAY_SIZE(f71869a_gpio_bank);
		data->bank = f71869a_gpio_bank;
		break;
	case f71882fg:
		data->nr_bank = ARRAY_SIZE(f71882_gpio_bank);
		data->bank = f71882_gpio_bank;
		break;
	case f71889a:
		data->nr_bank = ARRAY_SIZE(f71889a_gpio_bank);
		data->bank = f71889a_gpio_bank;
		break;
	case f71889f:
		data->nr_bank = ARRAY_SIZE(f71889_gpio_bank);
		data->bank = f71889_gpio_bank;
		break;
	case f81866:
		data->nr_bank = ARRAY_SIZE(f81866_gpio_bank);
		data->bank = f81866_gpio_bank;
		break;
	case  f81804:
		data->nr_bank = ARRAY_SIZE(f81804_gpio_bank);
		data->bank = f81804_gpio_bank;
		break;
	case f81865:
		data->nr_bank = ARRAY_SIZE(f81865_gpio_bank);
		data->bank = f81865_gpio_bank;
		break;
	default:
		return -ENODEV;
	}
	data->sio = sio;

	platform_set_drvdata(pdev, data);

	/* For each GPIO bank, register a GPIO chip. */
	for (i = 0; i < data->nr_bank; i++) {
		struct f7188x_gpio_bank *bank = &data->bank[i];

		bank->chip.parent = &pdev->dev;
		bank->data = data;

		err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
		if (err) {
			dev_err(&pdev->dev,
				"Failed to register gpiochip %d: %d\n",
				i, err);
			return err;
		}
	}

	return 0;
}

static int __init f7188x_find(int addr, struct f7188x_sio *sio)
{
	int err;
	u16 devid;

	err = superio_enter(addr);
	if (err)
		return err;

	err = -ENODEV;
	devid = superio_inw(addr, SIO_MANID);
	if (devid != SIO_FINTEK_ID) {
		pr_debug(DRVNAME ": Not a Fintek device at 0x%08x\n", addr);
		goto err;
	}

	devid = superio_inw(addr, SIO_DEVID);
	switch (devid) {
	case SIO_F71869_ID:
		sio->type = f71869;
		break;
	case SIO_F71869A_ID:
		sio->type = f71869a;
		break;
	case SIO_F71882_ID:
		sio->type = f71882fg;
		break;
	case SIO_F71889A_ID:
		sio->type = f71889a;
		break;
	case SIO_F71889_ID:
		sio->type = f71889f;
		break;
	case SIO_F81866_ID:
		sio->type = f81866;
		break;
	case SIO_F81804_ID:
		sio->type = f81804;
		break;
	case SIO_F81865_ID:
		sio->type = f81865;
		break;
	default:
		pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid);
		goto err;
	}
	sio->addr = addr;
	err = 0;

	pr_info(DRVNAME ": Found %s at %#x, revision %d\n",
		f7188x_names[sio->type],
		(unsigned int) addr,
		(int) superio_inb(addr, SIO_DEVREV));

err:
	superio_exit(addr);
	return err;
}

static struct platform_device *f7188x_gpio_pdev;

static int __init
f7188x_gpio_device_add(const struct f7188x_sio *sio)
{
	int err;

	f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1);
	if (!f7188x_gpio_pdev)
		return -ENOMEM;

	err = platform_device_add_data(f7188x_gpio_pdev,
				       sio, sizeof(*sio));
	if (err) {
		pr_err(DRVNAME "Platform data allocation failed\n");
		goto err;
	}

	err = platform_device_add(f7188x_gpio_pdev);
	if (err) {
		pr_err(DRVNAME "Device addition failed\n");
		goto err;
	}

	return 0;

err:
	platform_device_put(f7188x_gpio_pdev);

	return err;
}

/*
 * Try to match a supported Fintek device by reading the (hard-wired)
 * configuration I/O ports. If available, then register both the platform
 * device and driver to support the GPIOs.
 */

static struct platform_driver f7188x_gpio_driver = {
	.driver = {
		.name	= DRVNAME,
	},
	.probe		= f7188x_gpio_probe,
};

static int __init f7188x_gpio_init(void)
{
	int err;
	struct f7188x_sio sio;

	if (f7188x_find(0x2e, &sio) &&
	    f7188x_find(0x4e, &sio))
		return -ENODEV;

	err = platform_driver_register(&f7188x_gpio_driver);
	if (!err) {
		err = f7188x_gpio_device_add(&sio);
		if (err)
			platform_driver_unregister(&f7188x_gpio_driver);
	}

	return err;
}
subsys_initcall(f7188x_gpio_init);

static void __exit f7188x_gpio_exit(void)
{
	platform_device_unregister(f7188x_gpio_pdev);
	platform_driver_unregister(&f7188x_gpio_driver);
}
module_exit(f7188x_gpio_exit);

MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71869, F71869A, F71882FG, F71889A, F71889F and F81866");
MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
6c17aa01	2	/*
1920906f	3	* GPIO driver for Fintek Super-I/O F71869, F71869A, F71882, F71889 and F81866
6c17aa01 SG	4	*
	5	* Copyright (C) 2010-2013 LaCie
	6	*
	7	* Author: Simon Guinot <simon.guinot@sequanux.org>
6c17aa01 SG	8	*/
	9
	10	#include <linux/module.h>
	11	#include <linux/init.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/io.h>
148c8642 LW	14	#include <linux/gpio/driver.h>
148c8642 LW	15	#include <linux/bitops.h>
6c17aa01 SG	16
	17	#define DRVNAME "gpio-f7188x"
	18
	19	/*
	20	* Super-I/O registers
	21	*/
	22	#define SIO_LDSEL 0x07 /* Logical device select */
	23	#define SIO_DEVID 0x20 /* Device ID (2 bytes) */
	24	#define SIO_DEVREV 0x22 /* Device revision */
	25	#define SIO_MANID 0x23 /* Fintek ID (2 bytes) */
	26
	27	#define SIO_LD_GPIO 0x06 /* GPIO logical device */
	28	#define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
	29	#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
	30
	31	#define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */
24ccef35	32	#define SIO_F71869_ID 0x0814 /* F71869 chipset ID */
7e960363	33	#define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */
6c17aa01 SG	34	#define SIO_F71882_ID 0x0541 /* F71882 chipset ID */
6c17aa01 SG	35	#define SIO_F71889_ID 0x0909 /* F71889 chipset ID */
d69843e4	36	#define SIO_F71889A_ID 0x1005 /* F71889A chipset ID */
1920906f	37	#define SIO_F81866_ID 0x1010 /* F81866 chipset ID */
b0c3e54e	38	#define SIO_F81804_ID 0x1502 /* F81804 chipset ID, same for f81966 */
17f96ee2 PJ	39	#define SIO_F81865_ID 0x0704 /* F81865 chipset ID */
	40
	41
	42	enum chips {
	43	f71869,
	44	f71869a,
	45	f71882fg,
	46	f71889a,
	47	f71889f,
	48	f81866,
	49	f81804,
	50	f81865,
	51	};
6c17aa01 SG	52
6c17aa01 SG	53	static const char * const f7188x_names[] = {
24ccef35	54	"f71869",
7e960363	55	"f71869a",
6c17aa01	56	"f71882fg",
d69843e4	57	"f71889a",
6c17aa01	58	"f71889f",
1920906f	59	"f81866",
b0c3e54e	60	"f81804",
17f96ee2	61	"f81865",
6c17aa01 SG	62	};
	63
	64	struct f7188x_sio {
	65	int addr;
	66	enum chips type;
	67	};
	68
	69	struct f7188x_gpio_bank {
	70	struct gpio_chip chip;
	71	unsigned int regbase;
	72	struct f7188x_gpio_data *data;
	73	};
	74
	75	struct f7188x_gpio_data {
	76	struct f7188x_sio *sio;
	77	int nr_bank;
	78	struct f7188x_gpio_bank *bank;
	79	};
	80
	81	/*
	82	* Super-I/O functions.
	83	*/
	84
	85	static inline int superio_inb(int base, int reg)
	86	{
	87	outb(reg, base);
	88	return inb(base + 1);
	89	}
	90
	91	static int superio_inw(int base, int reg)
	92	{
	93	int val;
	94
	95	outb(reg++, base);
	96	val = inb(base + 1) << 8;
	97	outb(reg, base);
	98	val \|= inb(base + 1);
	99
	100	return val;
	101	}
	102
	103	static inline void superio_outb(int base, int reg, int val)
	104	{
	105	outb(reg, base);
	106	outb(val, base + 1);
	107	}
	108
	109	static inline int superio_enter(int base)
	110	{
	111	/* Don't step on other drivers' I/O space by accident. */
	112	if (!request_muxed_region(base, 2, DRVNAME)) {
	113	pr_err(DRVNAME "I/O address 0x%04x already in use\n", base);
	114	return -EBUSY;
	115	}
	116
	117	/* According to the datasheet the key must be send twice. */
	118	outb(SIO_UNLOCK_KEY, base);
	119	outb(SIO_UNLOCK_KEY, base);
	120
	121	return 0;
	122	}
	123
	124	static inline void superio_select(int base, int ld)
	125	{
126	outb(SIO_LDSEL, base);
127	outb(ld, base + 1);
128	}
129
130	static inline void superio_exit(int base)
131	{
132	outb(SIO_LOCK_KEY, base);
133	release_region(base, 2);
134	}
135
136	/*
137	* GPIO chip.
138	*/
139
107cdd2d	140	static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset);
6c17aa01 SG	141	static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset);
	142	static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset);
	143	static int f7188x_gpio_direction_out(struct gpio_chip *chip,
	144	unsigned offset, int value);
	145	static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value);
2956b5d9 MW	146	static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
2956b5d9 MW	147	unsigned long config);
6c17aa01 SG	148
	149	#define F7188X_GPIO_BANK(_base, _ngpio, _regbase) \
	150	{ \
	151	.chip = { \
	152	.label = DRVNAME, \
	153	.owner = THIS_MODULE, \
107cdd2d	154	.get_direction = f7188x_gpio_get_direction, \
6c17aa01 SG	155	.direction_input = f7188x_gpio_direction_in, \
	156	.get = f7188x_gpio_get, \
	157	.direction_output = f7188x_gpio_direction_out, \
	158	.set = f7188x_gpio_set, \
2956b5d9	159	.set_config = f7188x_gpio_set_config, \
6c17aa01 SG	160	.base = _base, \
6c17aa01 SG	161	.ngpio = _ngpio, \
aeccc1b4	162	.can_sleep = true, \
6c17aa01 SG	163	}, \
	164	.regbase = _regbase, \
	165	}
	166
	167	#define gpio_dir(base) (base + 0)
	168	#define gpio_data_out(base) (base + 1)
	169	#define gpio_data_in(base) (base + 2)
	170	/* Output mode register (0:open drain 1:push-pull). */
	171	#define gpio_out_mode(base) (base + 3)
	172
24ccef35 AB	173	static struct f7188x_gpio_bank f71869_gpio_bank[] = {
	174	F7188X_GPIO_BANK(0, 6, 0xF0),
	175	F7188X_GPIO_BANK(10, 8, 0xE0),
	176	F7188X_GPIO_BANK(20, 8, 0xD0),
	177	F7188X_GPIO_BANK(30, 8, 0xC0),
	178	F7188X_GPIO_BANK(40, 8, 0xB0),
	179	F7188X_GPIO_BANK(50, 5, 0xA0),
	180	F7188X_GPIO_BANK(60, 6, 0x90),
	181	};
	182
7e960363 AB	183	static struct f7188x_gpio_bank f71869a_gpio_bank[] = {
	184	F7188X_GPIO_BANK(0, 6, 0xF0),
	185	F7188X_GPIO_BANK(10, 8, 0xE0),
	186	F7188X_GPIO_BANK(20, 8, 0xD0),
	187	F7188X_GPIO_BANK(30, 8, 0xC0),
	188	F7188X_GPIO_BANK(40, 8, 0xB0),
	189	F7188X_GPIO_BANK(50, 5, 0xA0),
	190	F7188X_GPIO_BANK(60, 8, 0x90),
	191	F7188X_GPIO_BANK(70, 8, 0x80),
	192	};
	193
6c17aa01	194	static struct f7188x_gpio_bank f71882_gpio_bank[] = {
38e003f4	195	F7188X_GPIO_BANK(0, 8, 0xF0),
6c17aa01 SG	196	F7188X_GPIO_BANK(10, 8, 0xE0),
	197	F7188X_GPIO_BANK(20, 8, 0xD0),
	198	F7188X_GPIO_BANK(30, 4, 0xC0),
	199	F7188X_GPIO_BANK(40, 4, 0xB0),
	200	};
	201
d69843e4 MP	202	static struct f7188x_gpio_bank f71889a_gpio_bank[] = {
	203	F7188X_GPIO_BANK(0, 7, 0xF0),
	204	F7188X_GPIO_BANK(10, 7, 0xE0),
	205	F7188X_GPIO_BANK(20, 8, 0xD0),
	206	F7188X_GPIO_BANK(30, 8, 0xC0),
	207	F7188X_GPIO_BANK(40, 8, 0xB0),
	208	F7188X_GPIO_BANK(50, 5, 0xA0),
	209	F7188X_GPIO_BANK(60, 8, 0x90),
	210	F7188X_GPIO_BANK(70, 8, 0x80),
	211	};
	212
6c17aa01	213	static struct f7188x_gpio_bank f71889_gpio_bank[] = {
38e003f4	214	F7188X_GPIO_BANK(0, 7, 0xF0),
6c17aa01 SG	215	F7188X_GPIO_BANK(10, 7, 0xE0),
	216	F7188X_GPIO_BANK(20, 8, 0xD0),
	217	F7188X_GPIO_BANK(30, 8, 0xC0),
	218	F7188X_GPIO_BANK(40, 8, 0xB0),
	219	F7188X_GPIO_BANK(50, 5, 0xA0),
	220	F7188X_GPIO_BANK(60, 8, 0x90),
	221	F7188X_GPIO_BANK(70, 8, 0x80),
	222	};
	223
1920906f PH	224	static struct f7188x_gpio_bank f81866_gpio_bank[] = {
	225	F7188X_GPIO_BANK(0, 8, 0xF0),
	226	F7188X_GPIO_BANK(10, 8, 0xE0),
	227	F7188X_GPIO_BANK(20, 8, 0xD0),
	228	F7188X_GPIO_BANK(30, 8, 0xC0),
	229	F7188X_GPIO_BANK(40, 8, 0xB0),
	230	F7188X_GPIO_BANK(50, 8, 0xA0),
	231	F7188X_GPIO_BANK(60, 8, 0x90),
	232	F7188X_GPIO_BANK(70, 8, 0x80),
	233	F7188X_GPIO_BANK(80, 8, 0x88),
	234	};
	235
b0c3e54e SK	236
	237	static struct f7188x_gpio_bank f81804_gpio_bank[] = {
	238	F7188X_GPIO_BANK(0, 8, 0xF0),
	239	F7188X_GPIO_BANK(10, 8, 0xE0),
	240	F7188X_GPIO_BANK(20, 8, 0xD0),
	241	F7188X_GPIO_BANK(50, 8, 0xA0),
	242	F7188X_GPIO_BANK(60, 8, 0x90),
	243	F7188X_GPIO_BANK(70, 8, 0x80),
	244	F7188X_GPIO_BANK(90, 8, 0x98),
	245	};
	246
17f96ee2 PJ	247	static struct f7188x_gpio_bank f81865_gpio_bank[] = {
	248	F7188X_GPIO_BANK(0, 8, 0xF0),
	249	F7188X_GPIO_BANK(10, 8, 0xE0),
	250	F7188X_GPIO_BANK(20, 8, 0xD0),
	251	F7188X_GPIO_BANK(30, 8, 0xC0),
	252	F7188X_GPIO_BANK(40, 8, 0xB0),
	253	F7188X_GPIO_BANK(50, 8, 0xA0),
	254	F7188X_GPIO_BANK(60, 5, 0x90),
	255	};
b0c3e54e	256
107cdd2d	257	static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
	258	{
	259	int err;
35a26144	260	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
107cdd2d	261	struct f7188x_sio *sio = bank->data->sio;
	262	u8 dir;
	263
	264	err = superio_enter(sio->addr);
	265	if (err)
	266	return err;
	267	superio_select(sio->addr, SIO_LD_GPIO);
	268
	269	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
	270
	271	superio_exit(sio->addr);
	272
e42615ec MV	273	if (dir & 1 << offset)
	274	return GPIO_LINE_DIRECTION_OUT;
	275
	276	return GPIO_LINE_DIRECTION_IN;
107cdd2d	277	}
107cdd2d	278
6c17aa01 SG	279	static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
	280	{
	281	int err;
f372d5f5	282	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
6c17aa01 SG	283	struct f7188x_sio *sio = bank->data->sio;
	284	u8 dir;
	285
	286	err = superio_enter(sio->addr);
	287	if (err)
	288	return err;
	289	superio_select(sio->addr, SIO_LD_GPIO);
	290
	291	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
148c8642	292	dir &= ~BIT(offset);
6c17aa01 SG	293	superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
	294
	295	superio_exit(sio->addr);
	296
	297	return 0;
	298	}
	299
	300	static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
	301	{
	302	int err;
f372d5f5	303	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
6c17aa01 SG	304	struct f7188x_sio *sio = bank->data->sio;
	305	u8 dir, data;
	306
	307	err = superio_enter(sio->addr);
	308	if (err)
	309	return err;
	310	superio_select(sio->addr, SIO_LD_GPIO);
	311
	312	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
148c8642	313	dir = !!(dir & BIT(offset));
6c17aa01 SG	314	if (dir)
	315	data = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	316	else
	317	data = superio_inb(sio->addr, gpio_data_in(bank->regbase));
	318
	319	superio_exit(sio->addr);
	320
148c8642	321	return !!(data & BIT(offset));
6c17aa01 SG	322	}
	323
	324	static int f7188x_gpio_direction_out(struct gpio_chip *chip,
	325	unsigned offset, int value)
	326	{
	327	int err;
f372d5f5	328	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
6c17aa01 SG	329	struct f7188x_sio *sio = bank->data->sio;
	330	u8 dir, data_out;
	331
	332	err = superio_enter(sio->addr);
	333	if (err)
	334	return err;
	335	superio_select(sio->addr, SIO_LD_GPIO);
	336
	337	data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	338	if (value)
148c8642	339	data_out \|= BIT(offset);
6c17aa01	340	else
148c8642	341	data_out &= ~BIT(offset);
6c17aa01 SG	342	superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
	343
	344	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
148c8642	345	dir \|= BIT(offset);
6c17aa01 SG	346	superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
	347
	348	superio_exit(sio->addr);
	349
	350	return 0;
	351	}
	352
	353	static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	354	{
	355	int err;
f372d5f5	356	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
6c17aa01 SG	357	struct f7188x_sio *sio = bank->data->sio;
	358	u8 data_out;
	359
	360	err = superio_enter(sio->addr);
	361	if (err)
	362	return;
	363	superio_select(sio->addr, SIO_LD_GPIO);
	364
	365	data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	366	if (value)
148c8642	367	data_out \|= BIT(offset);
6c17aa01	368	else
148c8642	369	data_out &= ~BIT(offset);
6c17aa01 SG	370	superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
	371
	372	superio_exit(sio->addr);
	373	}
	374
2956b5d9 MW	375	static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset,
2956b5d9 MW	376	unsigned long config)
f90c6bdb LW	377	{
f90c6bdb LW	378	int err;
2956b5d9	379	enum pin_config_param param = pinconf_to_config_param(config);
f90c6bdb LW	380	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	381	struct f7188x_sio *sio = bank->data->sio;
	382	u8 data;
	383
2956b5d9 MW	384	if (param != PIN_CONFIG_DRIVE_OPEN_DRAIN &&
2956b5d9 MW	385	param != PIN_CONFIG_DRIVE_PUSH_PULL)
f90c6bdb LW	386	return -ENOTSUPP;
	387
	388	err = superio_enter(sio->addr);
	389	if (err)
	390	return err;
	391	superio_select(sio->addr, SIO_LD_GPIO);
	392
	393	data = superio_inb(sio->addr, gpio_out_mode(bank->regbase));
2956b5d9	394	if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN)
f90c6bdb LW	395	data &= ~BIT(offset);
	396	else
	397	data \|= BIT(offset);
327819d1	398	superio_outb(sio->addr, gpio_out_mode(bank->regbase), data);
f90c6bdb LW	399
	400	superio_exit(sio->addr);
	401	return 0;
	402	}
	403
6c17aa01 SG	404	/*
	405	* Platform device and driver.
	406	*/
	407
	408	static int f7188x_gpio_probe(struct platform_device *pdev)
	409	{
	410	int err;
	411	int i;
ab128afc	412	struct f7188x_sio *sio = dev_get_platdata(&pdev->dev);
6c17aa01 SG	413	struct f7188x_gpio_data *data;
	414
	415	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	416	if (!data)
	417	return -ENOMEM;
	418
	419	switch (sio->type) {
24ccef35 AB	420	case f71869:
	421	data->nr_bank = ARRAY_SIZE(f71869_gpio_bank);
	422	data->bank = f71869_gpio_bank;
	423	break;
7e960363 AB	424	case f71869a:
	425	data->nr_bank = ARRAY_SIZE(f71869a_gpio_bank);
	426	data->bank = f71869a_gpio_bank;
	427	break;
6c17aa01 SG	428	case f71882fg:
	429	data->nr_bank = ARRAY_SIZE(f71882_gpio_bank);
	430	data->bank = f71882_gpio_bank;
	431	break;
d69843e4 MP	432	case f71889a:
	433	data->nr_bank = ARRAY_SIZE(f71889a_gpio_bank);
	434	data->bank = f71889a_gpio_bank;
b86c86aa	435	break;
6c17aa01 SG	436	case f71889f:
	437	data->nr_bank = ARRAY_SIZE(f71889_gpio_bank);
	438	data->bank = f71889_gpio_bank;
	439	break;
1920906f PH	440	case f81866:
	441	data->nr_bank = ARRAY_SIZE(f81866_gpio_bank);
	442	data->bank = f81866_gpio_bank;
	443	break;
b0c3e54e SK	444	case f81804:
	445	data->nr_bank = ARRAY_SIZE(f81804_gpio_bank);
	446	data->bank = f81804_gpio_bank;
	447	break;
17f96ee2 PJ	448	case f81865:
	449	data->nr_bank = ARRAY_SIZE(f81865_gpio_bank);
	450	data->bank = f81865_gpio_bank;
	451	break;
6c17aa01 SG	452	default:
	453	return -ENODEV;
	454	}
	455	data->sio = sio;
	456
	457	platform_set_drvdata(pdev, data);
	458
	459	/* For each GPIO bank, register a GPIO chip. */
	460	for (i = 0; i < data->nr_bank; i++) {
	461	struct f7188x_gpio_bank *bank = &data->bank[i];
	462
58383c78	463	bank->chip.parent = &pdev->dev;
6c17aa01 SG	464	bank->data = data;
6c17aa01 SG	465
330f4e56	466	err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
6c17aa01 SG	467	if (err) {
	468	dev_err(&pdev->dev,
	469	"Failed to register gpiochip %d: %d\n",
	470	i, err);
330f4e56	471	return err;
6c17aa01 SG	472	}
	473	}
	474
6c17aa01 SG	475	return 0;
	476	}
	477
	478	static int __init f7188x_find(int addr, struct f7188x_sio *sio)
	479	{
	480	int err;
	481	u16 devid;
	482
	483	err = superio_enter(addr);
	484	if (err)
	485	return err;
	486
	487	err = -ENODEV;
	488	devid = superio_inw(addr, SIO_MANID);
	489	if (devid != SIO_FINTEK_ID) {
	490	pr_debug(DRVNAME ": Not a Fintek device at 0x%08x\n", addr);
	491	goto err;
	492	}
	493
	494	devid = superio_inw(addr, SIO_DEVID);
	495	switch (devid) {
24ccef35 AB	496	case SIO_F71869_ID:
	497	sio->type = f71869;
	498	break;
7e960363 AB	499	case SIO_F71869A_ID:
	500	sio->type = f71869a;
	501	break;
6c17aa01 SG	502	case SIO_F71882_ID:
	503	sio->type = f71882fg;
	504	break;
d69843e4 MP	505	case SIO_F71889A_ID:
	506	sio->type = f71889a;
	507	break;
6c17aa01 SG	508	case SIO_F71889_ID:
	509	sio->type = f71889f;
	510	break;
1920906f PH	511	case SIO_F81866_ID:
	512	sio->type = f81866;
	513	break;
b0c3e54e SK	514	case SIO_F81804_ID:
	515	sio->type = f81804;
	516	break;
17f96ee2 PJ	517	case SIO_F81865_ID:
	518	sio->type = f81865;
	519	break;
6c17aa01 SG	520	default:
	521	pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid);
	522	goto err;
	523	}
	524	sio->addr = addr;
	525	err = 0;
	526
	527	pr_info(DRVNAME ": Found %s at %#x, revision %d\n",
	528	f7188x_names[sio->type],
	529	(unsigned int) addr,
	530	(int) superio_inb(addr, SIO_DEVREV));
	531
	532	err:
	533	superio_exit(addr);
	534	return err;
	535	}
	536
	537	static struct platform_device *f7188x_gpio_pdev;
	538
	539	static int __init
	540	f7188x_gpio_device_add(const struct f7188x_sio *sio)
	541	{
	542	int err;
	543
	544	f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1);
	545	if (!f7188x_gpio_pdev)
	546	return -ENOMEM;
	547
	548	err = platform_device_add_data(f7188x_gpio_pdev,
	549	sio, sizeof(*sio));
	550	if (err) {
	551	pr_err(DRVNAME "Platform data allocation failed\n");
	552	goto err;
	553	}
	554
	555	err = platform_device_add(f7188x_gpio_pdev);
	556	if (err) {
	557	pr_err(DRVNAME "Device addition failed\n");
	558	goto err;
	559	}
	560
	561	return 0;
	562
	563	err:
	564	platform_device_put(f7188x_gpio_pdev);
	565
	566	return err;
	567	}
	568
	569	/*
3f8f4f19	570	* Try to match a supported Fintek device by reading the (hard-wired)
6c17aa01 SG	571	* configuration I/O ports. If available, then register both the platform
	572	* device and driver to support the GPIOs.
	573	*/
	574
	575	static struct platform_driver f7188x_gpio_driver = {
	576	.driver = {
6c17aa01 SG	577	.name = DRVNAME,
	578	},
	579	.probe = f7188x_gpio_probe,
6c17aa01 SG	580	};
	581
	582	static int __init f7188x_gpio_init(void)
	583	{
	584	int err;
	585	struct f7188x_sio sio;
	586
	587	if (f7188x_find(0x2e, &sio) &&
	588	f7188x_find(0x4e, &sio))
	589	return -ENODEV;
	590
	591	err = platform_driver_register(&f7188x_gpio_driver);
	592	if (!err) {
	593	err = f7188x_gpio_device_add(&sio);
	594	if (err)
	595	platform_driver_unregister(&f7188x_gpio_driver);
	596	}
	597
	598	return err;
	599	}
	600	subsys_initcall(f7188x_gpio_init);
	601
	602	static void __exit f7188x_gpio_exit(void)
	603	{
	604	platform_device_unregister(f7188x_gpio_pdev);
	605	platform_driver_unregister(&f7188x_gpio_driver);
	606	}
	607	module_exit(f7188x_gpio_exit);
	608
d69843e4	609	MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71869, F71869A, F71882FG, F71889A, F71889F and F81866");
6c17aa01 SG	610	MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>");
6c17aa01 SG	611	MODULE_LICENSE("GPL");