Commit | Line | Data |
---|---|---|
6c17aa01 | 1 | /* |
1920906f | 2 | * GPIO driver for Fintek Super-I/O F71869, F71869A, F71882, F71889 and F81866 |
6c17aa01 SG |
3 | * |
4 | * Copyright (C) 2010-2013 LaCie | |
5 | * | |
6 | * Author: Simon Guinot <simon.guinot@sequanux.org> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/io.h> | |
148c8642 LW |
18 | #include <linux/gpio/driver.h> |
19 | #include <linux/bitops.h> | |
6c17aa01 SG |
20 | |
21 | #define DRVNAME "gpio-f7188x" | |
22 | ||
23 | /* | |
24 | * Super-I/O registers | |
25 | */ | |
26 | #define SIO_LDSEL 0x07 /* Logical device select */ | |
27 | #define SIO_DEVID 0x20 /* Device ID (2 bytes) */ | |
28 | #define SIO_DEVREV 0x22 /* Device revision */ | |
29 | #define SIO_MANID 0x23 /* Fintek ID (2 bytes) */ | |
30 | ||
31 | #define SIO_LD_GPIO 0x06 /* GPIO logical device */ | |
32 | #define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */ | |
33 | #define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */ | |
34 | ||
35 | #define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */ | |
24ccef35 | 36 | #define SIO_F71869_ID 0x0814 /* F71869 chipset ID */ |
7e960363 | 37 | #define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */ |
6c17aa01 SG |
38 | #define SIO_F71882_ID 0x0541 /* F71882 chipset ID */ |
39 | #define SIO_F71889_ID 0x0909 /* F71889 chipset ID */ | |
d69843e4 | 40 | #define SIO_F71889A_ID 0x1005 /* F71889A chipset ID */ |
1920906f | 41 | #define SIO_F81866_ID 0x1010 /* F81866 chipset ID */ |
b0c3e54e | 42 | #define SIO_F81804_ID 0x1502 /* F81804 chipset ID, same for f81966 */ |
6c17aa01 | 43 | |
b0c3e54e SK |
44 | |
45 | enum chips { f71869, f71869a, f71882fg, f71889a, f71889f, f81866, f81804 }; | |
6c17aa01 SG |
46 | |
47 | static const char * const f7188x_names[] = { | |
24ccef35 | 48 | "f71869", |
7e960363 | 49 | "f71869a", |
6c17aa01 | 50 | "f71882fg", |
d69843e4 | 51 | "f71889a", |
6c17aa01 | 52 | "f71889f", |
1920906f | 53 | "f81866", |
b0c3e54e | 54 | "f81804", |
6c17aa01 SG |
55 | }; |
56 | ||
57 | struct f7188x_sio { | |
58 | int addr; | |
59 | enum chips type; | |
60 | }; | |
61 | ||
62 | struct f7188x_gpio_bank { | |
63 | struct gpio_chip chip; | |
64 | unsigned int regbase; | |
65 | struct f7188x_gpio_data *data; | |
66 | }; | |
67 | ||
68 | struct f7188x_gpio_data { | |
69 | struct f7188x_sio *sio; | |
70 | int nr_bank; | |
71 | struct f7188x_gpio_bank *bank; | |
72 | }; | |
73 | ||
74 | /* | |
75 | * Super-I/O functions. | |
76 | */ | |
77 | ||
78 | static inline int superio_inb(int base, int reg) | |
79 | { | |
80 | outb(reg, base); | |
81 | return inb(base + 1); | |
82 | } | |
83 | ||
84 | static int superio_inw(int base, int reg) | |
85 | { | |
86 | int val; | |
87 | ||
88 | outb(reg++, base); | |
89 | val = inb(base + 1) << 8; | |
90 | outb(reg, base); | |
91 | val |= inb(base + 1); | |
92 | ||
93 | return val; | |
94 | } | |
95 | ||
96 | static inline void superio_outb(int base, int reg, int val) | |
97 | { | |
98 | outb(reg, base); | |
99 | outb(val, base + 1); | |
100 | } | |
101 | ||
102 | static inline int superio_enter(int base) | |
103 | { | |
104 | /* Don't step on other drivers' I/O space by accident. */ | |
105 | if (!request_muxed_region(base, 2, DRVNAME)) { | |
106 | pr_err(DRVNAME "I/O address 0x%04x already in use\n", base); | |
107 | return -EBUSY; | |
108 | } | |
109 | ||
110 | /* According to the datasheet the key must be send twice. */ | |
111 | outb(SIO_UNLOCK_KEY, base); | |
112 | outb(SIO_UNLOCK_KEY, base); | |
113 | ||
114 | return 0; | |
115 | } | |
116 | ||
117 | static inline void superio_select(int base, int ld) | |
118 | { | |
119 | outb(SIO_LDSEL, base); | |
120 | outb(ld, base + 1); | |
121 | } | |
122 | ||
123 | static inline void superio_exit(int base) | |
124 | { | |
125 | outb(SIO_LOCK_KEY, base); | |
126 | release_region(base, 2); | |
127 | } | |
128 | ||
129 | /* | |
130 | * GPIO chip. | |
131 | */ | |
132 | ||
107cdd2d | 133 | static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset); |
6c17aa01 SG |
134 | static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset); |
135 | static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset); | |
136 | static int f7188x_gpio_direction_out(struct gpio_chip *chip, | |
137 | unsigned offset, int value); | |
138 | static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value); | |
2956b5d9 MW |
139 | static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset, |
140 | unsigned long config); | |
6c17aa01 SG |
141 | |
142 | #define F7188X_GPIO_BANK(_base, _ngpio, _regbase) \ | |
143 | { \ | |
144 | .chip = { \ | |
145 | .label = DRVNAME, \ | |
146 | .owner = THIS_MODULE, \ | |
107cdd2d | 147 | .get_direction = f7188x_gpio_get_direction, \ |
6c17aa01 SG |
148 | .direction_input = f7188x_gpio_direction_in, \ |
149 | .get = f7188x_gpio_get, \ | |
150 | .direction_output = f7188x_gpio_direction_out, \ | |
151 | .set = f7188x_gpio_set, \ | |
2956b5d9 | 152 | .set_config = f7188x_gpio_set_config, \ |
6c17aa01 SG |
153 | .base = _base, \ |
154 | .ngpio = _ngpio, \ | |
aeccc1b4 | 155 | .can_sleep = true, \ |
6c17aa01 SG |
156 | }, \ |
157 | .regbase = _regbase, \ | |
158 | } | |
159 | ||
160 | #define gpio_dir(base) (base + 0) | |
161 | #define gpio_data_out(base) (base + 1) | |
162 | #define gpio_data_in(base) (base + 2) | |
163 | /* Output mode register (0:open drain 1:push-pull). */ | |
164 | #define gpio_out_mode(base) (base + 3) | |
165 | ||
24ccef35 AB |
166 | static struct f7188x_gpio_bank f71869_gpio_bank[] = { |
167 | F7188X_GPIO_BANK(0, 6, 0xF0), | |
168 | F7188X_GPIO_BANK(10, 8, 0xE0), | |
169 | F7188X_GPIO_BANK(20, 8, 0xD0), | |
170 | F7188X_GPIO_BANK(30, 8, 0xC0), | |
171 | F7188X_GPIO_BANK(40, 8, 0xB0), | |
172 | F7188X_GPIO_BANK(50, 5, 0xA0), | |
173 | F7188X_GPIO_BANK(60, 6, 0x90), | |
174 | }; | |
175 | ||
7e960363 AB |
176 | static struct f7188x_gpio_bank f71869a_gpio_bank[] = { |
177 | F7188X_GPIO_BANK(0, 6, 0xF0), | |
178 | F7188X_GPIO_BANK(10, 8, 0xE0), | |
179 | F7188X_GPIO_BANK(20, 8, 0xD0), | |
180 | F7188X_GPIO_BANK(30, 8, 0xC0), | |
181 | F7188X_GPIO_BANK(40, 8, 0xB0), | |
182 | F7188X_GPIO_BANK(50, 5, 0xA0), | |
183 | F7188X_GPIO_BANK(60, 8, 0x90), | |
184 | F7188X_GPIO_BANK(70, 8, 0x80), | |
185 | }; | |
186 | ||
6c17aa01 | 187 | static struct f7188x_gpio_bank f71882_gpio_bank[] = { |
38e003f4 | 188 | F7188X_GPIO_BANK(0, 8, 0xF0), |
6c17aa01 SG |
189 | F7188X_GPIO_BANK(10, 8, 0xE0), |
190 | F7188X_GPIO_BANK(20, 8, 0xD0), | |
191 | F7188X_GPIO_BANK(30, 4, 0xC0), | |
192 | F7188X_GPIO_BANK(40, 4, 0xB0), | |
193 | }; | |
194 | ||
d69843e4 MP |
195 | static struct f7188x_gpio_bank f71889a_gpio_bank[] = { |
196 | F7188X_GPIO_BANK(0, 7, 0xF0), | |
197 | F7188X_GPIO_BANK(10, 7, 0xE0), | |
198 | F7188X_GPIO_BANK(20, 8, 0xD0), | |
199 | F7188X_GPIO_BANK(30, 8, 0xC0), | |
200 | F7188X_GPIO_BANK(40, 8, 0xB0), | |
201 | F7188X_GPIO_BANK(50, 5, 0xA0), | |
202 | F7188X_GPIO_BANK(60, 8, 0x90), | |
203 | F7188X_GPIO_BANK(70, 8, 0x80), | |
204 | }; | |
205 | ||
6c17aa01 | 206 | static struct f7188x_gpio_bank f71889_gpio_bank[] = { |
38e003f4 | 207 | F7188X_GPIO_BANK(0, 7, 0xF0), |
6c17aa01 SG |
208 | F7188X_GPIO_BANK(10, 7, 0xE0), |
209 | F7188X_GPIO_BANK(20, 8, 0xD0), | |
210 | F7188X_GPIO_BANK(30, 8, 0xC0), | |
211 | F7188X_GPIO_BANK(40, 8, 0xB0), | |
212 | F7188X_GPIO_BANK(50, 5, 0xA0), | |
213 | F7188X_GPIO_BANK(60, 8, 0x90), | |
214 | F7188X_GPIO_BANK(70, 8, 0x80), | |
215 | }; | |
216 | ||
1920906f PH |
217 | static struct f7188x_gpio_bank f81866_gpio_bank[] = { |
218 | F7188X_GPIO_BANK(0, 8, 0xF0), | |
219 | F7188X_GPIO_BANK(10, 8, 0xE0), | |
220 | F7188X_GPIO_BANK(20, 8, 0xD0), | |
221 | F7188X_GPIO_BANK(30, 8, 0xC0), | |
222 | F7188X_GPIO_BANK(40, 8, 0xB0), | |
223 | F7188X_GPIO_BANK(50, 8, 0xA0), | |
224 | F7188X_GPIO_BANK(60, 8, 0x90), | |
225 | F7188X_GPIO_BANK(70, 8, 0x80), | |
226 | F7188X_GPIO_BANK(80, 8, 0x88), | |
227 | }; | |
228 | ||
b0c3e54e SK |
229 | |
230 | static struct f7188x_gpio_bank f81804_gpio_bank[] = { | |
231 | F7188X_GPIO_BANK(0, 8, 0xF0), | |
232 | F7188X_GPIO_BANK(10, 8, 0xE0), | |
233 | F7188X_GPIO_BANK(20, 8, 0xD0), | |
234 | F7188X_GPIO_BANK(50, 8, 0xA0), | |
235 | F7188X_GPIO_BANK(60, 8, 0x90), | |
236 | F7188X_GPIO_BANK(70, 8, 0x80), | |
237 | F7188X_GPIO_BANK(90, 8, 0x98), | |
238 | }; | |
239 | ||
240 | ||
107cdd2d | 241 | static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
242 | { | |
243 | int err; | |
35a26144 | 244 | struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); |
107cdd2d | 245 | struct f7188x_sio *sio = bank->data->sio; |
246 | u8 dir; | |
247 | ||
248 | err = superio_enter(sio->addr); | |
249 | if (err) | |
250 | return err; | |
251 | superio_select(sio->addr, SIO_LD_GPIO); | |
252 | ||
253 | dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); | |
254 | ||
255 | superio_exit(sio->addr); | |
256 | ||
257 | return !(dir & 1 << offset); | |
258 | } | |
259 | ||
6c17aa01 SG |
260 | static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset) |
261 | { | |
262 | int err; | |
f372d5f5 | 263 | struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); |
6c17aa01 SG |
264 | struct f7188x_sio *sio = bank->data->sio; |
265 | u8 dir; | |
266 | ||
267 | err = superio_enter(sio->addr); | |
268 | if (err) | |
269 | return err; | |
270 | superio_select(sio->addr, SIO_LD_GPIO); | |
271 | ||
272 | dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); | |
148c8642 | 273 | dir &= ~BIT(offset); |
6c17aa01 SG |
274 | superio_outb(sio->addr, gpio_dir(bank->regbase), dir); |
275 | ||
276 | superio_exit(sio->addr); | |
277 | ||
278 | return 0; | |
279 | } | |
280 | ||
281 | static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset) | |
282 | { | |
283 | int err; | |
f372d5f5 | 284 | struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); |
6c17aa01 SG |
285 | struct f7188x_sio *sio = bank->data->sio; |
286 | u8 dir, data; | |
287 | ||
288 | err = superio_enter(sio->addr); | |
289 | if (err) | |
290 | return err; | |
291 | superio_select(sio->addr, SIO_LD_GPIO); | |
292 | ||
293 | dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); | |
148c8642 | 294 | dir = !!(dir & BIT(offset)); |
6c17aa01 SG |
295 | if (dir) |
296 | data = superio_inb(sio->addr, gpio_data_out(bank->regbase)); | |
297 | else | |
298 | data = superio_inb(sio->addr, gpio_data_in(bank->regbase)); | |
299 | ||
300 | superio_exit(sio->addr); | |
301 | ||
148c8642 | 302 | return !!(data & BIT(offset)); |
6c17aa01 SG |
303 | } |
304 | ||
305 | static int f7188x_gpio_direction_out(struct gpio_chip *chip, | |
306 | unsigned offset, int value) | |
307 | { | |
308 | int err; | |
f372d5f5 | 309 | struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); |
6c17aa01 SG |
310 | struct f7188x_sio *sio = bank->data->sio; |
311 | u8 dir, data_out; | |
312 | ||
313 | err = superio_enter(sio->addr); | |
314 | if (err) | |
315 | return err; | |
316 | superio_select(sio->addr, SIO_LD_GPIO); | |
317 | ||
318 | data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase)); | |
319 | if (value) | |
148c8642 | 320 | data_out |= BIT(offset); |
6c17aa01 | 321 | else |
148c8642 | 322 | data_out &= ~BIT(offset); |
6c17aa01 SG |
323 | superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out); |
324 | ||
325 | dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); | |
148c8642 | 326 | dir |= BIT(offset); |
6c17aa01 SG |
327 | superio_outb(sio->addr, gpio_dir(bank->regbase), dir); |
328 | ||
329 | superio_exit(sio->addr); | |
330 | ||
331 | return 0; | |
332 | } | |
333 | ||
334 | static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
335 | { | |
336 | int err; | |
f372d5f5 | 337 | struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); |
6c17aa01 SG |
338 | struct f7188x_sio *sio = bank->data->sio; |
339 | u8 data_out; | |
340 | ||
341 | err = superio_enter(sio->addr); | |
342 | if (err) | |
343 | return; | |
344 | superio_select(sio->addr, SIO_LD_GPIO); | |
345 | ||
346 | data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase)); | |
347 | if (value) | |
148c8642 | 348 | data_out |= BIT(offset); |
6c17aa01 | 349 | else |
148c8642 | 350 | data_out &= ~BIT(offset); |
6c17aa01 SG |
351 | superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out); |
352 | ||
353 | superio_exit(sio->addr); | |
354 | } | |
355 | ||
2956b5d9 MW |
356 | static int f7188x_gpio_set_config(struct gpio_chip *chip, unsigned offset, |
357 | unsigned long config) | |
f90c6bdb LW |
358 | { |
359 | int err; | |
2956b5d9 | 360 | enum pin_config_param param = pinconf_to_config_param(config); |
f90c6bdb LW |
361 | struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); |
362 | struct f7188x_sio *sio = bank->data->sio; | |
363 | u8 data; | |
364 | ||
2956b5d9 MW |
365 | if (param != PIN_CONFIG_DRIVE_OPEN_DRAIN && |
366 | param != PIN_CONFIG_DRIVE_PUSH_PULL) | |
f90c6bdb LW |
367 | return -ENOTSUPP; |
368 | ||
369 | err = superio_enter(sio->addr); | |
370 | if (err) | |
371 | return err; | |
372 | superio_select(sio->addr, SIO_LD_GPIO); | |
373 | ||
374 | data = superio_inb(sio->addr, gpio_out_mode(bank->regbase)); | |
2956b5d9 | 375 | if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN) |
f90c6bdb LW |
376 | data &= ~BIT(offset); |
377 | else | |
378 | data |= BIT(offset); | |
327819d1 | 379 | superio_outb(sio->addr, gpio_out_mode(bank->regbase), data); |
f90c6bdb LW |
380 | |
381 | superio_exit(sio->addr); | |
382 | return 0; | |
383 | } | |
384 | ||
6c17aa01 SG |
385 | /* |
386 | * Platform device and driver. | |
387 | */ | |
388 | ||
389 | static int f7188x_gpio_probe(struct platform_device *pdev) | |
390 | { | |
391 | int err; | |
392 | int i; | |
ab128afc | 393 | struct f7188x_sio *sio = dev_get_platdata(&pdev->dev); |
6c17aa01 SG |
394 | struct f7188x_gpio_data *data; |
395 | ||
396 | data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); | |
397 | if (!data) | |
398 | return -ENOMEM; | |
399 | ||
400 | switch (sio->type) { | |
24ccef35 AB |
401 | case f71869: |
402 | data->nr_bank = ARRAY_SIZE(f71869_gpio_bank); | |
403 | data->bank = f71869_gpio_bank; | |
404 | break; | |
7e960363 AB |
405 | case f71869a: |
406 | data->nr_bank = ARRAY_SIZE(f71869a_gpio_bank); | |
407 | data->bank = f71869a_gpio_bank; | |
408 | break; | |
6c17aa01 SG |
409 | case f71882fg: |
410 | data->nr_bank = ARRAY_SIZE(f71882_gpio_bank); | |
411 | data->bank = f71882_gpio_bank; | |
412 | break; | |
d69843e4 MP |
413 | case f71889a: |
414 | data->nr_bank = ARRAY_SIZE(f71889a_gpio_bank); | |
415 | data->bank = f71889a_gpio_bank; | |
b86c86aa | 416 | break; |
6c17aa01 SG |
417 | case f71889f: |
418 | data->nr_bank = ARRAY_SIZE(f71889_gpio_bank); | |
419 | data->bank = f71889_gpio_bank; | |
420 | break; | |
1920906f PH |
421 | case f81866: |
422 | data->nr_bank = ARRAY_SIZE(f81866_gpio_bank); | |
423 | data->bank = f81866_gpio_bank; | |
424 | break; | |
b0c3e54e SK |
425 | case f81804: |
426 | data->nr_bank = ARRAY_SIZE(f81804_gpio_bank); | |
427 | data->bank = f81804_gpio_bank; | |
428 | break; | |
6c17aa01 SG |
429 | default: |
430 | return -ENODEV; | |
431 | } | |
432 | data->sio = sio; | |
433 | ||
434 | platform_set_drvdata(pdev, data); | |
435 | ||
436 | /* For each GPIO bank, register a GPIO chip. */ | |
437 | for (i = 0; i < data->nr_bank; i++) { | |
438 | struct f7188x_gpio_bank *bank = &data->bank[i]; | |
439 | ||
58383c78 | 440 | bank->chip.parent = &pdev->dev; |
6c17aa01 SG |
441 | bank->data = data; |
442 | ||
330f4e56 | 443 | err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank); |
6c17aa01 SG |
444 | if (err) { |
445 | dev_err(&pdev->dev, | |
446 | "Failed to register gpiochip %d: %d\n", | |
447 | i, err); | |
330f4e56 | 448 | return err; |
6c17aa01 SG |
449 | } |
450 | } | |
451 | ||
6c17aa01 SG |
452 | return 0; |
453 | } | |
454 | ||
455 | static int __init f7188x_find(int addr, struct f7188x_sio *sio) | |
456 | { | |
457 | int err; | |
458 | u16 devid; | |
459 | ||
460 | err = superio_enter(addr); | |
461 | if (err) | |
462 | return err; | |
463 | ||
464 | err = -ENODEV; | |
465 | devid = superio_inw(addr, SIO_MANID); | |
466 | if (devid != SIO_FINTEK_ID) { | |
467 | pr_debug(DRVNAME ": Not a Fintek device at 0x%08x\n", addr); | |
468 | goto err; | |
469 | } | |
470 | ||
471 | devid = superio_inw(addr, SIO_DEVID); | |
472 | switch (devid) { | |
24ccef35 AB |
473 | case SIO_F71869_ID: |
474 | sio->type = f71869; | |
475 | break; | |
7e960363 AB |
476 | case SIO_F71869A_ID: |
477 | sio->type = f71869a; | |
478 | break; | |
6c17aa01 SG |
479 | case SIO_F71882_ID: |
480 | sio->type = f71882fg; | |
481 | break; | |
d69843e4 MP |
482 | case SIO_F71889A_ID: |
483 | sio->type = f71889a; | |
484 | break; | |
6c17aa01 SG |
485 | case SIO_F71889_ID: |
486 | sio->type = f71889f; | |
487 | break; | |
1920906f PH |
488 | case SIO_F81866_ID: |
489 | sio->type = f81866; | |
490 | break; | |
b0c3e54e SK |
491 | case SIO_F81804_ID: |
492 | sio->type = f81804; | |
493 | break; | |
6c17aa01 SG |
494 | default: |
495 | pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid); | |
496 | goto err; | |
497 | } | |
498 | sio->addr = addr; | |
499 | err = 0; | |
500 | ||
501 | pr_info(DRVNAME ": Found %s at %#x, revision %d\n", | |
502 | f7188x_names[sio->type], | |
503 | (unsigned int) addr, | |
504 | (int) superio_inb(addr, SIO_DEVREV)); | |
505 | ||
506 | err: | |
507 | superio_exit(addr); | |
508 | return err; | |
509 | } | |
510 | ||
511 | static struct platform_device *f7188x_gpio_pdev; | |
512 | ||
513 | static int __init | |
514 | f7188x_gpio_device_add(const struct f7188x_sio *sio) | |
515 | { | |
516 | int err; | |
517 | ||
518 | f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1); | |
519 | if (!f7188x_gpio_pdev) | |
520 | return -ENOMEM; | |
521 | ||
522 | err = platform_device_add_data(f7188x_gpio_pdev, | |
523 | sio, sizeof(*sio)); | |
524 | if (err) { | |
525 | pr_err(DRVNAME "Platform data allocation failed\n"); | |
526 | goto err; | |
527 | } | |
528 | ||
529 | err = platform_device_add(f7188x_gpio_pdev); | |
530 | if (err) { | |
531 | pr_err(DRVNAME "Device addition failed\n"); | |
532 | goto err; | |
533 | } | |
534 | ||
535 | return 0; | |
536 | ||
537 | err: | |
538 | platform_device_put(f7188x_gpio_pdev); | |
539 | ||
540 | return err; | |
541 | } | |
542 | ||
543 | /* | |
3f8f4f19 | 544 | * Try to match a supported Fintek device by reading the (hard-wired) |
6c17aa01 SG |
545 | * configuration I/O ports. If available, then register both the platform |
546 | * device and driver to support the GPIOs. | |
547 | */ | |
548 | ||
549 | static struct platform_driver f7188x_gpio_driver = { | |
550 | .driver = { | |
6c17aa01 SG |
551 | .name = DRVNAME, |
552 | }, | |
553 | .probe = f7188x_gpio_probe, | |
6c17aa01 SG |
554 | }; |
555 | ||
556 | static int __init f7188x_gpio_init(void) | |
557 | { | |
558 | int err; | |
559 | struct f7188x_sio sio; | |
560 | ||
561 | if (f7188x_find(0x2e, &sio) && | |
562 | f7188x_find(0x4e, &sio)) | |
563 | return -ENODEV; | |
564 | ||
565 | err = platform_driver_register(&f7188x_gpio_driver); | |
566 | if (!err) { | |
567 | err = f7188x_gpio_device_add(&sio); | |
568 | if (err) | |
569 | platform_driver_unregister(&f7188x_gpio_driver); | |
570 | } | |
571 | ||
572 | return err; | |
573 | } | |
574 | subsys_initcall(f7188x_gpio_init); | |
575 | ||
576 | static void __exit f7188x_gpio_exit(void) | |
577 | { | |
578 | platform_device_unregister(f7188x_gpio_pdev); | |
579 | platform_driver_unregister(&f7188x_gpio_driver); | |
580 | } | |
581 | module_exit(f7188x_gpio_exit); | |
582 | ||
d69843e4 | 583 | MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71869, F71869A, F71882FG, F71889A, F71889F and F81866"); |
6c17aa01 SG |
584 | MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>"); |
585 | MODULE_LICENSE("GPL"); |