[linux-2.6-block.git] / drivers / gpio / gpio-ep93xx.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Generic EP93xx GPIO handling
 *
 * Copyright (c) 2008 Ryan Mallon
 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
 *
 * Based on code originally from:
 *  linux/arch/arm/mach-ep93xx/core.c
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/gpio/driver.h>
#include <linux/bitops.h>

#define EP93XX_GPIO_F_INT_STATUS 0x5c
#define EP93XX_GPIO_A_INT_STATUS 0xa0
#define EP93XX_GPIO_B_INT_STATUS 0xbc

/* Maximum value for gpio line identifiers */
#define EP93XX_GPIO_LINE_MAX 63

/* Maximum value for irq capable line identifiers */
#define EP93XX_GPIO_LINE_MAX_IRQ 23

/*
 * IRQ numbers used by this driver is 64 ..87
 *
 * Map GPIO A0..A7  (0..7)  to irq 64..71,
 *          B0..B7  (7..15) to irq 72..79, and
 *          F0..F7 (16..24) to irq 80..87.
 */
static unsigned int ep93xx_gpio_irq_base[3] = { 64, 72, 80 };

struct ep93xx_gpio {
	void __iomem		*base;
	struct gpio_chip	gc[8];
};

/*************************************************************************
 * Interrupt handling for EP93xx on-chip GPIOs
 *************************************************************************/
static unsigned char gpio_int_unmasked[3];
static unsigned char gpio_int_enabled[3];
static unsigned char gpio_int_type1[3];
static unsigned char gpio_int_type2[3];
static unsigned char gpio_int_debounce[3];

/* Port ordering is: A B F */
static const u8 int_type1_register_offset[3]	= { 0x90, 0xac, 0x4c };
static const u8 int_type2_register_offset[3]	= { 0x94, 0xb0, 0x50 };
static const u8 eoi_register_offset[3]		= { 0x98, 0xb4, 0x54 };
static const u8 int_en_register_offset[3]	= { 0x9c, 0xb8, 0x58 };
static const u8 int_debounce_register_offset[3]	= { 0xa8, 0xc4, 0x64 };

static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigned port)
{
	BUG_ON(port > 2);

	writeb_relaxed(0, epg->base + int_en_register_offset[port]);

	writeb_relaxed(gpio_int_type2[port],
		       epg->base + int_type2_register_offset[port]);

	writeb_relaxed(gpio_int_type1[port],
		       epg->base + int_type1_register_offset[port]);

	writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
	       epg->base + int_en_register_offset[port]);
}

static int ep93xx_gpio_port(struct gpio_chip *gc)
{
	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	int port = 0;

	while (gc != &epg->gc[port] && port < sizeof(epg->gc))
		port++;

	/* This should not happen but is there as a last safeguard */
	if (gc != &epg->gc[port]) {
		pr_crit("can't find the GPIO port\n");
		return 0;
	}

	return port;
}

static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
				     unsigned int offset, bool enable)
{
	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	int port = ep93xx_gpio_port(gc);
	int port_mask = BIT(offset);

	if (enable)
		gpio_int_debounce[port] |= port_mask;
	else
		gpio_int_debounce[port] &= ~port_mask;

	writeb(gpio_int_debounce[port],
	       epg->base + int_debounce_register_offset[port]);
}

static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
{
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	struct irq_chip *irqchip = irq_desc_get_chip(desc);
	unsigned long stat;
	int offset;

	chained_irq_enter(irqchip, desc);

	stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
	for_each_set_bit(offset, &stat, 8) {
		int gpio_irq = ep93xx_gpio_irq_base[0] + offset;
		generic_handle_irq(gpio_irq);
	}

	stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
	for_each_set_bit(offset, &stat, 8) {
		int gpio_irq = ep93xx_gpio_irq_base[1] + offset;
		generic_handle_irq(gpio_irq);
	}

	chained_irq_exit(irqchip, desc);
}

static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
{
	/*
	 * map discontiguous hw irq range to continuous sw irq range:
	 *
	 *  IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7}
	 */
	struct irq_chip *irqchip = irq_desc_get_chip(desc);
	unsigned int irq = irq_desc_get_irq(desc);
	int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
	int gpio_irq = ep93xx_gpio_irq_base[2] + port_f_idx;

	chained_irq_enter(irqchip, desc);
	generic_handle_irq(gpio_irq);
	chained_irq_exit(irqchip, desc);
}

static void ep93xx_gpio_irq_ack(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	int port = ep93xx_gpio_port(gc);
	int port_mask = BIT(d->irq & 7);

	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
		gpio_int_type2[port] ^= port_mask; /* switch edge direction */
		ep93xx_gpio_update_int_params(epg, port);
	}

	writeb(port_mask, epg->base + eoi_register_offset[port]);
}

static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	int port = ep93xx_gpio_port(gc);
	int port_mask = BIT(d->irq & 7);

	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
		gpio_int_type2[port] ^= port_mask; /* switch edge direction */

	gpio_int_unmasked[port] &= ~port_mask;
	ep93xx_gpio_update_int_params(epg, port);

	writeb(port_mask, epg->base + eoi_register_offset[port]);
}

static void ep93xx_gpio_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	int port = ep93xx_gpio_port(gc);

	gpio_int_unmasked[port] &= ~BIT(d->irq & 7);
	ep93xx_gpio_update_int_params(epg, port);
}

static void ep93xx_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	int port = ep93xx_gpio_port(gc);

	gpio_int_unmasked[port] |= BIT(d->irq & 7);
	ep93xx_gpio_update_int_params(epg, port);
}

/*
 * gpio_int_type1 controls whether the interrupt is level (0) or
 * edge (1) triggered, while gpio_int_type2 controls whether it
 * triggers on low/falling (0) or high/rising (1).
 */
static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	int port = ep93xx_gpio_port(gc);
	int offset = d->irq & 7;
	int port_mask = BIT(offset);
	irq_flow_handler_t handler;

	gc->direction_input(gc, offset);

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		gpio_int_type1[port] |= port_mask;
		gpio_int_type2[port] |= port_mask;
		handler = handle_edge_irq;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		gpio_int_type1[port] |= port_mask;
		gpio_int_type2[port] &= ~port_mask;
		handler = handle_edge_irq;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		gpio_int_type1[port] &= ~port_mask;
		gpio_int_type2[port] |= port_mask;
		handler = handle_level_irq;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		gpio_int_type1[port] &= ~port_mask;
		gpio_int_type2[port] &= ~port_mask;
		handler = handle_level_irq;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		gpio_int_type1[port] |= port_mask;
		/* set initial polarity based on current input level */
		if (gc->get(gc, offset))
			gpio_int_type2[port] &= ~port_mask; /* falling */
		else
			gpio_int_type2[port] |= port_mask; /* rising */
		handler = handle_edge_irq;
		break;
	default:
		return -EINVAL;
	}

	irq_set_handler_locked(d, handler);

	gpio_int_enabled[port] |= port_mask;

	ep93xx_gpio_update_int_params(epg, port);

	return 0;
}

static struct irq_chip ep93xx_gpio_irq_chip = {
	.name		= "GPIO",
	.irq_ack	= ep93xx_gpio_irq_ack,
	.irq_mask_ack	= ep93xx_gpio_irq_mask_ack,
	.irq_mask	= ep93xx_gpio_irq_mask,
	.irq_unmask	= ep93xx_gpio_irq_unmask,
	.irq_set_type	= ep93xx_gpio_irq_type,
};

static void ep93xx_gpio_init_irq(struct platform_device *pdev,
				 struct ep93xx_gpio *epg)
{
	int gpio_irq;
	int i;

	/* The A bank */
	for (i = 0; i < 8; i++) {
		gpio_irq = ep93xx_gpio_irq_base[0] + i;
		irq_set_chip_data(gpio_irq, &epg->gc[0]);
		irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
					 handle_level_irq);
		irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
	}
	/* The B bank */
	for (i = 0; i < 8; i++) {
		gpio_irq = ep93xx_gpio_irq_base[1] + i;
		irq_set_chip_data(gpio_irq, &epg->gc[1]);
		irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
					 handle_level_irq);
		irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
	}
	/* The F bank */
	for (i = 0; i < 8; i++) {
		gpio_irq = ep93xx_gpio_irq_base[2] + i;
		irq_set_chip_data(gpio_irq, &epg->gc[5]);
		irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
					 handle_level_irq);
		irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
	}

	irq_set_chained_handler_and_data(platform_get_irq(pdev, 0),
					 ep93xx_gpio_ab_irq_handler,
					 &epg->gc[0]);
	for (i = 1; i <= 8; i++)
		irq_set_chained_handler_and_data(platform_get_irq(pdev, i),
						 ep93xx_gpio_f_irq_handler,
						 &epg->gc[i]);
}


/*************************************************************************
 * gpiolib interface for EP93xx on-chip GPIOs
 *************************************************************************/
struct ep93xx_gpio_bank {
	const char	*label;
	int		data;
	int		dir;
	int		base;
	bool		has_irq;
};

#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _has_irq)	\
	{							\
		.label		= _label,			\
		.data		= _data,			\
		.dir		= _dir,				\
		.base		= _base,			\
		.has_irq	= _has_irq,			\
	}

static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
	EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true), /* Bank A has 8 IRQs */
	EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true), /* Bank B has 8 IRQs */
	EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
	EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
	EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
	EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true), /* Bank F has 8 IRQs */
	EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
	EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
};

static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
				  unsigned long config)
{
	u32 debounce;

	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
		return -ENOTSUPP;

	debounce = pinconf_to_config_argument(config);
	ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false);

	return 0;
}

static int ep93xx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
	int port = ep93xx_gpio_port(gc);

	/* Those are the ports supporting IRQ */
	if (port != 0 && port != 1 && port != 5)
		return -EINVAL;

	return ep93xx_gpio_irq_base[port] + offset;
}

static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev,
				struct ep93xx_gpio *epg,
				struct ep93xx_gpio_bank *bank)
{
	void __iomem *data = epg->base + bank->data;
	void __iomem *dir = epg->base + bank->dir;
	int err;

	err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
	if (err)
		return err;

	gc->label = bank->label;
	gc->base = bank->base;

	if (bank->has_irq) {
		gc->set_config = ep93xx_gpio_set_config;
		gc->to_irq = ep93xx_gpio_to_irq;
	}

	return devm_gpiochip_add_data(dev, gc, epg);
}

static int ep93xx_gpio_probe(struct platform_device *pdev)
{
	struct ep93xx_gpio *epg;
	struct resource *res;
	int i;
	struct device *dev = &pdev->dev;

	epg = devm_kzalloc(dev, sizeof(*epg), GFP_KERNEL);
	if (!epg)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	epg->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(epg->base))
		return PTR_ERR(epg->base);

	for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
		struct gpio_chip *gc = &epg->gc[i];
		struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];

		if (ep93xx_gpio_add_bank(gc, &pdev->dev, epg, bank))
			dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
				bank->label);
	}

	ep93xx_gpio_init_irq(pdev, epg);

	return 0;
}

static struct platform_driver ep93xx_gpio_driver = {
	.driver		= {
		.name	= "gpio-ep93xx",
	},
	.probe		= ep93xx_gpio_probe,
};

static int __init ep93xx_gpio_init(void)
{
	return platform_driver_register(&ep93xx_gpio_driver);
}
postcore_initcall(ep93xx_gpio_init);

MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
		"H Hartley Sweeten <hsweeten@visionengravers.com>");
MODULE_DESCRIPTION("EP93XX GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
68b64931	1	// SPDX-License-Identifier: GPL-2.0
b685004f	2	/*
b685004f RM	3	* Generic EP93xx GPIO handling
b685004f RM	4	*
1c5454ee	5	* Copyright (c) 2008 Ryan Mallon
1e4c8842	6	* Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
b685004f RM	7	*
	8	* Based on code originally from:
	9	* linux/arch/arm/mach-ep93xx/core.c
b685004f RM	10	*/
	11
	12	#include <linux/init.h>
bb207ef1	13	#include <linux/module.h>
1e4c8842	14	#include <linux/platform_device.h>
fced80c7	15	#include <linux/io.h>
595c050d	16	#include <linux/irq.h>
1e4c8842	17	#include <linux/slab.h>
0f4630f3	18	#include <linux/gpio/driver.h>
51ba88e3	19	#include <linux/bitops.h>
b685004f	20
991ce74e LW	21	#define EP93XX_GPIO_F_INT_STATUS 0x5c
	22	#define EP93XX_GPIO_A_INT_STATUS 0xa0
	23	#define EP93XX_GPIO_B_INT_STATUS 0xbc
4c2baed3 AB	24
	25	/* Maximum value for gpio line identifiers */
	26	#define EP93XX_GPIO_LINE_MAX 63
	27
	28	/* Maximum value for irq capable line identifiers */
	29	#define EP93XX_GPIO_LINE_MAX_IRQ 23
	30
d875cc27 LW	31	/*
	32	* IRQ numbers used by this driver is 64 ..87
	33	*
	34	* Map GPIO A0..A7 (0..7) to irq 64..71,
	35	* B0..B7 (7..15) to irq 72..79, and
	36	* F0..F7 (16..24) to irq 80..87.
	37	*/
	38	static unsigned int ep93xx_gpio_irq_base[3] = { 64, 72, 80 };
	39
1e4c8842	40	struct ep93xx_gpio {
1d2bb17a	41	void __iomem *base;
0f4630f3	42	struct gpio_chip gc[8];
1e4c8842 HS	43	};
1e4c8842 HS	44
d056ab78	45	/*************************************************************************
4742723c	46	* Interrupt handling for EP93xx on-chip GPIOs
d056ab78 HS	47	*************************************************************************/
	48	static unsigned char gpio_int_unmasked[3];
	49	static unsigned char gpio_int_enabled[3];
	50	static unsigned char gpio_int_type1[3];
	51	static unsigned char gpio_int_type2[3];
	52	static unsigned char gpio_int_debounce[3];
	53
	54	/* Port ordering is: A B F */
	55	static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
	56	static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
	57	static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
	58	static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
	59	static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
	60
991ce74e	61	static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigned port)
d056ab78 HS	62	{
	63	BUG_ON(port > 2);
	64
991ce74e	65	writeb_relaxed(0, epg->base + int_en_register_offset[port]);
d056ab78	66
d27e06ac	67	writeb_relaxed(gpio_int_type2[port],
991ce74e	68	epg->base + int_type2_register_offset[port]);
d056ab78	69
d27e06ac	70	writeb_relaxed(gpio_int_type1[port],
991ce74e	71	epg->base + int_type1_register_offset[port]);
d056ab78	72
d27e06ac	73	writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
991ce74e	74	epg->base + int_en_register_offset[port]);
d056ab78 HS	75	}
d056ab78 HS	76
fd935fc4	77	static int ep93xx_gpio_port(struct gpio_chip *gc)
d056ab78	78	{
fd935fc4 LW	79	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	80	int port = 0;
	81
	82	while (gc != &epg->gc[port] && port < sizeof(epg->gc))
	83	port++;
	84
	85	/* This should not happen but is there as a last safeguard */
	86	if (gc != &epg->gc[port]) {
	87	pr_crit("can't find the GPIO port\n");
	88	return 0;
	89	}
	90
	91	return port;
	92	}
	93
	94	static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
	95	unsigned int offset, bool enable)
	96	{
	97	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	98	int port = ep93xx_gpio_port(gc);
	99	int port_mask = BIT(offset);
d056ab78 HS	100
	101	if (enable)
	102	gpio_int_debounce[port] \|= port_mask;
	103	else
	104	gpio_int_debounce[port] &= ~port_mask;
	105
d27e06ac	106	writeb(gpio_int_debounce[port],
991ce74e	107	epg->base + int_debounce_register_offset[port]);
d056ab78	108	}
d056ab78	109
bd0b9ac4	110	static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
d056ab78	111	{
991ce74e LW	112	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
991ce74e LW	113	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
99399f40	114	struct irq_chip *irqchip = irq_desc_get_chip(desc);
68491b07 LW	115	unsigned long stat;
68491b07 LW	116	int offset;
d056ab78	117
99399f40 LW	118	chained_irq_enter(irqchip, desc);
99399f40 LW	119
68491b07 LW	120	stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
68491b07 LW	121	for_each_set_bit(offset, &stat, 8) {
d875cc27	122	int gpio_irq = ep93xx_gpio_irq_base[0] + offset;
68491b07	123	generic_handle_irq(gpio_irq);
d056ab78 HS	124	}
d056ab78 HS	125
68491b07 LW	126	stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
68491b07 LW	127	for_each_set_bit(offset, &stat, 8) {
d875cc27	128	int gpio_irq = ep93xx_gpio_irq_base[1] + offset;
68491b07	129	generic_handle_irq(gpio_irq);
d056ab78	130	}
99399f40 LW	131
99399f40 LW	132	chained_irq_exit(irqchip, desc);
d056ab78 HS	133	}
d056ab78 HS	134
bd0b9ac4	135	static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
d056ab78 HS	136	{
d056ab78 HS	137	/*
25985edc	138	* map discontiguous hw irq range to continuous sw irq range:
d056ab78	139	*
d875cc27	140	* IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7}
d056ab78	141	*/
99399f40	142	struct irq_chip *irqchip = irq_desc_get_chip(desc);
e43ea7a7	143	unsigned int irq = irq_desc_get_irq(desc);
d056ab78	144	int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
d875cc27	145	int gpio_irq = ep93xx_gpio_irq_base[2] + port_f_idx;
d056ab78	146
99399f40	147	chained_irq_enter(irqchip, desc);
d056ab78	148	generic_handle_irq(gpio_irq);
99399f40	149	chained_irq_exit(irqchip, desc);
d056ab78 HS	150	}
d056ab78 HS	151
c0afc916	152	static void ep93xx_gpio_irq_ack(struct irq_data *d)
d056ab78	153	{
991ce74e LW	154	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
991ce74e LW	155	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
51ba88e3 LW	156	int port = ep93xx_gpio_port(gc);
51ba88e3 LW	157	int port_mask = BIT(d->irq & 7);
d056ab78	158
d1735a2e	159	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
d056ab78	160	gpio_int_type2[port] ^= port_mask; /* switch edge direction */
991ce74e	161	ep93xx_gpio_update_int_params(epg, port);
d056ab78 HS	162	}
d056ab78 HS	163
991ce74e	164	writeb(port_mask, epg->base + eoi_register_offset[port]);
d056ab78 HS	165	}
d056ab78 HS	166
c0afc916	167	static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
d056ab78	168	{
991ce74e LW	169	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
991ce74e LW	170	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
51ba88e3 LW	171	int port = ep93xx_gpio_port(gc);
51ba88e3 LW	172	int port_mask = BIT(d->irq & 7);
d056ab78	173
d1735a2e	174	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
d056ab78 HS	175	gpio_int_type2[port] ^= port_mask; /* switch edge direction */
	176
	177	gpio_int_unmasked[port] &= ~port_mask;
991ce74e	178	ep93xx_gpio_update_int_params(epg, port);
d056ab78	179
991ce74e	180	writeb(port_mask, epg->base + eoi_register_offset[port]);
d056ab78 HS	181	}
d056ab78 HS	182
c0afc916	183	static void ep93xx_gpio_irq_mask(struct irq_data *d)
d056ab78	184	{
991ce74e LW	185	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
991ce74e LW	186	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
51ba88e3	187	int port = ep93xx_gpio_port(gc);
d056ab78	188
51ba88e3	189	gpio_int_unmasked[port] &= ~BIT(d->irq & 7);
991ce74e	190	ep93xx_gpio_update_int_params(epg, port);
d056ab78 HS	191	}
d056ab78 HS	192
c0afc916	193	static void ep93xx_gpio_irq_unmask(struct irq_data *d)
d056ab78	194	{
991ce74e LW	195	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
991ce74e LW	196	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
51ba88e3	197	int port = ep93xx_gpio_port(gc);
d056ab78	198
51ba88e3	199	gpio_int_unmasked[port] \|= BIT(d->irq & 7);
991ce74e	200	ep93xx_gpio_update_int_params(epg, port);
d056ab78 HS	201	}
	202
	203	/*
	204	* gpio_int_type1 controls whether the interrupt is level (0) or
	205	* edge (1) triggered, while gpio_int_type2 controls whether it
	206	* triggers on low/falling (0) or high/rising (1).
	207	*/
c0afc916	208	static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
d056ab78	209	{
991ce74e LW	210	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
991ce74e LW	211	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
51ba88e3 LW	212	int port = ep93xx_gpio_port(gc);
	213	int offset = d->irq & 7;
	214	int port_mask = BIT(offset);
d1735a2e	215	irq_flow_handler_t handler;
d056ab78	216
51ba88e3	217	gc->direction_input(gc, offset);
d056ab78 HS	218
	219	switch (type) {
	220	case IRQ_TYPE_EDGE_RISING:
	221	gpio_int_type1[port] \|= port_mask;
	222	gpio_int_type2[port] \|= port_mask;
d1735a2e	223	handler = handle_edge_irq;
d056ab78 HS	224	break;
	225	case IRQ_TYPE_EDGE_FALLING:
	226	gpio_int_type1[port] \|= port_mask;
	227	gpio_int_type2[port] &= ~port_mask;
d1735a2e	228	handler = handle_edge_irq;
d056ab78 HS	229	break;
	230	case IRQ_TYPE_LEVEL_HIGH:
	231	gpio_int_type1[port] &= ~port_mask;
	232	gpio_int_type2[port] \|= port_mask;
d1735a2e	233	handler = handle_level_irq;
d056ab78 HS	234	break;
	235	case IRQ_TYPE_LEVEL_LOW:
	236	gpio_int_type1[port] &= ~port_mask;
	237	gpio_int_type2[port] &= ~port_mask;
d1735a2e	238	handler = handle_level_irq;
d056ab78 HS	239	break;
	240	case IRQ_TYPE_EDGE_BOTH:
	241	gpio_int_type1[port] \|= port_mask;
	242	/* set initial polarity based on current input level */
51ba88e3	243	if (gc->get(gc, offset))
d056ab78 HS	244	gpio_int_type2[port] &= ~port_mask; /* falling */
	245	else
	246	gpio_int_type2[port] \|= port_mask; /* rising */
d1735a2e	247	handler = handle_edge_irq;
d056ab78 HS	248	break;
d056ab78 HS	249	default:
d056ab78 HS	250	return -EINVAL;
	251	}
	252
72b2a9ef	253	irq_set_handler_locked(d, handler);
d056ab78	254
d1735a2e	255	gpio_int_enabled[port] \|= port_mask;
d056ab78	256
991ce74e	257	ep93xx_gpio_update_int_params(epg, port);
d056ab78 HS	258
	259	return 0;
	260	}
	261
	262	static struct irq_chip ep93xx_gpio_irq_chip = {
	263	.name = "GPIO",
c0afc916 LB	264	.irq_ack = ep93xx_gpio_irq_ack,
	265	.irq_mask_ack = ep93xx_gpio_irq_mask_ack,
	266	.irq_mask = ep93xx_gpio_irq_mask,
	267	.irq_unmask = ep93xx_gpio_irq_unmask,
	268	.irq_set_type = ep93xx_gpio_irq_type,
d056ab78 HS	269	};
d056ab78 HS	270
991ce74e LW	271	static void ep93xx_gpio_init_irq(struct platform_device *pdev,
991ce74e LW	272	struct ep93xx_gpio *epg)
d056ab78 HS	273	{
d056ab78 HS	274	int gpio_irq;
4c2baed3	275	int i;
d056ab78	276
991ce74e	277	/* The A bank */
d875cc27 LW	278	for (i = 0; i < 8; i++) {
d875cc27 LW	279	gpio_irq = ep93xx_gpio_irq_base[0] + i;
991ce74e LW	280	irq_set_chip_data(gpio_irq, &epg->gc[0]);
	281	irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
	282	handle_level_irq);
	283	irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
	284	}
	285	/* The B bank */
d875cc27 LW	286	for (i = 0; i < 8; i++) {
d875cc27 LW	287	gpio_irq = ep93xx_gpio_irq_base[1] + i;
991ce74e LW	288	irq_set_chip_data(gpio_irq, &epg->gc[1]);
	289	irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
	290	handle_level_irq);
	291	irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
	292	}
	293	/* The F bank */
d875cc27 LW	294	for (i = 0; i < 8; i++) {
d875cc27 LW	295	gpio_irq = ep93xx_gpio_irq_base[2] + i;
991ce74e	296	irq_set_chip_data(gpio_irq, &epg->gc[5]);
f38c02f3 TG	297	irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
f38c02f3 TG	298	handle_level_irq);
23393d49	299	irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
d056ab78 HS	300	}
d056ab78 HS	301
991ce74e LW	302	irq_set_chained_handler_and_data(platform_get_irq(pdev, 0),
	303	ep93xx_gpio_ab_irq_handler,
	304	&epg->gc[0]);
4c2baed3	305	for (i = 1; i <= 8; i++)
991ce74e LW	306	irq_set_chained_handler_and_data(platform_get_irq(pdev, i),
	307	ep93xx_gpio_f_irq_handler,
	308	&epg->gc[i]);
d056ab78 HS	309	}
	310
	311
	312	/*************************************************************************
	313	* gpiolib interface for EP93xx on-chip GPIOs
	314	*************************************************************************/
1e4c8842 HS	315	struct ep93xx_gpio_bank {
	316	const char *label;
	317	int data;
	318	int dir;
	319	int base;
3c38b3a3	320	bool has_irq;
b685004f RM	321	};
b685004f RM	322
3c38b3a3	323	#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _has_irq) \
1e4c8842 HS	324	{ \
	325	.label = _label, \
	326	.data = _data, \
	327	.dir = _dir, \
	328	.base = _base, \
3c38b3a3	329	.has_irq = _has_irq, \
1e4c8842	330	}
b685004f	331
1e4c8842	332	static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
3c38b3a3 LW	333	EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true), /* Bank A has 8 IRQs */
3c38b3a3 LW	334	EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true), /* Bank B has 8 IRQs */
1e4c8842 HS	335	EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
	336	EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
	337	EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
3c38b3a3	338	EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true), /* Bank F has 8 IRQs */
1e4c8842 HS	339	EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
	340	EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
	341	};
	342
991ce74e	343	static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
2956b5d9	344	unsigned long config)
b685004f	345	{
2956b5d9 MW	346	u32 debounce;
	347
	348	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
	349	return -ENOTSUPP;
b685004f	350
2956b5d9	351	debounce = pinconf_to_config_argument(config);
fd935fc4	352	ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false);
b685004f RM	353
	354	return 0;
	355	}
	356
d875cc27	357	static int ep93xx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
257af9f9	358	{
d875cc27	359	int port = ep93xx_gpio_port(gc);
257af9f9	360
d875cc27 LW	361	/* Those are the ports supporting IRQ */
d875cc27 LW	362	if (port != 0 && port != 1 && port != 5)
257af9f9 LW	363	return -EINVAL;
257af9f9 LW	364
d875cc27	365	return ep93xx_gpio_irq_base[port] + offset;
257af9f9 LW	366	}
257af9f9 LW	367
0f4630f3	368	static int ep93xx_gpio_add_bank(struct gpio_chip gc, struct device dev,
991ce74e LW	369	struct ep93xx_gpio *epg,
991ce74e LW	370	struct ep93xx_gpio_bank *bank)
b685004f	371	{
991ce74e LW	372	void __iomem *data = epg->base + bank->data;
991ce74e LW	373	void __iomem *dir = epg->base + bank->dir;
1e4c8842	374	int err;
b685004f	375
0f4630f3	376	err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
1e4c8842 HS	377	if (err)
1e4c8842 HS	378	return err;
b685004f	379
0f4630f3 LW	380	gc->label = bank->label;
0f4630f3 LW	381	gc->base = bank->base;
b685004f	382
3c38b3a3	383	if (bank->has_irq) {
2956b5d9	384	gc->set_config = ep93xx_gpio_set_config;
0f4630f3	385	gc->to_irq = ep93xx_gpio_to_irq;
257af9f9	386	}
b685004f	387
991ce74e	388	return devm_gpiochip_add_data(dev, gc, epg);
b685004f RM	389	}
b685004f RM	390
3836309d	391	static int ep93xx_gpio_probe(struct platform_device *pdev)
b685004f	392	{
1d2bb17a	393	struct ep93xx_gpio *epg;
1e4c8842	394	struct resource *res;
1e4c8842	395	int i;
1aeede0b	396	struct device *dev = &pdev->dev;
b685004f	397
1d2bb17a LW	398	epg = devm_kzalloc(dev, sizeof(*epg), GFP_KERNEL);
1d2bb17a LW	399	if (!epg)
1e4c8842	400	return -ENOMEM;
b685004f	401
1e4c8842	402	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1d2bb17a LW	403	epg->base = devm_ioremap_resource(dev, res);
	404	if (IS_ERR(epg->base))
	405	return PTR_ERR(epg->base);
5d046af0	406
1e4c8842	407	for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
1d2bb17a	408	struct gpio_chip *gc = &epg->gc[i];
1e4c8842	409	struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
5d046af0	410
991ce74e	411	if (ep93xx_gpio_add_bank(gc, &pdev->dev, epg, bank))
1e4c8842 HS	412	dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
1e4c8842 HS	413	bank->label);
b685004f RM	414	}
b685004f RM	415
991ce74e	416	ep93xx_gpio_init_irq(pdev, epg);
b685004f	417
1e4c8842	418	return 0;
1e4c8842	419	}
fd015480	420
1e4c8842 HS	421	static struct platform_driver ep93xx_gpio_driver = {
	422	.driver = {
	423	.name = "gpio-ep93xx",
1e4c8842 HS	424	},
	425	.probe = ep93xx_gpio_probe,
	426	};
	427
	428	static int __init ep93xx_gpio_init(void)
	429	{
1e4c8842	430	return platform_driver_register(&ep93xx_gpio_driver);
b685004f	431	}
1e4c8842 HS	432	postcore_initcall(ep93xx_gpio_init);
	433
	434	MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
	435	"H Hartley Sweeten <hsweeten@visionengravers.com>");
	436	MODULE_DESCRIPTION("EP93XX GPIO driver");
	437	MODULE_LICENSE("GPL");