Commit | Line | Data |
---|---|---|
68b64931 | 1 | // SPDX-License-Identifier: GPL-2.0 |
b685004f | 2 | /* |
b685004f RM |
3 | * Generic EP93xx GPIO handling |
4 | * | |
1c5454ee | 5 | * Copyright (c) 2008 Ryan Mallon |
1e4c8842 | 6 | * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com> |
b685004f RM |
7 | * |
8 | * Based on code originally from: | |
9 | * linux/arch/arm/mach-ep93xx/core.c | |
b685004f RM |
10 | */ |
11 | ||
12 | #include <linux/init.h> | |
bb207ef1 | 13 | #include <linux/module.h> |
1e4c8842 | 14 | #include <linux/platform_device.h> |
fced80c7 | 15 | #include <linux/io.h> |
595c050d | 16 | #include <linux/irq.h> |
1e4c8842 | 17 | #include <linux/slab.h> |
0f4630f3 | 18 | #include <linux/gpio/driver.h> |
51ba88e3 | 19 | #include <linux/bitops.h> |
b685004f | 20 | |
991ce74e LW |
21 | #define EP93XX_GPIO_F_INT_STATUS 0x5c |
22 | #define EP93XX_GPIO_A_INT_STATUS 0xa0 | |
23 | #define EP93XX_GPIO_B_INT_STATUS 0xbc | |
4c2baed3 AB |
24 | |
25 | /* Maximum value for gpio line identifiers */ | |
26 | #define EP93XX_GPIO_LINE_MAX 63 | |
27 | ||
28 | /* Maximum value for irq capable line identifiers */ | |
29 | #define EP93XX_GPIO_LINE_MAX_IRQ 23 | |
30 | ||
d875cc27 | 31 | /* |
a419a3d9 LW |
32 | * Static mapping of GPIO bank F IRQS: |
33 | * F0..F7 (16..24) to irq 80..87. | |
d875cc27 | 34 | */ |
a419a3d9 | 35 | #define EP93XX_GPIO_F_IRQ_BASE 80 |
d875cc27 | 36 | |
1e4c8842 | 37 | struct ep93xx_gpio { |
1d2bb17a | 38 | void __iomem *base; |
0f4630f3 | 39 | struct gpio_chip gc[8]; |
1e4c8842 HS |
40 | }; |
41 | ||
d056ab78 | 42 | /************************************************************************* |
4742723c | 43 | * Interrupt handling for EP93xx on-chip GPIOs |
d056ab78 HS |
44 | *************************************************************************/ |
45 | static unsigned char gpio_int_unmasked[3]; | |
46 | static unsigned char gpio_int_enabled[3]; | |
47 | static unsigned char gpio_int_type1[3]; | |
48 | static unsigned char gpio_int_type2[3]; | |
49 | static unsigned char gpio_int_debounce[3]; | |
50 | ||
51 | /* Port ordering is: A B F */ | |
52 | static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c }; | |
53 | static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 }; | |
54 | static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 }; | |
55 | static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 }; | |
56 | static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 }; | |
57 | ||
991ce74e | 58 | static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigned port) |
d056ab78 HS |
59 | { |
60 | BUG_ON(port > 2); | |
61 | ||
991ce74e | 62 | writeb_relaxed(0, epg->base + int_en_register_offset[port]); |
d056ab78 | 63 | |
d27e06ac | 64 | writeb_relaxed(gpio_int_type2[port], |
991ce74e | 65 | epg->base + int_type2_register_offset[port]); |
d056ab78 | 66 | |
d27e06ac | 67 | writeb_relaxed(gpio_int_type1[port], |
991ce74e | 68 | epg->base + int_type1_register_offset[port]); |
d056ab78 | 69 | |
d27e06ac | 70 | writeb(gpio_int_unmasked[port] & gpio_int_enabled[port], |
991ce74e | 71 | epg->base + int_en_register_offset[port]); |
d056ab78 HS |
72 | } |
73 | ||
fd935fc4 | 74 | static int ep93xx_gpio_port(struct gpio_chip *gc) |
d056ab78 | 75 | { |
fd935fc4 LW |
76 | struct ep93xx_gpio *epg = gpiochip_get_data(gc); |
77 | int port = 0; | |
78 | ||
f40f7307 | 79 | while (port < ARRAY_SIZE(epg->gc) && gc != &epg->gc[port]) |
fd935fc4 LW |
80 | port++; |
81 | ||
82 | /* This should not happen but is there as a last safeguard */ | |
f6d9af47 | 83 | if (port == ARRAY_SIZE(epg->gc)) { |
fd935fc4 LW |
84 | pr_crit("can't find the GPIO port\n"); |
85 | return 0; | |
86 | } | |
87 | ||
88 | return port; | |
89 | } | |
90 | ||
91 | static void ep93xx_gpio_int_debounce(struct gpio_chip *gc, | |
92 | unsigned int offset, bool enable) | |
93 | { | |
94 | struct ep93xx_gpio *epg = gpiochip_get_data(gc); | |
95 | int port = ep93xx_gpio_port(gc); | |
96 | int port_mask = BIT(offset); | |
d056ab78 HS |
97 | |
98 | if (enable) | |
99 | gpio_int_debounce[port] |= port_mask; | |
100 | else | |
101 | gpio_int_debounce[port] &= ~port_mask; | |
102 | ||
d27e06ac | 103 | writeb(gpio_int_debounce[port], |
991ce74e | 104 | epg->base + int_debounce_register_offset[port]); |
d056ab78 | 105 | } |
d056ab78 | 106 | |
bd0b9ac4 | 107 | static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) |
d056ab78 | 108 | { |
991ce74e LW |
109 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
110 | struct ep93xx_gpio *epg = gpiochip_get_data(gc); | |
99399f40 | 111 | struct irq_chip *irqchip = irq_desc_get_chip(desc); |
68491b07 LW |
112 | unsigned long stat; |
113 | int offset; | |
d056ab78 | 114 | |
99399f40 LW |
115 | chained_irq_enter(irqchip, desc); |
116 | ||
a419a3d9 LW |
117 | /* |
118 | * Dispatch the IRQs to the irqdomain of each A and B | |
119 | * gpiochip irqdomains depending on what has fired. | |
120 | * The tricky part is that the IRQ line is shared | |
121 | * between bank A and B and each has their own gpiochip. | |
122 | */ | |
68491b07 | 123 | stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS); |
a419a3d9 LW |
124 | for_each_set_bit(offset, &stat, 8) |
125 | generic_handle_irq(irq_find_mapping(epg->gc[0].irq.domain, | |
126 | offset)); | |
d056ab78 | 127 | |
68491b07 | 128 | stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS); |
a419a3d9 LW |
129 | for_each_set_bit(offset, &stat, 8) |
130 | generic_handle_irq(irq_find_mapping(epg->gc[1].irq.domain, | |
131 | offset)); | |
99399f40 LW |
132 | |
133 | chained_irq_exit(irqchip, desc); | |
d056ab78 HS |
134 | } |
135 | ||
bd0b9ac4 | 136 | static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc) |
d056ab78 HS |
137 | { |
138 | /* | |
25985edc | 139 | * map discontiguous hw irq range to continuous sw irq range: |
d056ab78 | 140 | * |
d875cc27 | 141 | * IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7} |
d056ab78 | 142 | */ |
99399f40 | 143 | struct irq_chip *irqchip = irq_desc_get_chip(desc); |
e43ea7a7 | 144 | unsigned int irq = irq_desc_get_irq(desc); |
d056ab78 | 145 | int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */ |
a419a3d9 | 146 | int gpio_irq = EP93XX_GPIO_F_IRQ_BASE + port_f_idx; |
d056ab78 | 147 | |
99399f40 | 148 | chained_irq_enter(irqchip, desc); |
d056ab78 | 149 | generic_handle_irq(gpio_irq); |
99399f40 | 150 | chained_irq_exit(irqchip, desc); |
d056ab78 HS |
151 | } |
152 | ||
c0afc916 | 153 | static void ep93xx_gpio_irq_ack(struct irq_data *d) |
d056ab78 | 154 | { |
991ce74e LW |
155 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
156 | struct ep93xx_gpio *epg = gpiochip_get_data(gc); | |
51ba88e3 LW |
157 | int port = ep93xx_gpio_port(gc); |
158 | int port_mask = BIT(d->irq & 7); | |
d056ab78 | 159 | |
d1735a2e | 160 | if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { |
d056ab78 | 161 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ |
991ce74e | 162 | ep93xx_gpio_update_int_params(epg, port); |
d056ab78 HS |
163 | } |
164 | ||
991ce74e | 165 | writeb(port_mask, epg->base + eoi_register_offset[port]); |
d056ab78 HS |
166 | } |
167 | ||
c0afc916 | 168 | static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) |
d056ab78 | 169 | { |
991ce74e LW |
170 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
171 | struct ep93xx_gpio *epg = gpiochip_get_data(gc); | |
51ba88e3 LW |
172 | int port = ep93xx_gpio_port(gc); |
173 | int port_mask = BIT(d->irq & 7); | |
d056ab78 | 174 | |
d1735a2e | 175 | if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) |
d056ab78 HS |
176 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ |
177 | ||
178 | gpio_int_unmasked[port] &= ~port_mask; | |
991ce74e | 179 | ep93xx_gpio_update_int_params(epg, port); |
d056ab78 | 180 | |
991ce74e | 181 | writeb(port_mask, epg->base + eoi_register_offset[port]); |
d056ab78 HS |
182 | } |
183 | ||
c0afc916 | 184 | static void ep93xx_gpio_irq_mask(struct irq_data *d) |
d056ab78 | 185 | { |
991ce74e LW |
186 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
187 | struct ep93xx_gpio *epg = gpiochip_get_data(gc); | |
51ba88e3 | 188 | int port = ep93xx_gpio_port(gc); |
d056ab78 | 189 | |
51ba88e3 | 190 | gpio_int_unmasked[port] &= ~BIT(d->irq & 7); |
991ce74e | 191 | ep93xx_gpio_update_int_params(epg, port); |
d056ab78 HS |
192 | } |
193 | ||
c0afc916 | 194 | static void ep93xx_gpio_irq_unmask(struct irq_data *d) |
d056ab78 | 195 | { |
991ce74e LW |
196 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
197 | struct ep93xx_gpio *epg = gpiochip_get_data(gc); | |
51ba88e3 | 198 | int port = ep93xx_gpio_port(gc); |
d056ab78 | 199 | |
51ba88e3 | 200 | gpio_int_unmasked[port] |= BIT(d->irq & 7); |
991ce74e | 201 | ep93xx_gpio_update_int_params(epg, port); |
d056ab78 HS |
202 | } |
203 | ||
204 | /* | |
205 | * gpio_int_type1 controls whether the interrupt is level (0) or | |
206 | * edge (1) triggered, while gpio_int_type2 controls whether it | |
207 | * triggers on low/falling (0) or high/rising (1). | |
208 | */ | |
c0afc916 | 209 | static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) |
d056ab78 | 210 | { |
991ce74e LW |
211 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
212 | struct ep93xx_gpio *epg = gpiochip_get_data(gc); | |
51ba88e3 LW |
213 | int port = ep93xx_gpio_port(gc); |
214 | int offset = d->irq & 7; | |
215 | int port_mask = BIT(offset); | |
d1735a2e | 216 | irq_flow_handler_t handler; |
d056ab78 | 217 | |
51ba88e3 | 218 | gc->direction_input(gc, offset); |
d056ab78 HS |
219 | |
220 | switch (type) { | |
221 | case IRQ_TYPE_EDGE_RISING: | |
222 | gpio_int_type1[port] |= port_mask; | |
223 | gpio_int_type2[port] |= port_mask; | |
d1735a2e | 224 | handler = handle_edge_irq; |
d056ab78 HS |
225 | break; |
226 | case IRQ_TYPE_EDGE_FALLING: | |
227 | gpio_int_type1[port] |= port_mask; | |
228 | gpio_int_type2[port] &= ~port_mask; | |
d1735a2e | 229 | handler = handle_edge_irq; |
d056ab78 HS |
230 | break; |
231 | case IRQ_TYPE_LEVEL_HIGH: | |
232 | gpio_int_type1[port] &= ~port_mask; | |
233 | gpio_int_type2[port] |= port_mask; | |
d1735a2e | 234 | handler = handle_level_irq; |
d056ab78 HS |
235 | break; |
236 | case IRQ_TYPE_LEVEL_LOW: | |
237 | gpio_int_type1[port] &= ~port_mask; | |
238 | gpio_int_type2[port] &= ~port_mask; | |
d1735a2e | 239 | handler = handle_level_irq; |
d056ab78 HS |
240 | break; |
241 | case IRQ_TYPE_EDGE_BOTH: | |
242 | gpio_int_type1[port] |= port_mask; | |
243 | /* set initial polarity based on current input level */ | |
51ba88e3 | 244 | if (gc->get(gc, offset)) |
d056ab78 HS |
245 | gpio_int_type2[port] &= ~port_mask; /* falling */ |
246 | else | |
247 | gpio_int_type2[port] |= port_mask; /* rising */ | |
d1735a2e | 248 | handler = handle_edge_irq; |
d056ab78 HS |
249 | break; |
250 | default: | |
d056ab78 HS |
251 | return -EINVAL; |
252 | } | |
253 | ||
72b2a9ef | 254 | irq_set_handler_locked(d, handler); |
d056ab78 | 255 | |
d1735a2e | 256 | gpio_int_enabled[port] |= port_mask; |
d056ab78 | 257 | |
991ce74e | 258 | ep93xx_gpio_update_int_params(epg, port); |
d056ab78 HS |
259 | |
260 | return 0; | |
261 | } | |
262 | ||
263 | static struct irq_chip ep93xx_gpio_irq_chip = { | |
264 | .name = "GPIO", | |
c0afc916 LB |
265 | .irq_ack = ep93xx_gpio_irq_ack, |
266 | .irq_mask_ack = ep93xx_gpio_irq_mask_ack, | |
267 | .irq_mask = ep93xx_gpio_irq_mask, | |
268 | .irq_unmask = ep93xx_gpio_irq_unmask, | |
269 | .irq_set_type = ep93xx_gpio_irq_type, | |
d056ab78 HS |
270 | }; |
271 | ||
a419a3d9 LW |
272 | static int ep93xx_gpio_init_irq(struct platform_device *pdev, |
273 | struct ep93xx_gpio *epg) | |
d056ab78 | 274 | { |
a419a3d9 LW |
275 | int ab_parent_irq = platform_get_irq(pdev, 0); |
276 | struct device *dev = &pdev->dev; | |
d056ab78 | 277 | int gpio_irq; |
a419a3d9 | 278 | int ret; |
4c2baed3 | 279 | int i; |
d056ab78 | 280 | |
991ce74e | 281 | /* The A bank */ |
a419a3d9 LW |
282 | ret = gpiochip_irqchip_add(&epg->gc[0], &ep93xx_gpio_irq_chip, |
283 | 64, handle_level_irq, | |
284 | IRQ_TYPE_NONE); | |
285 | if (ret) { | |
286 | dev_err(dev, "Could not add irqchip 0\n"); | |
287 | return ret; | |
991ce74e | 288 | } |
a419a3d9 LW |
289 | gpiochip_set_chained_irqchip(&epg->gc[0], &ep93xx_gpio_irq_chip, |
290 | ab_parent_irq, | |
291 | ep93xx_gpio_ab_irq_handler); | |
292 | ||
991ce74e | 293 | /* The B bank */ |
a419a3d9 LW |
294 | ret = gpiochip_irqchip_add(&epg->gc[1], &ep93xx_gpio_irq_chip, |
295 | 72, handle_level_irq, | |
296 | IRQ_TYPE_NONE); | |
297 | if (ret) { | |
298 | dev_err(dev, "Could not add irqchip 1\n"); | |
299 | return ret; | |
991ce74e | 300 | } |
a419a3d9 LW |
301 | gpiochip_set_chained_irqchip(&epg->gc[1], &ep93xx_gpio_irq_chip, |
302 | ab_parent_irq, | |
303 | ep93xx_gpio_ab_irq_handler); | |
304 | ||
991ce74e | 305 | /* The F bank */ |
d875cc27 | 306 | for (i = 0; i < 8; i++) { |
a419a3d9 | 307 | gpio_irq = EP93XX_GPIO_F_IRQ_BASE + i; |
991ce74e | 308 | irq_set_chip_data(gpio_irq, &epg->gc[5]); |
f38c02f3 TG |
309 | irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, |
310 | handle_level_irq); | |
23393d49 | 311 | irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); |
d056ab78 HS |
312 | } |
313 | ||
4c2baed3 | 314 | for (i = 1; i <= 8; i++) |
991ce74e LW |
315 | irq_set_chained_handler_and_data(platform_get_irq(pdev, i), |
316 | ep93xx_gpio_f_irq_handler, | |
317 | &epg->gc[i]); | |
a419a3d9 | 318 | return 0; |
d056ab78 HS |
319 | } |
320 | ||
321 | ||
322 | /************************************************************************* | |
323 | * gpiolib interface for EP93xx on-chip GPIOs | |
324 | *************************************************************************/ | |
1e4c8842 HS |
325 | struct ep93xx_gpio_bank { |
326 | const char *label; | |
327 | int data; | |
328 | int dir; | |
329 | int base; | |
3c38b3a3 | 330 | bool has_irq; |
b685004f RM |
331 | }; |
332 | ||
3c38b3a3 | 333 | #define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _has_irq) \ |
1e4c8842 HS |
334 | { \ |
335 | .label = _label, \ | |
336 | .data = _data, \ | |
337 | .dir = _dir, \ | |
338 | .base = _base, \ | |
3c38b3a3 | 339 | .has_irq = _has_irq, \ |
1e4c8842 | 340 | } |
b685004f | 341 | |
1e4c8842 | 342 | static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = { |
3c38b3a3 LW |
343 | EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true), /* Bank A has 8 IRQs */ |
344 | EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true), /* Bank B has 8 IRQs */ | |
1e4c8842 HS |
345 | EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false), |
346 | EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false), | |
347 | EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false), | |
3c38b3a3 | 348 | EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true), /* Bank F has 8 IRQs */ |
1e4c8842 HS |
349 | EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false), |
350 | EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false), | |
351 | }; | |
352 | ||
991ce74e | 353 | static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, |
2956b5d9 | 354 | unsigned long config) |
b685004f | 355 | { |
2956b5d9 MW |
356 | u32 debounce; |
357 | ||
358 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
359 | return -ENOTSUPP; | |
b685004f | 360 | |
2956b5d9 | 361 | debounce = pinconf_to_config_argument(config); |
fd935fc4 | 362 | ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false); |
b685004f RM |
363 | |
364 | return 0; | |
365 | } | |
366 | ||
a419a3d9 | 367 | static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, unsigned offset) |
257af9f9 | 368 | { |
a419a3d9 | 369 | return EP93XX_GPIO_F_IRQ_BASE + offset; |
257af9f9 LW |
370 | } |
371 | ||
0f4630f3 | 372 | static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev, |
991ce74e LW |
373 | struct ep93xx_gpio *epg, |
374 | struct ep93xx_gpio_bank *bank) | |
b685004f | 375 | { |
991ce74e LW |
376 | void __iomem *data = epg->base + bank->data; |
377 | void __iomem *dir = epg->base + bank->dir; | |
1e4c8842 | 378 | int err; |
b685004f | 379 | |
0f4630f3 | 380 | err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0); |
1e4c8842 HS |
381 | if (err) |
382 | return err; | |
b685004f | 383 | |
0f4630f3 LW |
384 | gc->label = bank->label; |
385 | gc->base = bank->base; | |
b685004f | 386 | |
a419a3d9 | 387 | if (bank->has_irq) |
2956b5d9 | 388 | gc->set_config = ep93xx_gpio_set_config; |
b685004f | 389 | |
991ce74e | 390 | return devm_gpiochip_add_data(dev, gc, epg); |
b685004f RM |
391 | } |
392 | ||
3836309d | 393 | static int ep93xx_gpio_probe(struct platform_device *pdev) |
b685004f | 394 | { |
1d2bb17a | 395 | struct ep93xx_gpio *epg; |
1e4c8842 | 396 | int i; |
b685004f | 397 | |
6bdec6c7 | 398 | epg = devm_kzalloc(&pdev->dev, sizeof(*epg), GFP_KERNEL); |
1d2bb17a | 399 | if (!epg) |
1e4c8842 | 400 | return -ENOMEM; |
b685004f | 401 | |
6bdec6c7 | 402 | epg->base = devm_platform_ioremap_resource(pdev, 0); |
1d2bb17a LW |
403 | if (IS_ERR(epg->base)) |
404 | return PTR_ERR(epg->base); | |
5d046af0 | 405 | |
1e4c8842 | 406 | for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) { |
1d2bb17a | 407 | struct gpio_chip *gc = &epg->gc[i]; |
1e4c8842 | 408 | struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i]; |
5d046af0 | 409 | |
991ce74e | 410 | if (ep93xx_gpio_add_bank(gc, &pdev->dev, epg, bank)) |
1e4c8842 | 411 | dev_warn(&pdev->dev, "Unable to add gpio bank %s\n", |
a419a3d9 LW |
412 | bank->label); |
413 | /* Only bank F has especially funky IRQ handling */ | |
414 | if (i == 5) | |
415 | gc->to_irq = ep93xx_gpio_f_to_irq; | |
b685004f RM |
416 | } |
417 | ||
991ce74e | 418 | ep93xx_gpio_init_irq(pdev, epg); |
b685004f | 419 | |
1e4c8842 | 420 | return 0; |
1e4c8842 | 421 | } |
fd015480 | 422 | |
1e4c8842 HS |
423 | static struct platform_driver ep93xx_gpio_driver = { |
424 | .driver = { | |
425 | .name = "gpio-ep93xx", | |
1e4c8842 HS |
426 | }, |
427 | .probe = ep93xx_gpio_probe, | |
428 | }; | |
429 | ||
430 | static int __init ep93xx_gpio_init(void) | |
431 | { | |
1e4c8842 | 432 | return platform_driver_register(&ep93xx_gpio_driver); |
b685004f | 433 | } |
1e4c8842 HS |
434 | postcore_initcall(ep93xx_gpio_init); |
435 | ||
436 | MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> " | |
437 | "H Hartley Sweeten <hsweeten@visionengravers.com>"); | |
438 | MODULE_DESCRIPTION("EP93XX GPIO driver"); | |
439 | MODULE_LICENSE("GPL"); |