[linux-2.6-block.git] / drivers / gpio / gpio-ep93xx.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Generic EP93xx GPIO handling
 *
 * Copyright (c) 2008 Ryan Mallon
 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
 *
 * Based on code originally from:
 *  linux/arch/arm/mach-ep93xx/core.c
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/gpio/driver.h>
#include <linux/bitops.h>

#define EP93XX_GPIO_F_INT_STATUS 0x5c
#define EP93XX_GPIO_A_INT_STATUS 0xa0
#define EP93XX_GPIO_B_INT_STATUS 0xbc

/* Maximum value for gpio line identifiers */
#define EP93XX_GPIO_LINE_MAX 63

/* Maximum value for irq capable line identifiers */
#define EP93XX_GPIO_LINE_MAX_IRQ 23

/*
 * Static mapping of GPIO bank F IRQS:
 * F0..F7 (16..24) to irq 80..87.
 */
#define EP93XX_GPIO_F_IRQ_BASE 80

struct ep93xx_gpio {
	void __iomem		*base;
	struct gpio_chip	gc[8];
};

/*************************************************************************
 * Interrupt handling for EP93xx on-chip GPIOs
 *************************************************************************/
static unsigned char gpio_int_unmasked[3];
static unsigned char gpio_int_enabled[3];
static unsigned char gpio_int_type1[3];
static unsigned char gpio_int_type2[3];
static unsigned char gpio_int_debounce[3];

/* Port ordering is: A B F */
static const u8 int_type1_register_offset[3]	= { 0x90, 0xac, 0x4c };
static const u8 int_type2_register_offset[3]	= { 0x94, 0xb0, 0x50 };
static const u8 eoi_register_offset[3]		= { 0x98, 0xb4, 0x54 };
static const u8 int_en_register_offset[3]	= { 0x9c, 0xb8, 0x58 };
static const u8 int_debounce_register_offset[3]	= { 0xa8, 0xc4, 0x64 };

static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigned port)
{
	BUG_ON(port > 2);

	writeb_relaxed(0, epg->base + int_en_register_offset[port]);

	writeb_relaxed(gpio_int_type2[port],
		       epg->base + int_type2_register_offset[port]);

	writeb_relaxed(gpio_int_type1[port],
		       epg->base + int_type1_register_offset[port]);

	writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
	       epg->base + int_en_register_offset[port]);
}

static int ep93xx_gpio_port(struct gpio_chip *gc)
{
	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	int port = 0;

	while (port < ARRAY_SIZE(epg->gc) && gc != &epg->gc[port])
		port++;

	/* This should not happen but is there as a last safeguard */
	if (port == ARRAY_SIZE(epg->gc)) {
		pr_crit("can't find the GPIO port\n");
		return 0;
	}

	return port;
}

static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
				     unsigned int offset, bool enable)
{
	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	int port = ep93xx_gpio_port(gc);
	int port_mask = BIT(offset);

	if (enable)
		gpio_int_debounce[port] |= port_mask;
	else
		gpio_int_debounce[port] &= ~port_mask;

	writeb(gpio_int_debounce[port],
	       epg->base + int_debounce_register_offset[port]);
}

static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
{
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	struct irq_chip *irqchip = irq_desc_get_chip(desc);
	unsigned long stat;
	int offset;

	chained_irq_enter(irqchip, desc);

	/*
	 * Dispatch the IRQs to the irqdomain of each A and B
	 * gpiochip irqdomains depending on what has fired.
	 * The tricky part is that the IRQ line is shared
	 * between bank A and B and each has their own gpiochip.
	 */
	stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
	for_each_set_bit(offset, &stat, 8)
		generic_handle_irq(irq_find_mapping(epg->gc[0].irq.domain,
						    offset));

	stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
	for_each_set_bit(offset, &stat, 8)
		generic_handle_irq(irq_find_mapping(epg->gc[1].irq.domain,
						    offset));

	chained_irq_exit(irqchip, desc);
}

static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
{
	/*
	 * map discontiguous hw irq range to continuous sw irq range:
	 *
	 *  IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7}
	 */
	struct irq_chip *irqchip = irq_desc_get_chip(desc);
	unsigned int irq = irq_desc_get_irq(desc);
	int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
	int gpio_irq = EP93XX_GPIO_F_IRQ_BASE + port_f_idx;

	chained_irq_enter(irqchip, desc);
	generic_handle_irq(gpio_irq);
	chained_irq_exit(irqchip, desc);
}

static void ep93xx_gpio_irq_ack(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	int port = ep93xx_gpio_port(gc);
	int port_mask = BIT(d->irq & 7);

	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
		gpio_int_type2[port] ^= port_mask; /* switch edge direction */
		ep93xx_gpio_update_int_params(epg, port);
	}

	writeb(port_mask, epg->base + eoi_register_offset[port]);
}

static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	int port = ep93xx_gpio_port(gc);
	int port_mask = BIT(d->irq & 7);

	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
		gpio_int_type2[port] ^= port_mask; /* switch edge direction */

	gpio_int_unmasked[port] &= ~port_mask;
	ep93xx_gpio_update_int_params(epg, port);

	writeb(port_mask, epg->base + eoi_register_offset[port]);
}

static void ep93xx_gpio_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	int port = ep93xx_gpio_port(gc);

	gpio_int_unmasked[port] &= ~BIT(d->irq & 7);
	ep93xx_gpio_update_int_params(epg, port);
}

static void ep93xx_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	int port = ep93xx_gpio_port(gc);

	gpio_int_unmasked[port] |= BIT(d->irq & 7);
	ep93xx_gpio_update_int_params(epg, port);
}

/*
 * gpio_int_type1 controls whether the interrupt is level (0) or
 * edge (1) triggered, while gpio_int_type2 controls whether it
 * triggers on low/falling (0) or high/rising (1).
 */
static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	int port = ep93xx_gpio_port(gc);
	int offset = d->irq & 7;
	int port_mask = BIT(offset);
	irq_flow_handler_t handler;

	gc->direction_input(gc, offset);

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		gpio_int_type1[port] |= port_mask;
		gpio_int_type2[port] |= port_mask;
		handler = handle_edge_irq;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		gpio_int_type1[port] |= port_mask;
		gpio_int_type2[port] &= ~port_mask;
		handler = handle_edge_irq;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		gpio_int_type1[port] &= ~port_mask;
		gpio_int_type2[port] |= port_mask;
		handler = handle_level_irq;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		gpio_int_type1[port] &= ~port_mask;
		gpio_int_type2[port] &= ~port_mask;
		handler = handle_level_irq;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		gpio_int_type1[port] |= port_mask;
		/* set initial polarity based on current input level */
		if (gc->get(gc, offset))
			gpio_int_type2[port] &= ~port_mask; /* falling */
		else
			gpio_int_type2[port] |= port_mask; /* rising */
		handler = handle_edge_irq;
		break;
	default:
		return -EINVAL;
	}

	irq_set_handler_locked(d, handler);

	gpio_int_enabled[port] |= port_mask;

	ep93xx_gpio_update_int_params(epg, port);

	return 0;
}

static struct irq_chip ep93xx_gpio_irq_chip = {
	.name		= "GPIO",
	.irq_ack	= ep93xx_gpio_irq_ack,
	.irq_mask_ack	= ep93xx_gpio_irq_mask_ack,
	.irq_mask	= ep93xx_gpio_irq_mask,
	.irq_unmask	= ep93xx_gpio_irq_unmask,
	.irq_set_type	= ep93xx_gpio_irq_type,
};

static int ep93xx_gpio_init_irq(struct platform_device *pdev,
				struct ep93xx_gpio *epg)
{
	int ab_parent_irq = platform_get_irq(pdev, 0);
	struct device *dev = &pdev->dev;
	int gpio_irq;
	int ret;
	int i;

	/* The A bank */
	ret = gpiochip_irqchip_add(&epg->gc[0], &ep93xx_gpio_irq_chip,
                                   64, handle_level_irq,
                                   IRQ_TYPE_NONE);
	if (ret) {
		dev_err(dev, "Could not add irqchip 0\n");
		return ret;
	}
	gpiochip_set_chained_irqchip(&epg->gc[0], &ep93xx_gpio_irq_chip,
				     ab_parent_irq,
				     ep93xx_gpio_ab_irq_handler);

	/* The B bank */
	ret = gpiochip_irqchip_add(&epg->gc[1], &ep93xx_gpio_irq_chip,
                                   72, handle_level_irq,
                                   IRQ_TYPE_NONE);
	if (ret) {
		dev_err(dev, "Could not add irqchip 1\n");
		return ret;
	}
	gpiochip_set_chained_irqchip(&epg->gc[1], &ep93xx_gpio_irq_chip,
				     ab_parent_irq,
				     ep93xx_gpio_ab_irq_handler);

	/* The F bank */
	for (i = 0; i < 8; i++) {
		gpio_irq = EP93XX_GPIO_F_IRQ_BASE + i;
		irq_set_chip_data(gpio_irq, &epg->gc[5]);
		irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
					 handle_level_irq);
		irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
	}

	for (i = 1; i <= 8; i++)
		irq_set_chained_handler_and_data(platform_get_irq(pdev, i),
						 ep93xx_gpio_f_irq_handler,
						 &epg->gc[i]);
	return 0;
}


/*************************************************************************
 * gpiolib interface for EP93xx on-chip GPIOs
 *************************************************************************/
struct ep93xx_gpio_bank {
	const char	*label;
	int		data;
	int		dir;
	int		base;
	bool		has_irq;
};

#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _has_irq)	\
	{							\
		.label		= _label,			\
		.data		= _data,			\
		.dir		= _dir,				\
		.base		= _base,			\
		.has_irq	= _has_irq,			\
	}

static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
	EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true), /* Bank A has 8 IRQs */
	EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true), /* Bank B has 8 IRQs */
	EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
	EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
	EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
	EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true), /* Bank F has 8 IRQs */
	EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
	EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
};

static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
				  unsigned long config)
{
	u32 debounce;

	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
		return -ENOTSUPP;

	debounce = pinconf_to_config_argument(config);
	ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false);

	return 0;
}

static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, unsigned offset)
{
	return EP93XX_GPIO_F_IRQ_BASE + offset;
}

static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev,
				struct ep93xx_gpio *epg,
				struct ep93xx_gpio_bank *bank)
{
	void __iomem *data = epg->base + bank->data;
	void __iomem *dir = epg->base + bank->dir;
	int err;

	err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
	if (err)
		return err;

	gc->label = bank->label;
	gc->base = bank->base;

	if (bank->has_irq)
		gc->set_config = ep93xx_gpio_set_config;

	return devm_gpiochip_add_data(dev, gc, epg);
}

static int ep93xx_gpio_probe(struct platform_device *pdev)
{
	struct ep93xx_gpio *epg;
	struct resource *res;
	int i;
	struct device *dev = &pdev->dev;

	epg = devm_kzalloc(dev, sizeof(*epg), GFP_KERNEL);
	if (!epg)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	epg->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(epg->base))
		return PTR_ERR(epg->base);

	for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
		struct gpio_chip *gc = &epg->gc[i];
		struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];

		if (ep93xx_gpio_add_bank(gc, &pdev->dev, epg, bank))
			dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
				 bank->label);
		/* Only bank F has especially funky IRQ handling */
		if (i == 5)
			gc->to_irq = ep93xx_gpio_f_to_irq;
	}

	ep93xx_gpio_init_irq(pdev, epg);

	return 0;
}

static struct platform_driver ep93xx_gpio_driver = {
	.driver		= {
		.name	= "gpio-ep93xx",
	},
	.probe		= ep93xx_gpio_probe,
};

static int __init ep93xx_gpio_init(void)
{
	return platform_driver_register(&ep93xx_gpio_driver);
}
postcore_initcall(ep93xx_gpio_init);

MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
		"H Hartley Sweeten <hsweeten@visionengravers.com>");
MODULE_DESCRIPTION("EP93XX GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
68b64931	1	// SPDX-License-Identifier: GPL-2.0
b685004f	2	/*
b685004f RM	3	* Generic EP93xx GPIO handling
b685004f RM	4	*
1c5454ee	5	* Copyright (c) 2008 Ryan Mallon
1e4c8842	6	* Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
b685004f RM	7	*
	8	* Based on code originally from:
	9	* linux/arch/arm/mach-ep93xx/core.c
b685004f RM	10	*/
	11
	12	#include <linux/init.h>
bb207ef1	13	#include <linux/module.h>
1e4c8842	14	#include <linux/platform_device.h>
fced80c7	15	#include <linux/io.h>
595c050d	16	#include <linux/irq.h>
1e4c8842	17	#include <linux/slab.h>
0f4630f3	18	#include <linux/gpio/driver.h>
51ba88e3	19	#include <linux/bitops.h>
b685004f	20
991ce74e LW	21	#define EP93XX_GPIO_F_INT_STATUS 0x5c
	22	#define EP93XX_GPIO_A_INT_STATUS 0xa0
	23	#define EP93XX_GPIO_B_INT_STATUS 0xbc
4c2baed3 AB	24
	25	/* Maximum value for gpio line identifiers */
	26	#define EP93XX_GPIO_LINE_MAX 63
	27
	28	/* Maximum value for irq capable line identifiers */
	29	#define EP93XX_GPIO_LINE_MAX_IRQ 23
	30
d875cc27	31	/*
a419a3d9 LW	32	* Static mapping of GPIO bank F IRQS:
a419a3d9 LW	33	* F0..F7 (16..24) to irq 80..87.
d875cc27	34	*/
a419a3d9	35	#define EP93XX_GPIO_F_IRQ_BASE 80
d875cc27	36
1e4c8842	37	struct ep93xx_gpio {
1d2bb17a	38	void __iomem *base;
0f4630f3	39	struct gpio_chip gc[8];
1e4c8842 HS	40	};
1e4c8842 HS	41
d056ab78	42	/*************************************************************************
4742723c	43	* Interrupt handling for EP93xx on-chip GPIOs
d056ab78 HS	44	*************************************************************************/
	45	static unsigned char gpio_int_unmasked[3];
	46	static unsigned char gpio_int_enabled[3];
	47	static unsigned char gpio_int_type1[3];
	48	static unsigned char gpio_int_type2[3];
	49	static unsigned char gpio_int_debounce[3];
	50
	51	/* Port ordering is: A B F */
	52	static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
	53	static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
	54	static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
	55	static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
	56	static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
	57
991ce74e	58	static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigned port)
d056ab78 HS	59	{
	60	BUG_ON(port > 2);
	61
991ce74e	62	writeb_relaxed(0, epg->base + int_en_register_offset[port]);
d056ab78	63
d27e06ac	64	writeb_relaxed(gpio_int_type2[port],
991ce74e	65	epg->base + int_type2_register_offset[port]);
d056ab78	66
d27e06ac	67	writeb_relaxed(gpio_int_type1[port],
991ce74e	68	epg->base + int_type1_register_offset[port]);
d056ab78	69
d27e06ac	70	writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
991ce74e	71	epg->base + int_en_register_offset[port]);
d056ab78 HS	72	}
d056ab78 HS	73
fd935fc4	74	static int ep93xx_gpio_port(struct gpio_chip *gc)
d056ab78	75	{
fd935fc4 LW	76	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	77	int port = 0;
	78
f40f7307	79	while (port < ARRAY_SIZE(epg->gc) && gc != &epg->gc[port])
fd935fc4 LW	80	port++;
	81
	82	/* This should not happen but is there as a last safeguard */
f6d9af47	83	if (port == ARRAY_SIZE(epg->gc)) {
fd935fc4 LW	84	pr_crit("can't find the GPIO port\n");
	85	return 0;
	86	}
	87
	88	return port;
	89	}
	90
	91	static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
	92	unsigned int offset, bool enable)
	93	{
	94	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
	95	int port = ep93xx_gpio_port(gc);
	96	int port_mask = BIT(offset);
d056ab78 HS	97
	98	if (enable)
	99	gpio_int_debounce[port] \|= port_mask;
	100	else
	101	gpio_int_debounce[port] &= ~port_mask;
	102
d27e06ac	103	writeb(gpio_int_debounce[port],
991ce74e	104	epg->base + int_debounce_register_offset[port]);
d056ab78	105	}
d056ab78	106
bd0b9ac4	107	static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
d056ab78	108	{
991ce74e LW	109	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
991ce74e LW	110	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
99399f40	111	struct irq_chip *irqchip = irq_desc_get_chip(desc);
68491b07 LW	112	unsigned long stat;
68491b07 LW	113	int offset;
d056ab78	114
99399f40 LW	115	chained_irq_enter(irqchip, desc);
99399f40 LW	116
a419a3d9 LW	117	/*
	118	* Dispatch the IRQs to the irqdomain of each A and B
	119	* gpiochip irqdomains depending on what has fired.
	120	* The tricky part is that the IRQ line is shared
	121	* between bank A and B and each has their own gpiochip.
	122	*/
68491b07	123	stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
a419a3d9 LW	124	for_each_set_bit(offset, &stat, 8)
	125	generic_handle_irq(irq_find_mapping(epg->gc[0].irq.domain,
	126	offset));
d056ab78	127
68491b07	128	stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
a419a3d9 LW	129	for_each_set_bit(offset, &stat, 8)
	130	generic_handle_irq(irq_find_mapping(epg->gc[1].irq.domain,
	131	offset));
99399f40 LW	132
99399f40 LW	133	chained_irq_exit(irqchip, desc);
d056ab78 HS	134	}
d056ab78 HS	135
bd0b9ac4	136	static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
d056ab78 HS	137	{
d056ab78 HS	138	/*
25985edc	139	* map discontiguous hw irq range to continuous sw irq range:
d056ab78	140	*
d875cc27	141	* IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7}
d056ab78	142	*/
99399f40	143	struct irq_chip *irqchip = irq_desc_get_chip(desc);
e43ea7a7	144	unsigned int irq = irq_desc_get_irq(desc);
d056ab78	145	int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
a419a3d9	146	int gpio_irq = EP93XX_GPIO_F_IRQ_BASE + port_f_idx;
d056ab78	147
99399f40	148	chained_irq_enter(irqchip, desc);
d056ab78	149	generic_handle_irq(gpio_irq);
99399f40	150	chained_irq_exit(irqchip, desc);
d056ab78 HS	151	}
d056ab78 HS	152
c0afc916	153	static void ep93xx_gpio_irq_ack(struct irq_data *d)
d056ab78	154	{
991ce74e LW	155	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
991ce74e LW	156	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
51ba88e3 LW	157	int port = ep93xx_gpio_port(gc);
51ba88e3 LW	158	int port_mask = BIT(d->irq & 7);
d056ab78	159
d1735a2e	160	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
d056ab78	161	gpio_int_type2[port] ^= port_mask; /* switch edge direction */
991ce74e	162	ep93xx_gpio_update_int_params(epg, port);
d056ab78 HS	163	}
d056ab78 HS	164
991ce74e	165	writeb(port_mask, epg->base + eoi_register_offset[port]);
d056ab78 HS	166	}
d056ab78 HS	167
c0afc916	168	static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
d056ab78	169	{
991ce74e LW	170	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
991ce74e LW	171	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
51ba88e3 LW	172	int port = ep93xx_gpio_port(gc);
51ba88e3 LW	173	int port_mask = BIT(d->irq & 7);
d056ab78	174
d1735a2e	175	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
d056ab78 HS	176	gpio_int_type2[port] ^= port_mask; /* switch edge direction */
	177
	178	gpio_int_unmasked[port] &= ~port_mask;
991ce74e	179	ep93xx_gpio_update_int_params(epg, port);
d056ab78	180
991ce74e	181	writeb(port_mask, epg->base + eoi_register_offset[port]);
d056ab78 HS	182	}
d056ab78 HS	183
c0afc916	184	static void ep93xx_gpio_irq_mask(struct irq_data *d)
d056ab78	185	{
991ce74e LW	186	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
991ce74e LW	187	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
51ba88e3	188	int port = ep93xx_gpio_port(gc);
d056ab78	189
51ba88e3	190	gpio_int_unmasked[port] &= ~BIT(d->irq & 7);
991ce74e	191	ep93xx_gpio_update_int_params(epg, port);
d056ab78 HS	192	}
d056ab78 HS	193
c0afc916	194	static void ep93xx_gpio_irq_unmask(struct irq_data *d)
d056ab78	195	{
991ce74e LW	196	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
991ce74e LW	197	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
51ba88e3	198	int port = ep93xx_gpio_port(gc);
d056ab78	199
51ba88e3	200	gpio_int_unmasked[port] \|= BIT(d->irq & 7);
991ce74e	201	ep93xx_gpio_update_int_params(epg, port);
d056ab78 HS	202	}
	203
	204	/*
	205	* gpio_int_type1 controls whether the interrupt is level (0) or
	206	* edge (1) triggered, while gpio_int_type2 controls whether it
	207	* triggers on low/falling (0) or high/rising (1).
	208	*/
c0afc916	209	static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
d056ab78	210	{
991ce74e LW	211	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
991ce74e LW	212	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
51ba88e3 LW	213	int port = ep93xx_gpio_port(gc);
	214	int offset = d->irq & 7;
	215	int port_mask = BIT(offset);
d1735a2e	216	irq_flow_handler_t handler;
d056ab78	217
51ba88e3	218	gc->direction_input(gc, offset);
d056ab78 HS	219
	220	switch (type) {
	221	case IRQ_TYPE_EDGE_RISING:
	222	gpio_int_type1[port] \|= port_mask;
	223	gpio_int_type2[port] \|= port_mask;
d1735a2e	224	handler = handle_edge_irq;
d056ab78 HS	225	break;
	226	case IRQ_TYPE_EDGE_FALLING:
	227	gpio_int_type1[port] \|= port_mask;
	228	gpio_int_type2[port] &= ~port_mask;
d1735a2e	229	handler = handle_edge_irq;
d056ab78 HS	230	break;
	231	case IRQ_TYPE_LEVEL_HIGH:
	232	gpio_int_type1[port] &= ~port_mask;
	233	gpio_int_type2[port] \|= port_mask;
d1735a2e	234	handler = handle_level_irq;
d056ab78 HS	235	break;
	236	case IRQ_TYPE_LEVEL_LOW:
	237	gpio_int_type1[port] &= ~port_mask;
	238	gpio_int_type2[port] &= ~port_mask;
d1735a2e	239	handler = handle_level_irq;
d056ab78 HS	240	break;
	241	case IRQ_TYPE_EDGE_BOTH:
	242	gpio_int_type1[port] \|= port_mask;
	243	/* set initial polarity based on current input level */
51ba88e3	244	if (gc->get(gc, offset))
d056ab78 HS	245	gpio_int_type2[port] &= ~port_mask; /* falling */
	246	else
	247	gpio_int_type2[port] \|= port_mask; /* rising */
d1735a2e	248	handler = handle_edge_irq;
d056ab78 HS	249	break;
d056ab78 HS	250	default:
d056ab78 HS	251	return -EINVAL;
	252	}
	253
72b2a9ef	254	irq_set_handler_locked(d, handler);
d056ab78	255
d1735a2e	256	gpio_int_enabled[port] \|= port_mask;
d056ab78	257
991ce74e	258	ep93xx_gpio_update_int_params(epg, port);
d056ab78 HS	259
	260	return 0;
	261	}
	262
	263	static struct irq_chip ep93xx_gpio_irq_chip = {
	264	.name = "GPIO",
c0afc916 LB	265	.irq_ack = ep93xx_gpio_irq_ack,
	266	.irq_mask_ack = ep93xx_gpio_irq_mask_ack,
	267	.irq_mask = ep93xx_gpio_irq_mask,
	268	.irq_unmask = ep93xx_gpio_irq_unmask,
	269	.irq_set_type = ep93xx_gpio_irq_type,
d056ab78 HS	270	};
d056ab78 HS	271
a419a3d9 LW	272	static int ep93xx_gpio_init_irq(struct platform_device *pdev,
a419a3d9 LW	273	struct ep93xx_gpio *epg)
d056ab78	274	{
a419a3d9 LW	275	int ab_parent_irq = platform_get_irq(pdev, 0);
a419a3d9 LW	276	struct device *dev = &pdev->dev;
d056ab78	277	int gpio_irq;
a419a3d9	278	int ret;
4c2baed3	279	int i;
d056ab78	280
991ce74e	281	/* The A bank */
a419a3d9 LW	282	ret = gpiochip_irqchip_add(&epg->gc[0], &ep93xx_gpio_irq_chip,
	283	64, handle_level_irq,
	284	IRQ_TYPE_NONE);
	285	if (ret) {
	286	dev_err(dev, "Could not add irqchip 0\n");
	287	return ret;
991ce74e	288	}
a419a3d9 LW	289	gpiochip_set_chained_irqchip(&epg->gc[0], &ep93xx_gpio_irq_chip,
	290	ab_parent_irq,
	291	ep93xx_gpio_ab_irq_handler);
	292
991ce74e	293	/* The B bank */
a419a3d9 LW	294	ret = gpiochip_irqchip_add(&epg->gc[1], &ep93xx_gpio_irq_chip,
	295	72, handle_level_irq,
	296	IRQ_TYPE_NONE);
	297	if (ret) {
	298	dev_err(dev, "Could not add irqchip 1\n");
	299	return ret;
991ce74e	300	}
a419a3d9 LW	301	gpiochip_set_chained_irqchip(&epg->gc[1], &ep93xx_gpio_irq_chip,
	302	ab_parent_irq,
	303	ep93xx_gpio_ab_irq_handler);
	304
991ce74e	305	/* The F bank */
d875cc27	306	for (i = 0; i < 8; i++) {
a419a3d9	307	gpio_irq = EP93XX_GPIO_F_IRQ_BASE + i;
991ce74e	308	irq_set_chip_data(gpio_irq, &epg->gc[5]);
f38c02f3 TG	309	irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
f38c02f3 TG	310	handle_level_irq);
23393d49	311	irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
d056ab78 HS	312	}
d056ab78 HS	313
4c2baed3	314	for (i = 1; i <= 8; i++)
991ce74e LW	315	irq_set_chained_handler_and_data(platform_get_irq(pdev, i),
	316	ep93xx_gpio_f_irq_handler,
	317	&epg->gc[i]);
a419a3d9	318	return 0;
d056ab78 HS	319	}
	320
	321
	322	/*************************************************************************
	323	* gpiolib interface for EP93xx on-chip GPIOs
	324	*************************************************************************/
1e4c8842 HS	325	struct ep93xx_gpio_bank {
	326	const char *label;
	327	int data;
	328	int dir;
	329	int base;
3c38b3a3	330	bool has_irq;
b685004f RM	331	};
b685004f RM	332
3c38b3a3	333	#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _has_irq) \
1e4c8842 HS	334	{ \
	335	.label = _label, \
	336	.data = _data, \
	337	.dir = _dir, \
	338	.base = _base, \
3c38b3a3	339	.has_irq = _has_irq, \
1e4c8842	340	}
b685004f	341
1e4c8842	342	static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
3c38b3a3 LW	343	EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true), /* Bank A has 8 IRQs */
3c38b3a3 LW	344	EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true), /* Bank B has 8 IRQs */
1e4c8842 HS	345	EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
	346	EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
	347	EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
3c38b3a3	348	EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true), /* Bank F has 8 IRQs */
1e4c8842 HS	349	EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
	350	EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
	351	};
	352
991ce74e	353	static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
2956b5d9	354	unsigned long config)
b685004f	355	{
2956b5d9 MW	356	u32 debounce;
	357
	358	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
	359	return -ENOTSUPP;
b685004f	360
2956b5d9	361	debounce = pinconf_to_config_argument(config);
fd935fc4	362	ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false);
b685004f RM	363
	364	return 0;
	365	}
	366
a419a3d9	367	static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, unsigned offset)
257af9f9	368	{
a419a3d9	369	return EP93XX_GPIO_F_IRQ_BASE + offset;
257af9f9 LW	370	}
257af9f9 LW	371
0f4630f3	372	static int ep93xx_gpio_add_bank(struct gpio_chip gc, struct device dev,
991ce74e LW	373	struct ep93xx_gpio *epg,
991ce74e LW	374	struct ep93xx_gpio_bank *bank)
b685004f	375	{
991ce74e LW	376	void __iomem *data = epg->base + bank->data;
991ce74e LW	377	void __iomem *dir = epg->base + bank->dir;
1e4c8842	378	int err;
b685004f	379
0f4630f3	380	err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
1e4c8842 HS	381	if (err)
1e4c8842 HS	382	return err;
b685004f	383
0f4630f3 LW	384	gc->label = bank->label;
0f4630f3 LW	385	gc->base = bank->base;
b685004f	386
a419a3d9	387	if (bank->has_irq)
2956b5d9	388	gc->set_config = ep93xx_gpio_set_config;
b685004f	389
991ce74e	390	return devm_gpiochip_add_data(dev, gc, epg);
b685004f RM	391	}
b685004f RM	392
3836309d	393	static int ep93xx_gpio_probe(struct platform_device *pdev)
b685004f	394	{
1d2bb17a	395	struct ep93xx_gpio *epg;
1e4c8842	396	struct resource *res;
1e4c8842	397	int i;
1aeede0b	398	struct device *dev = &pdev->dev;
b685004f	399
1d2bb17a LW	400	epg = devm_kzalloc(dev, sizeof(*epg), GFP_KERNEL);
1d2bb17a LW	401	if (!epg)
1e4c8842	402	return -ENOMEM;
b685004f	403
1e4c8842	404	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1d2bb17a LW	405	epg->base = devm_ioremap_resource(dev, res);
	406	if (IS_ERR(epg->base))
	407	return PTR_ERR(epg->base);
5d046af0	408
1e4c8842	409	for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
1d2bb17a	410	struct gpio_chip *gc = &epg->gc[i];
1e4c8842	411	struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
5d046af0	412
991ce74e	413	if (ep93xx_gpio_add_bank(gc, &pdev->dev, epg, bank))
1e4c8842	414	dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
a419a3d9 LW	415	bank->label);
	416	/* Only bank F has especially funky IRQ handling */
	417	if (i == 5)
	418	gc->to_irq = ep93xx_gpio_f_to_irq;
b685004f RM	419	}
b685004f RM	420
991ce74e	421	ep93xx_gpio_init_irq(pdev, epg);
b685004f	422
1e4c8842	423	return 0;
1e4c8842	424	}
fd015480	425
1e4c8842 HS	426	static struct platform_driver ep93xx_gpio_driver = {
	427	.driver = {
	428	.name = "gpio-ep93xx",
1e4c8842 HS	429	},
	430	.probe = ep93xx_gpio_probe,
	431	};
	432
	433	static int __init ep93xx_gpio_init(void)
	434	{
1e4c8842	435	return platform_driver_register(&ep93xx_gpio_driver);
b685004f	436	}
1e4c8842 HS	437	postcore_initcall(ep93xx_gpio_init);
	438
	439	MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
	440	"H Hartley Sweeten <hsweeten@visionengravers.com>");
	441	MODULE_DESCRIPTION("EP93XX GPIO driver");
	442	MODULE_LICENSE("GPL");