[linux-2.6-block.git] / drivers / gpio / gpio-em.c

/*
 * Emma Mobile GPIO Support - GIO
 *
 *  Copyright (C) 2012 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_data/gpio-em.h>

struct em_gio_priv {
	void __iomem *base0;
	void __iomem *base1;
	spinlock_t sense_lock;
	struct platform_device *pdev;
	struct gpio_chip gpio_chip;
	struct irq_chip irq_chip;
	struct irq_domain *irq_domain;
};

#define GIO_E1 0x00
#define GIO_E0 0x04
#define GIO_EM 0x04
#define GIO_OL 0x08
#define GIO_OH 0x0c
#define GIO_I 0x10
#define GIO_IIA 0x14
#define GIO_IEN 0x18
#define GIO_IDS 0x1c
#define GIO_IIM 0x1c
#define GIO_RAW 0x20
#define GIO_MST 0x24
#define GIO_IIR 0x28

#define GIO_IDT0 0x40
#define GIO_IDT1 0x44
#define GIO_IDT2 0x48
#define GIO_IDT3 0x4c
#define GIO_RAWBL 0x50
#define GIO_RAWBH 0x54
#define GIO_IRBL 0x58
#define GIO_IRBH 0x5c

#define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))

static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
{
	if (offs < GIO_IDT0)
		return ioread32(p->base0 + offs);
	else
		return ioread32(p->base1 + (offs - GIO_IDT0));
}

static inline void em_gio_write(struct em_gio_priv *p, int offs,
				unsigned long value)
{
	if (offs < GIO_IDT0)
		iowrite32(value, p->base0 + offs);
	else
		iowrite32(value, p->base1 + (offs - GIO_IDT0));
}

static void em_gio_irq_disable(struct irq_data *d)
{
	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);

	em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
}

static void em_gio_irq_enable(struct irq_data *d)
{
	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);

	em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
}

static int em_gio_irq_reqres(struct irq_data *d)
{
	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);

	if (gpio_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d))) {
		dev_err(p->gpio_chip.dev,
			"unable to lock HW IRQ %lu for IRQ\n",
			irqd_to_hwirq(d));
		return -EINVAL;
	}
	return 0;
}

static void em_gio_irq_relres(struct irq_data *d)
{
	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);

	gpio_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
}


#define GIO_ASYNC(x) (x + 8)

static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
	[IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
	[IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
	[IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
	[IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
	[IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
};

static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
{
	unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
	unsigned int reg, offset, shift;
	unsigned long flags;
	unsigned long tmp;

	if (!value)
		return -EINVAL;

	offset = irqd_to_hwirq(d);

	pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);

	/* 8 x 4 bit fields in 4 IDT registers */
	reg = GIO_IDT(offset >> 3);
	shift = (offset & 0x07) << 4;

	spin_lock_irqsave(&p->sense_lock, flags);

	/* disable the interrupt in IIA */
	tmp = em_gio_read(p, GIO_IIA);
	tmp &= ~BIT(offset);
	em_gio_write(p, GIO_IIA, tmp);

	/* change the sense setting in IDT */
	tmp = em_gio_read(p, reg);
	tmp &= ~(0xf << shift);
	tmp |= value << shift;
	em_gio_write(p, reg, tmp);

	/* clear pending interrupts */
	em_gio_write(p, GIO_IIR, BIT(offset));

	/* enable the interrupt in IIA */
	tmp = em_gio_read(p, GIO_IIA);
	tmp |= BIT(offset);
	em_gio_write(p, GIO_IIA, tmp);

	spin_unlock_irqrestore(&p->sense_lock, flags);

	return 0;
}

static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
{
	struct em_gio_priv *p = dev_id;
	unsigned long pending;
	unsigned int offset, irqs_handled = 0;

	while ((pending = em_gio_read(p, GIO_MST))) {
		offset = __ffs(pending);
		em_gio_write(p, GIO_IIR, BIT(offset));
		generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
		irqs_handled++;
	}

	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
}

static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
{
	return container_of(chip, struct em_gio_priv, gpio_chip);
}

static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
	return 0;
}

static int em_gio_get(struct gpio_chip *chip, unsigned offset)
{
	return (int)(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
}

static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
			 unsigned shift, int value)
{
	/* upper 16 bits contains mask and lower 16 actual value */
	em_gio_write(gpio_to_priv(chip), reg,
		     (BIT(shift + 16)) | (value << shift));
}

static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	/* output is split into two registers */
	if (offset < 16)
		__em_gio_set(chip, GIO_OL, offset, value);
	else
		__em_gio_set(chip, GIO_OH, offset - 16, value);
}

static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
				   int value)
{
	/* write GPIO value to output before selecting output mode of pin */
	em_gio_set(chip, offset, value);
	em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
	return 0;
}

static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
}

static int em_gio_request(struct gpio_chip *chip, unsigned offset)
{
	return pinctrl_request_gpio(chip->base + offset);
}

static void em_gio_free(struct gpio_chip *chip, unsigned offset)
{
	pinctrl_free_gpio(chip->base + offset);

	/* Set the GPIO as an input to ensure that the next GPIO request won't
	* drive the GPIO pin as an output.
	*/
	em_gio_direction_input(chip, offset);
}

static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq,
				 irq_hw_number_t hwirq)
{
	struct em_gio_priv *p = h->host_data;

	pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq);

	irq_set_chip_data(irq, h->host_data);
	irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
	set_irq_flags(irq, IRQF_VALID); /* kill me now */
	return 0;
}

static struct irq_domain_ops em_gio_irq_domain_ops = {
	.map	= em_gio_irq_domain_map,
	.xlate	= irq_domain_xlate_twocell,
};

static int em_gio_probe(struct platform_device *pdev)
{
	struct gpio_em_config pdata_dt;
	struct gpio_em_config *pdata = dev_get_platdata(&pdev->dev);
	struct em_gio_priv *p;
	struct resource *io[2], *irq[2];
	struct gpio_chip *gpio_chip;
	struct irq_chip *irq_chip;
	const char *name = dev_name(&pdev->dev);
	int ret;

	p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
	if (!p) {
		ret = -ENOMEM;
		goto err0;
	}

	p->pdev = pdev;
	platform_set_drvdata(pdev, p);
	spin_lock_init(&p->sense_lock);

	io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);

	if (!io[0] || !io[1] || !irq[0] || !irq[1]) {
		dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
		ret = -EINVAL;
		goto err0;
	}

	p->base0 = devm_ioremap_nocache(&pdev->dev, io[0]->start,
					resource_size(io[0]));
	if (!p->base0) {
		dev_err(&pdev->dev, "failed to remap low I/O memory\n");
		ret = -ENXIO;
		goto err0;
	}

	p->base1 = devm_ioremap_nocache(&pdev->dev, io[1]->start,
				   resource_size(io[1]));
	if (!p->base1) {
		dev_err(&pdev->dev, "failed to remap high I/O memory\n");
		ret = -ENXIO;
		goto err0;
	}

	if (!pdata) {
		memset(&pdata_dt, 0, sizeof(pdata_dt));
		pdata = &pdata_dt;

		if (of_property_read_u32(pdev->dev.of_node, "ngpios",
					 &pdata->number_of_pins)) {
			dev_err(&pdev->dev, "Missing ngpios OF property\n");
			ret = -EINVAL;
			goto err0;
		}

		ret = of_alias_get_id(pdev->dev.of_node, "gpio");
		if (ret < 0) {
			dev_err(&pdev->dev, "Couldn't get OF id\n");
			goto err0;
		}
		pdata->gpio_base = ret * 32; /* 32 GPIOs per instance */
	}

	gpio_chip = &p->gpio_chip;
	gpio_chip->of_node = pdev->dev.of_node;
	gpio_chip->direction_input = em_gio_direction_input;
	gpio_chip->get = em_gio_get;
	gpio_chip->direction_output = em_gio_direction_output;
	gpio_chip->set = em_gio_set;
	gpio_chip->to_irq = em_gio_to_irq;
	gpio_chip->request = em_gio_request;
	gpio_chip->free = em_gio_free;
	gpio_chip->label = name;
	gpio_chip->dev = &pdev->dev;
	gpio_chip->owner = THIS_MODULE;
	gpio_chip->base = pdata->gpio_base;
	gpio_chip->ngpio = pdata->number_of_pins;

	irq_chip = &p->irq_chip;
	irq_chip->name = name;
	irq_chip->irq_mask = em_gio_irq_disable;
	irq_chip->irq_unmask = em_gio_irq_enable;
	irq_chip->irq_set_type = em_gio_irq_set_type;
	irq_chip->irq_request_resources = em_gio_irq_reqres;
	irq_chip->irq_release_resources = em_gio_irq_relres;
	irq_chip->flags	= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;

	p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
					      pdata->number_of_pins,
					      pdata->irq_base,
					      &em_gio_irq_domain_ops, p);
	if (!p->irq_domain) {
		ret = -ENXIO;
		dev_err(&pdev->dev, "cannot initialize irq domain\n");
		goto err0;
	}

	if (devm_request_irq(&pdev->dev, irq[0]->start,
			     em_gio_irq_handler, 0, name, p)) {
		dev_err(&pdev->dev, "failed to request low IRQ\n");
		ret = -ENOENT;
		goto err1;
	}

	if (devm_request_irq(&pdev->dev, irq[1]->start,
			     em_gio_irq_handler, 0, name, p)) {
		dev_err(&pdev->dev, "failed to request high IRQ\n");
		ret = -ENOENT;
		goto err1;
	}

	ret = gpiochip_add(gpio_chip);
	if (ret) {
		dev_err(&pdev->dev, "failed to add GPIO controller\n");
		goto err1;
	}

	if (pdata->pctl_name) {
		ret = gpiochip_add_pin_range(gpio_chip, pdata->pctl_name, 0,
					     gpio_chip->base, gpio_chip->ngpio);
		if (ret < 0)
			dev_warn(&pdev->dev, "failed to add pin range\n");
	}
	return 0;

err1:
	irq_domain_remove(p->irq_domain);
err0:
	return ret;
}

static int em_gio_remove(struct platform_device *pdev)
{
	struct em_gio_priv *p = platform_get_drvdata(pdev);
	int ret;

	ret = gpiochip_remove(&p->gpio_chip);
	if (ret)
		return ret;

	irq_domain_remove(p->irq_domain);
	return 0;
}

static const struct of_device_id em_gio_dt_ids[] = {
	{ .compatible = "renesas,em-gio", },
	{},
};
MODULE_DEVICE_TABLE(of, em_gio_dt_ids);

static struct platform_driver em_gio_device_driver = {
	.probe		= em_gio_probe,
	.remove		= em_gio_remove,
	.driver		= {
		.name	= "em_gio",
		.of_match_table = em_gio_dt_ids,
		.owner		= THIS_MODULE,
	}
};

static int __init em_gio_init(void)
{
	return platform_driver_register(&em_gio_device_driver);
}
postcore_initcall(em_gio_init);

static void __exit em_gio_exit(void)
{
	platform_driver_unregister(&em_gio_device_driver);
}
module_exit(em_gio_exit);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
a07e103e MD	1	/*
	2	* Emma Mobile GPIO Support - GIO
	3	*
	4	* Copyright (C) 2012 Magnus Damm
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/ioport.h>
	25	#include <linux/io.h>
	26	#include <linux/irq.h>
	27	#include <linux/irqdomain.h>
	28	#include <linux/bitops.h>
	29	#include <linux/err.h>
	30	#include <linux/gpio.h>
	31	#include <linux/slab.h>
	32	#include <linux/module.h>
640efa08	33	#include <linux/pinctrl/consumer.h>
a07e103e MD	34	#include <linux/platform_data/gpio-em.h>
	35
	36	struct em_gio_priv {
	37	void __iomem *base0;
	38	void __iomem *base1;
a07e103e MD	39	spinlock_t sense_lock;
	40	struct platform_device *pdev;
	41	struct gpio_chip gpio_chip;
	42	struct irq_chip irq_chip;
	43	struct irq_domain *irq_domain;
	44	};
	45
	46	#define GIO_E1 0x00
	47	#define GIO_E0 0x04
	48	#define GIO_EM 0x04
	49	#define GIO_OL 0x08
	50	#define GIO_OH 0x0c
	51	#define GIO_I 0x10
	52	#define GIO_IIA 0x14
	53	#define GIO_IEN 0x18
	54	#define GIO_IDS 0x1c
	55	#define GIO_IIM 0x1c
	56	#define GIO_RAW 0x20
	57	#define GIO_MST 0x24
	58	#define GIO_IIR 0x28
	59
	60	#define GIO_IDT0 0x40
	61	#define GIO_IDT1 0x44
	62	#define GIO_IDT2 0x48
	63	#define GIO_IDT3 0x4c
	64	#define GIO_RAWBL 0x50
	65	#define GIO_RAWBH 0x54
	66	#define GIO_IRBL 0x58
	67	#define GIO_IRBH 0x5c
	68
	69	#define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
	70
	71	static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
	72	{
	73	if (offs < GIO_IDT0)
	74	return ioread32(p->base0 + offs);
	75	else
	76	return ioread32(p->base1 + (offs - GIO_IDT0));
	77	}
	78
	79	static inline void em_gio_write(struct em_gio_priv *p, int offs,
	80	unsigned long value)
	81	{
	82	if (offs < GIO_IDT0)
	83	iowrite32(value, p->base0 + offs);
	84	else
	85	iowrite32(value, p->base1 + (offs - GIO_IDT0));
	86	}
	87
a07e103e MD	88	static void em_gio_irq_disable(struct irq_data *d)
a07e103e MD	89	{
a9f77c93	90	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
a07e103e MD	91
	92	em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
	93	}
	94
	95	static void em_gio_irq_enable(struct irq_data *d)
	96	{
a9f77c93	97	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
a07e103e MD	98
	99	em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
	100	}
	101
57ef0428	102	static int em_gio_irq_reqres(struct irq_data *d)
0dc61623 LW	103	{
	104	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
	105
57ef0428	106	if (gpio_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d))) {
0dc61623 LW	107	dev_err(p->gpio_chip.dev,
	108	"unable to lock HW IRQ %lu for IRQ\n",
	109	irqd_to_hwirq(d));
57ef0428 LW	110	return -EINVAL;
57ef0428 LW	111	}
0dc61623 LW	112	return 0;
	113	}
	114
57ef0428	115	static void em_gio_irq_relres(struct irq_data *d)
0dc61623 LW	116	{
	117	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
	118
0dc61623 LW	119	gpio_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
	120	}
	121
	122
a07e103e MD	123	#define GIO_ASYNC(x) (x + 8)
	124
	125	static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
	126	[IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
	127	[IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
	128	[IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
	129	[IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
	130	[IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
	131	};
	132
	133	static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
	134	{
	135	unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
a9f77c93	136	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
a07e103e MD	137	unsigned int reg, offset, shift;
	138	unsigned long flags;
	139	unsigned long tmp;
	140
	141	if (!value)
	142	return -EINVAL;
	143
	144	offset = irqd_to_hwirq(d);
	145
	146	pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
	147
	148	/* 8 x 4 bit fields in 4 IDT registers */
	149	reg = GIO_IDT(offset >> 3);
	150	shift = (offset & 0x07) << 4;
	151
	152	spin_lock_irqsave(&p->sense_lock, flags);
	153
	154	/* disable the interrupt in IIA */
	155	tmp = em_gio_read(p, GIO_IIA);
	156	tmp &= ~BIT(offset);
	157	em_gio_write(p, GIO_IIA, tmp);
	158
	159	/* change the sense setting in IDT */
	160	tmp = em_gio_read(p, reg);
	161	tmp &= ~(0xf << shift);
	162	tmp \|= value << shift;
	163	em_gio_write(p, reg, tmp);
	164
	165	/* clear pending interrupts */
	166	em_gio_write(p, GIO_IIR, BIT(offset));
	167
	168	/* enable the interrupt in IIA */
	169	tmp = em_gio_read(p, GIO_IIA);
	170	tmp \|= BIT(offset);
	171	em_gio_write(p, GIO_IIA, tmp);
	172
	173	spin_unlock_irqrestore(&p->sense_lock, flags);
	174
	175	return 0;
	176	}
	177
	178	static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
	179	{
	180	struct em_gio_priv *p = dev_id;
	181	unsigned long pending;
	182	unsigned int offset, irqs_handled = 0;
	183
	184	while ((pending = em_gio_read(p, GIO_MST))) {
	185	offset = __ffs(pending);
	186	em_gio_write(p, GIO_IIR, BIT(offset));
	187	generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
	188	irqs_handled++;
	189	}
	190
	191	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
	192	}
	193
	194	static inline struct em_gio_priv gpio_to_priv(struct gpio_chip chip)
	195	{
	196	return container_of(chip, struct em_gio_priv, gpio_chip);
	197	}
	198
	199	static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
	200	{
201	em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
202	return 0;
203	}
204
205	static int em_gio_get(struct gpio_chip *chip, unsigned offset)
206	{
207	return (int)(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
208	}
209
210	static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
211	unsigned shift, int value)
212	{
213	/* upper 16 bits contains mask and lower 16 actual value */
214	em_gio_write(gpio_to_priv(chip), reg,
5f077644	215	(BIT(shift + 16)) \| (value << shift));
a07e103e MD	216	}
	217
	218	static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
	219	{
	220	/* output is split into two registers */
	221	if (offset < 16)
	222	__em_gio_set(chip, GIO_OL, offset, value);
	223	else
	224	__em_gio_set(chip, GIO_OH, offset - 16, value);
	225	}
	226
	227	static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
	228	int value)
	229	{
	230	/* write GPIO value to output before selecting output mode of pin */
	231	em_gio_set(chip, offset, value);
	232	em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
	233	return 0;
	234	}
	235
	236	static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
	237	{
7385500a	238	return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
a07e103e MD	239	}
a07e103e MD	240
640efa08 MD	241	static int em_gio_request(struct gpio_chip *chip, unsigned offset)
	242	{
	243	return pinctrl_request_gpio(chip->base + offset);
	244	}
	245
	246	static void em_gio_free(struct gpio_chip *chip, unsigned offset)
	247	{
	248	pinctrl_free_gpio(chip->base + offset);
	249
	250	/* Set the GPIO as an input to ensure that the next GPIO request won't
	251	* drive the GPIO pin as an output.
	252	*/
	253	em_gio_direction_input(chip, offset);
	254	}
	255
2d61e3e9 LW	256	static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq,
2d61e3e9 LW	257	irq_hw_number_t hwirq)
a07e103e MD	258	{
	259	struct em_gio_priv *p = h->host_data;
	260
2d61e3e9	261	pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq);
a07e103e	262
2d61e3e9 LW	263	irq_set_chip_data(irq, h->host_data);
	264	irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
	265	set_irq_flags(irq, IRQF_VALID); /* kill me now */
a07e103e MD	266	return 0;
	267	}
	268
	269	static struct irq_domain_ops em_gio_irq_domain_ops = {
	270	.map = em_gio_irq_domain_map,
753c5983	271	.xlate = irq_domain_xlate_twocell,
a07e103e MD	272	};
a07e103e MD	273
3836309d	274	static int em_gio_probe(struct platform_device *pdev)
a07e103e	275	{
753c5983	276	struct gpio_em_config pdata_dt;
e56aee18	277	struct gpio_em_config *pdata = dev_get_platdata(&pdev->dev);
a07e103e MD	278	struct em_gio_priv *p;
	279	struct resource io[2], irq[2];
	280	struct gpio_chip *gpio_chip;
	281	struct irq_chip *irq_chip;
	282	const char *name = dev_name(&pdev->dev);
	283	int ret;
	284
1cfe6f8c	285	p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
a07e103e	286	if (!p) {
a07e103e MD	287	ret = -ENOMEM;
	288	goto err0;
	289	}
	290
	291	p->pdev = pdev;
	292	platform_set_drvdata(pdev, p);
	293	spin_lock_init(&p->sense_lock);
	294
	295	io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	296	io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	297	irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	298	irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
	299
753c5983 MD	300	if (!io[0] \|\| !io[1] \|\| !irq[0] \|\| !irq[1]) {
753c5983 MD	301	dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
a07e103e	302	ret = -EINVAL;
1cfe6f8c	303	goto err0;
a07e103e MD	304	}
a07e103e MD	305
1cfe6f8c MD	306	p->base0 = devm_ioremap_nocache(&pdev->dev, io[0]->start,
1cfe6f8c MD	307	resource_size(io[0]));
a07e103e MD	308	if (!p->base0) {
	309	dev_err(&pdev->dev, "failed to remap low I/O memory\n");
	310	ret = -ENXIO;
1cfe6f8c	311	goto err0;
a07e103e MD	312	}
a07e103e MD	313
1cfe6f8c MD	314	p->base1 = devm_ioremap_nocache(&pdev->dev, io[1]->start,
1cfe6f8c MD	315	resource_size(io[1]));
a07e103e MD	316	if (!p->base1) {
	317	dev_err(&pdev->dev, "failed to remap high I/O memory\n");
	318	ret = -ENXIO;
1cfe6f8c	319	goto err0;
a07e103e MD	320	}
a07e103e MD	321
753c5983 MD	322	if (!pdata) {
	323	memset(&pdata_dt, 0, sizeof(pdata_dt));
	324	pdata = &pdata_dt;
	325
	326	if (of_property_read_u32(pdev->dev.of_node, "ngpios",
	327	&pdata->number_of_pins)) {
	328	dev_err(&pdev->dev, "Missing ngpios OF property\n");
	329	ret = -EINVAL;
1cfe6f8c	330	goto err0;
753c5983 MD	331	}
	332
	333	ret = of_alias_get_id(pdev->dev.of_node, "gpio");
	334	if (ret < 0) {
	335	dev_err(&pdev->dev, "Couldn't get OF id\n");
1cfe6f8c	336	goto err0;
753c5983 MD	337	}
	338	pdata->gpio_base = ret * 32; /* 32 GPIOs per instance */
	339	}
	340
a07e103e	341	gpio_chip = &p->gpio_chip;
b5927854	342	gpio_chip->of_node = pdev->dev.of_node;
a07e103e MD	343	gpio_chip->direction_input = em_gio_direction_input;
	344	gpio_chip->get = em_gio_get;
	345	gpio_chip->direction_output = em_gio_direction_output;
	346	gpio_chip->set = em_gio_set;
	347	gpio_chip->to_irq = em_gio_to_irq;
640efa08 MD	348	gpio_chip->request = em_gio_request;
640efa08 MD	349	gpio_chip->free = em_gio_free;
a07e103e	350	gpio_chip->label = name;
969bf7ae	351	gpio_chip->dev = &pdev->dev;
a07e103e MD	352	gpio_chip->owner = THIS_MODULE;
	353	gpio_chip->base = pdata->gpio_base;
	354	gpio_chip->ngpio = pdata->number_of_pins;
	355
	356	irq_chip = &p->irq_chip;
	357	irq_chip->name = name;
	358	irq_chip->irq_mask = em_gio_irq_disable;
	359	irq_chip->irq_unmask = em_gio_irq_enable;
a07e103e	360	irq_chip->irq_set_type = em_gio_irq_set_type;
57ef0428 LW	361	irq_chip->irq_request_resources = em_gio_irq_reqres;
57ef0428 LW	362	irq_chip->irq_release_resources = em_gio_irq_relres;
03621b60	363	irq_chip->flags = IRQCHIP_SKIP_SET_WAKE \| IRQCHIP_MASK_ON_SUSPEND;
a07e103e	364
c7886b18	365	p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
7385500a	366	pdata->number_of_pins,
c7886b18	367	pdata->irq_base,
7385500a	368	&em_gio_irq_domain_ops, p);
16310819 AL	369	if (!p->irq_domain) {
16310819 AL	370	ret = -ENXIO;
a07e103e	371	dev_err(&pdev->dev, "cannot initialize irq domain\n");
1cfe6f8c	372	goto err0;
a07e103e MD	373	}
a07e103e MD	374
1cfe6f8c MD	375	if (devm_request_irq(&pdev->dev, irq[0]->start,
1cfe6f8c MD	376	em_gio_irq_handler, 0, name, p)) {
a07e103e MD	377	dev_err(&pdev->dev, "failed to request low IRQ\n");
a07e103e MD	378	ret = -ENOENT;
1cfe6f8c	379	goto err1;
a07e103e MD	380	}
a07e103e MD	381
1cfe6f8c MD	382	if (devm_request_irq(&pdev->dev, irq[1]->start,
1cfe6f8c MD	383	em_gio_irq_handler, 0, name, p)) {
a07e103e MD	384	dev_err(&pdev->dev, "failed to request high IRQ\n");
a07e103e MD	385	ret = -ENOENT;
1cfe6f8c	386	goto err1;
a07e103e MD	387	}
	388
	389	ret = gpiochip_add(gpio_chip);
	390	if (ret) {
	391	dev_err(&pdev->dev, "failed to add GPIO controller\n");
1cfe6f8c	392	goto err1;
a07e103e	393	}
640efa08 MD	394
	395	if (pdata->pctl_name) {
	396	ret = gpiochip_add_pin_range(gpio_chip, pdata->pctl_name, 0,
	397	gpio_chip->base, gpio_chip->ngpio);
	398	if (ret < 0)
	399	dev_warn(&pdev->dev, "failed to add pin range\n");
	400	}
a07e103e MD	401	return 0;
a07e103e MD	402
a07e103e	403	err1:
1cfe6f8c	404	irq_domain_remove(p->irq_domain);
a07e103e MD	405	err0:
	406	return ret;
	407	}
	408
206210ce	409	static int em_gio_remove(struct platform_device *pdev)
a07e103e MD	410	{
a07e103e MD	411	struct em_gio_priv *p = platform_get_drvdata(pdev);
a07e103e MD	412	int ret;
	413
	414	ret = gpiochip_remove(&p->gpio_chip);
	415	if (ret)
	416	return ret;
	417
16310819	418	irq_domain_remove(p->irq_domain);
a07e103e MD	419	return 0;
	420	}
	421
753c5983 MD	422	static const struct of_device_id em_gio_dt_ids[] = {
	423	{ .compatible = "renesas,em-gio", },
	424	{},
	425	};
	426	MODULE_DEVICE_TABLE(of, em_gio_dt_ids);
	427
a07e103e MD	428	static struct platform_driver em_gio_device_driver = {
a07e103e MD	429	.probe = em_gio_probe,
8283c4ff	430	.remove = em_gio_remove,
a07e103e MD	431	.driver = {
a07e103e MD	432	.name = "em_gio",
753c5983 MD	433	.of_match_table = em_gio_dt_ids,
753c5983 MD	434	.owner = THIS_MODULE,
a07e103e MD	435	}
	436	};
	437
753c5983 MD	438	static int __init em_gio_init(void)
	439	{
	440	return platform_driver_register(&em_gio_device_driver);
	441	}
	442	postcore_initcall(em_gio_init);
	443
	444	static void __exit em_gio_exit(void)
	445	{
	446	platform_driver_unregister(&em_gio_device_driver);
	447	}
	448	module_exit(em_gio_exit);
a07e103e MD	449
	450	MODULE_AUTHOR("Magnus Damm");
	451	MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
	452	MODULE_LICENSE("GPL v2");