[linux-block.git] / drivers / gpio / gpio-em.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Emma Mobile GPIO Support - GIO
 *
 *  Copyright (C) 2012 Magnus Damm
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pinctrl/consumer.h>

struct em_gio_priv {
	void __iomem *base0;
	void __iomem *base1;
	spinlock_t sense_lock;
	struct platform_device *pdev;
	struct gpio_chip gpio_chip;
	struct irq_chip irq_chip;
	struct irq_domain *irq_domain;
};

#define GIO_E1 0x00
#define GIO_E0 0x04
#define GIO_EM 0x04
#define GIO_OL 0x08
#define GIO_OH 0x0c
#define GIO_I 0x10
#define GIO_IIA 0x14
#define GIO_IEN 0x18
#define GIO_IDS 0x1c
#define GIO_IIM 0x1c
#define GIO_RAW 0x20
#define GIO_MST 0x24
#define GIO_IIR 0x28

#define GIO_IDT0 0x40
#define GIO_IDT1 0x44
#define GIO_IDT2 0x48
#define GIO_IDT3 0x4c
#define GIO_RAWBL 0x50
#define GIO_RAWBH 0x54
#define GIO_IRBL 0x58
#define GIO_IRBH 0x5c

#define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))

static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
{
	if (offs < GIO_IDT0)
		return ioread32(p->base0 + offs);
	else
		return ioread32(p->base1 + (offs - GIO_IDT0));
}

static inline void em_gio_write(struct em_gio_priv *p, int offs,
				unsigned long value)
{
	if (offs < GIO_IDT0)
		iowrite32(value, p->base0 + offs);
	else
		iowrite32(value, p->base1 + (offs - GIO_IDT0));
}

static void em_gio_irq_disable(struct irq_data *d)
{
	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);

	em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
}

static void em_gio_irq_enable(struct irq_data *d)
{
	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);

	em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
}

static int em_gio_irq_reqres(struct irq_data *d)
{
	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
	int ret;

	ret = gpiochip_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
	if (ret) {
		dev_err(p->gpio_chip.parent,
			"unable to lock HW IRQ %lu for IRQ\n",
			irqd_to_hwirq(d));
		return ret;
	}
	return 0;
}

static void em_gio_irq_relres(struct irq_data *d)
{
	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);

	gpiochip_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
}


#define GIO_ASYNC(x) (x + 8)

static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
	[IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
	[IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
	[IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
	[IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
	[IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
};

static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
{
	unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
	unsigned int reg, offset, shift;
	unsigned long flags;
	unsigned long tmp;

	if (!value)
		return -EINVAL;

	offset = irqd_to_hwirq(d);

	pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);

	/* 8 x 4 bit fields in 4 IDT registers */
	reg = GIO_IDT(offset >> 3);
	shift = (offset & 0x07) << 4;

	spin_lock_irqsave(&p->sense_lock, flags);

	/* disable the interrupt in IIA */
	tmp = em_gio_read(p, GIO_IIA);
	tmp &= ~BIT(offset);
	em_gio_write(p, GIO_IIA, tmp);

	/* change the sense setting in IDT */
	tmp = em_gio_read(p, reg);
	tmp &= ~(0xf << shift);
	tmp |= value << shift;
	em_gio_write(p, reg, tmp);

	/* clear pending interrupts */
	em_gio_write(p, GIO_IIR, BIT(offset));

	/* enable the interrupt in IIA */
	tmp = em_gio_read(p, GIO_IIA);
	tmp |= BIT(offset);
	em_gio_write(p, GIO_IIA, tmp);

	spin_unlock_irqrestore(&p->sense_lock, flags);

	return 0;
}

static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
{
	struct em_gio_priv *p = dev_id;
	unsigned long pending;
	unsigned int offset, irqs_handled = 0;

	while ((pending = em_gio_read(p, GIO_MST))) {
		offset = __ffs(pending);
		em_gio_write(p, GIO_IIR, BIT(offset));
		generic_handle_domain_irq(p->irq_domain, offset);
		irqs_handled++;
	}

	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
}

static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
{
	return gpiochip_get_data(chip);
}

static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
	return 0;
}

static int em_gio_get(struct gpio_chip *chip, unsigned offset)
{
	return !!(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
}

static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
			 unsigned shift, int value)
{
	/* upper 16 bits contains mask and lower 16 actual value */
	em_gio_write(gpio_to_priv(chip), reg,
		     (BIT(shift + 16)) | (value << shift));
}

static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	/* output is split into two registers */
	if (offset < 16)
		__em_gio_set(chip, GIO_OL, offset, value);
	else
		__em_gio_set(chip, GIO_OH, offset - 16, value);
}

static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
				   int value)
{
	/* write GPIO value to output before selecting output mode of pin */
	em_gio_set(chip, offset, value);
	em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
	return 0;
}

static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
}

static void em_gio_free(struct gpio_chip *chip, unsigned offset)
{
	pinctrl_gpio_free(chip, offset);

	/* Set the GPIO as an input to ensure that the next GPIO request won't
	* drive the GPIO pin as an output.
	*/
	em_gio_direction_input(chip, offset);
}

static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq,
				 irq_hw_number_t hwirq)
{
	struct em_gio_priv *p = h->host_data;

	pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq);

	irq_set_chip_data(irq, h->host_data);
	irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
	return 0;
}

static const struct irq_domain_ops em_gio_irq_domain_ops = {
	.map	= em_gio_irq_domain_map,
	.xlate	= irq_domain_xlate_twocell,
};

static void em_gio_irq_domain_remove(void *data)
{
	struct irq_domain *domain = data;

	irq_domain_remove(domain);
}

static int em_gio_probe(struct platform_device *pdev)
{
	struct em_gio_priv *p;
	struct gpio_chip *gpio_chip;
	struct irq_chip *irq_chip;
	struct device *dev = &pdev->dev;
	const char *name = dev_name(dev);
	unsigned int ngpios;
	int irq[2], ret;

	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
	if (!p)
		return -ENOMEM;

	p->pdev = pdev;
	platform_set_drvdata(pdev, p);
	spin_lock_init(&p->sense_lock);

	irq[0] = platform_get_irq(pdev, 0);
	if (irq[0] < 0)
		return irq[0];

	irq[1] = platform_get_irq(pdev, 1);
	if (irq[1] < 0)
		return irq[1];

	p->base0 = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(p->base0))
		return PTR_ERR(p->base0);

	p->base1 = devm_platform_ioremap_resource(pdev, 1);
	if (IS_ERR(p->base1))
		return PTR_ERR(p->base1);

	if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
		dev_err(dev, "Missing ngpios OF property\n");
		return -EINVAL;
	}

	gpio_chip = &p->gpio_chip;
	gpio_chip->direction_input = em_gio_direction_input;
	gpio_chip->get = em_gio_get;
	gpio_chip->direction_output = em_gio_direction_output;
	gpio_chip->set = em_gio_set;
	gpio_chip->to_irq = em_gio_to_irq;
	gpio_chip->request = pinctrl_gpio_request;
	gpio_chip->free = em_gio_free;
	gpio_chip->label = name;
	gpio_chip->parent = dev;
	gpio_chip->owner = THIS_MODULE;
	gpio_chip->base = -1;
	gpio_chip->ngpio = ngpios;

	irq_chip = &p->irq_chip;
	irq_chip->name = "gpio-em";
	irq_chip->irq_mask = em_gio_irq_disable;
	irq_chip->irq_unmask = em_gio_irq_enable;
	irq_chip->irq_set_type = em_gio_irq_set_type;
	irq_chip->irq_request_resources = em_gio_irq_reqres;
	irq_chip->irq_release_resources = em_gio_irq_relres;
	irq_chip->flags	= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;

	p->irq_domain = irq_domain_add_simple(dev->of_node, ngpios, 0,
					      &em_gio_irq_domain_ops, p);
	if (!p->irq_domain) {
		dev_err(dev, "cannot initialize irq domain\n");
		return -ENXIO;
	}

	ret = devm_add_action_or_reset(dev, em_gio_irq_domain_remove,
				       p->irq_domain);
	if (ret)
		return ret;

	if (devm_request_irq(dev, irq[0], em_gio_irq_handler, 0, name, p)) {
		dev_err(dev, "failed to request low IRQ\n");
		return -ENOENT;
	}

	if (devm_request_irq(dev, irq[1], em_gio_irq_handler, 0, name, p)) {
		dev_err(dev, "failed to request high IRQ\n");
		return -ENOENT;
	}

	ret = devm_gpiochip_add_data(dev, gpio_chip, p);
	if (ret) {
		dev_err(dev, "failed to add GPIO controller\n");
		return ret;
	}

	return 0;
}

static const struct of_device_id em_gio_dt_ids[] = {
	{ .compatible = "renesas,em-gio", },
	{},
};
MODULE_DEVICE_TABLE(of, em_gio_dt_ids);

static struct platform_driver em_gio_device_driver = {
	.probe		= em_gio_probe,
	.driver		= {
		.name	= "em_gio",
		.of_match_table = em_gio_dt_ids,
	}
};

static int __init em_gio_init(void)
{
	return platform_driver_register(&em_gio_device_driver);
}
postcore_initcall(em_gio_init);

static void __exit em_gio_exit(void)
{
	platform_driver_unregister(&em_gio_device_driver);
}
module_exit(em_gio_exit);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
0b712183	1	// SPDX-License-Identifier: GPL-2.0-only
a07e103e MD	2	/*
	3	* Emma Mobile GPIO Support - GIO
	4	*
	5	* Copyright (C) 2012 Magnus Damm
a07e103e MD	6	*/
	7
	8	#include <linux/init.h>
	9	#include <linux/platform_device.h>
	10	#include <linux/spinlock.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/ioport.h>
	13	#include <linux/io.h>
	14	#include <linux/irq.h>
	15	#include <linux/irqdomain.h>
	16	#include <linux/bitops.h>
	17	#include <linux/err.h>
7275cb75	18	#include <linux/gpio/driver.h>
a07e103e MD	19	#include <linux/slab.h>
a07e103e MD	20	#include <linux/module.h>
640efa08	21	#include <linux/pinctrl/consumer.h>
a07e103e MD	22
	23	struct em_gio_priv {
	24	void __iomem *base0;
	25	void __iomem *base1;
a07e103e MD	26	spinlock_t sense_lock;
	27	struct platform_device *pdev;
	28	struct gpio_chip gpio_chip;
	29	struct irq_chip irq_chip;
	30	struct irq_domain *irq_domain;
	31	};
	32
	33	#define GIO_E1 0x00
	34	#define GIO_E0 0x04
	35	#define GIO_EM 0x04
	36	#define GIO_OL 0x08
	37	#define GIO_OH 0x0c
	38	#define GIO_I 0x10
	39	#define GIO_IIA 0x14
	40	#define GIO_IEN 0x18
	41	#define GIO_IDS 0x1c
	42	#define GIO_IIM 0x1c
	43	#define GIO_RAW 0x20
	44	#define GIO_MST 0x24
	45	#define GIO_IIR 0x28
	46
	47	#define GIO_IDT0 0x40
	48	#define GIO_IDT1 0x44
	49	#define GIO_IDT2 0x48
	50	#define GIO_IDT3 0x4c
	51	#define GIO_RAWBL 0x50
	52	#define GIO_RAWBH 0x54
	53	#define GIO_IRBL 0x58
	54	#define GIO_IRBH 0x5c
	55
	56	#define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
	57
	58	static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
	59	{
	60	if (offs < GIO_IDT0)
	61	return ioread32(p->base0 + offs);
	62	else
	63	return ioread32(p->base1 + (offs - GIO_IDT0));
	64	}
	65
	66	static inline void em_gio_write(struct em_gio_priv *p, int offs,
	67	unsigned long value)
	68	{
	69	if (offs < GIO_IDT0)
	70	iowrite32(value, p->base0 + offs);
	71	else
	72	iowrite32(value, p->base1 + (offs - GIO_IDT0));
	73	}
	74
a07e103e MD	75	static void em_gio_irq_disable(struct irq_data *d)
a07e103e MD	76	{
a9f77c93	77	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
a07e103e MD	78
	79	em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
	80	}
	81
	82	static void em_gio_irq_enable(struct irq_data *d)
	83	{
a9f77c93	84	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
a07e103e MD	85
	86	em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
	87	}
	88
57ef0428	89	static int em_gio_irq_reqres(struct irq_data *d)
0dc61623 LW	90	{
0dc61623 LW	91	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
41d69087	92	int ret;
0dc61623	93
41d69087 AS	94	ret = gpiochip_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
41d69087 AS	95	if (ret) {
58383c78	96	dev_err(p->gpio_chip.parent,
0dc61623 LW	97	"unable to lock HW IRQ %lu for IRQ\n",
0dc61623 LW	98	irqd_to_hwirq(d));
41d69087	99	return ret;
57ef0428	100	}
0dc61623 LW	101	return 0;
	102	}
	103
57ef0428	104	static void em_gio_irq_relres(struct irq_data *d)
0dc61623 LW	105	{
	106	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
	107
e3a2e878	108	gpiochip_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
0dc61623 LW	109	}
	110
	111
a07e103e MD	112	#define GIO_ASYNC(x) (x + 8)
	113
	114	static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
	115	[IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
	116	[IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
	117	[IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
	118	[IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
	119	[IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
	120	};
	121
	122	static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
	123	{
	124	unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
a9f77c93	125	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
a07e103e MD	126	unsigned int reg, offset, shift;
	127	unsigned long flags;
	128	unsigned long tmp;
	129
	130	if (!value)
	131	return -EINVAL;
	132
	133	offset = irqd_to_hwirq(d);
	134
	135	pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
	136
	137	/* 8 x 4 bit fields in 4 IDT registers */
	138	reg = GIO_IDT(offset >> 3);
	139	shift = (offset & 0x07) << 4;
	140
	141	spin_lock_irqsave(&p->sense_lock, flags);
	142
	143	/* disable the interrupt in IIA */
	144	tmp = em_gio_read(p, GIO_IIA);
	145	tmp &= ~BIT(offset);
	146	em_gio_write(p, GIO_IIA, tmp);
	147
	148	/* change the sense setting in IDT */
	149	tmp = em_gio_read(p, reg);
	150	tmp &= ~(0xf << shift);
	151	tmp \|= value << shift;
	152	em_gio_write(p, reg, tmp);
	153
	154	/* clear pending interrupts */
	155	em_gio_write(p, GIO_IIR, BIT(offset));
	156
	157	/* enable the interrupt in IIA */
	158	tmp = em_gio_read(p, GIO_IIA);
	159	tmp \|= BIT(offset);
	160	em_gio_write(p, GIO_IIA, tmp);
	161
	162	spin_unlock_irqrestore(&p->sense_lock, flags);
	163
	164	return 0;
	165	}
	166
	167	static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
	168	{
	169	struct em_gio_priv *p = dev_id;
	170	unsigned long pending;
	171	unsigned int offset, irqs_handled = 0;
	172
	173	while ((pending = em_gio_read(p, GIO_MST))) {
	174	offset = __ffs(pending);
	175	em_gio_write(p, GIO_IIR, BIT(offset));
dbd1c54f	176	generic_handle_domain_irq(p->irq_domain, offset);
a07e103e MD	177	irqs_handled++;
	178	}
	179
	180	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
	181	}
	182
	183	static inline struct em_gio_priv gpio_to_priv(struct gpio_chip chip)
	184	{
6219e7bb	185	return gpiochip_get_data(chip);
a07e103e MD	186	}
	187
	188	static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
	189	{
	190	em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
	191	return 0;
	192	}
	193
	194	static int em_gio_get(struct gpio_chip *chip, unsigned offset)
	195	{
8388f290	196	return !!(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
a07e103e MD	197	}
	198
	199	static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
	200	unsigned shift, int value)
	201	{
	202	/* upper 16 bits contains mask and lower 16 actual value */
	203	em_gio_write(gpio_to_priv(chip), reg,
5f077644	204	(BIT(shift + 16)) \| (value << shift));
a07e103e MD	205	}
	206
	207	static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
	208	{
	209	/* output is split into two registers */
	210	if (offset < 16)
	211	__em_gio_set(chip, GIO_OL, offset, value);
	212	else
	213	__em_gio_set(chip, GIO_OH, offset - 16, value);
	214	}
	215
	216	static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
	217	int value)
	218	{
	219	/* write GPIO value to output before selecting output mode of pin */
	220	em_gio_set(chip, offset, value);
	221	em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
	222	return 0;
	223	}
	224
	225	static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
	226	{
7385500a	227	return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
a07e103e MD	228	}
a07e103e MD	229
640efa08 MD	230	static void em_gio_free(struct gpio_chip *chip, unsigned offset)
640efa08 MD	231	{
4fccb263	232	pinctrl_gpio_free(chip, offset);
640efa08 MD	233
	234	/* Set the GPIO as an input to ensure that the next GPIO request won't
	235	* drive the GPIO pin as an output.
	236	*/
	237	em_gio_direction_input(chip, offset);
	238	}
	239
2d61e3e9 LW	240	static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq,
2d61e3e9 LW	241	irq_hw_number_t hwirq)
a07e103e MD	242	{
	243	struct em_gio_priv *p = h->host_data;
	244
2d61e3e9	245	pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq);
a07e103e	246
2d61e3e9 LW	247	irq_set_chip_data(irq, h->host_data);
2d61e3e9 LW	248	irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
a07e103e MD	249	return 0;
	250	}
	251
0b354dc4	252	static const struct irq_domain_ops em_gio_irq_domain_ops = {
a07e103e	253	.map = em_gio_irq_domain_map,
753c5983	254	.xlate = irq_domain_xlate_twocell,
a07e103e MD	255	};
a07e103e MD	256
19ec11a2 BG	257	static void em_gio_irq_domain_remove(void *data)
	258	{
	259	struct irq_domain *domain = data;
	260
	261	irq_domain_remove(domain);
	262	}
	263
3836309d	264	static int em_gio_probe(struct platform_device *pdev)
a07e103e	265	{
a07e103e	266	struct em_gio_priv *p;
a07e103e MD	267	struct gpio_chip *gpio_chip;
a07e103e MD	268	struct irq_chip *irq_chip;
66ad6629 BG	269	struct device *dev = &pdev->dev;
66ad6629 BG	270	const char *name = dev_name(dev);
527b397a	271	unsigned int ngpios;
be053b2d	272	int irq[2], ret;
a07e103e	273
66ad6629	274	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
715ed728 GU	275	if (!p)
715ed728 GU	276	return -ENOMEM;
a07e103e MD	277
	278	p->pdev = pdev;
	279	platform_set_drvdata(pdev, p);
	280	spin_lock_init(&p->sense_lock);
	281
be053b2d GU	282	irq[0] = platform_get_irq(pdev, 0);
	283	if (irq[0] < 0)
	284	return irq[0];
a07e103e	285
be053b2d GU	286	irq[1] = platform_get_irq(pdev, 1);
	287	if (irq[1] < 0)
	288	return irq[1];
a07e103e	289
94bfcbf0 BG	290	p->base0 = devm_platform_ioremap_resource(pdev, 0);
	291	if (IS_ERR(p->base0))
	292	return PTR_ERR(p->base0);
a07e103e	293
94bfcbf0 BG	294	p->base1 = devm_platform_ioremap_resource(pdev, 1);
	295	if (IS_ERR(p->base1))
	296	return PTR_ERR(p->base1);
a07e103e	297
66ad6629 BG	298	if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
66ad6629 BG	299	dev_err(dev, "Missing ngpios OF property\n");
715ed728	300	return -EINVAL;
753c5983 MD	301	}
753c5983 MD	302
a07e103e MD	303	gpio_chip = &p->gpio_chip;
	304	gpio_chip->direction_input = em_gio_direction_input;
	305	gpio_chip->get = em_gio_get;
	306	gpio_chip->direction_output = em_gio_direction_output;
	307	gpio_chip->set = em_gio_set;
	308	gpio_chip->to_irq = em_gio_to_irq;
8e1df2f5	309	gpio_chip->request = pinctrl_gpio_request;
640efa08	310	gpio_chip->free = em_gio_free;
a07e103e	311	gpio_chip->label = name;
66ad6629	312	gpio_chip->parent = dev;
a07e103e	313	gpio_chip->owner = THIS_MODULE;
527b397a GU	314	gpio_chip->base = -1;
527b397a GU	315	gpio_chip->ngpio = ngpios;
a07e103e MD	316
a07e103e MD	317	irq_chip = &p->irq_chip;
b74f0456	318	irq_chip->name = "gpio-em";
a07e103e MD	319	irq_chip->irq_mask = em_gio_irq_disable;
a07e103e MD	320	irq_chip->irq_unmask = em_gio_irq_enable;
a07e103e	321	irq_chip->irq_set_type = em_gio_irq_set_type;
57ef0428 LW	322	irq_chip->irq_request_resources = em_gio_irq_reqres;
57ef0428 LW	323	irq_chip->irq_release_resources = em_gio_irq_relres;
03621b60	324	irq_chip->flags = IRQCHIP_SKIP_SET_WAKE \| IRQCHIP_MASK_ON_SUSPEND;
a07e103e	325
66ad6629	326	p->irq_domain = irq_domain_add_simple(dev->of_node, ngpios, 0,
7385500a	327	&em_gio_irq_domain_ops, p);
16310819	328	if (!p->irq_domain) {
66ad6629	329	dev_err(dev, "cannot initialize irq domain\n");
715ed728	330	return -ENXIO;
a07e103e MD	331	}
a07e103e MD	332
66ad6629	333	ret = devm_add_action_or_reset(dev, em_gio_irq_domain_remove,
19ec11a2 BG	334	p->irq_domain);
	335	if (ret)
	336	return ret;
	337
be053b2d	338	if (devm_request_irq(dev, irq[0], em_gio_irq_handler, 0, name, p)) {
66ad6629	339	dev_err(dev, "failed to request low IRQ\n");
19ec11a2	340	return -ENOENT;
a07e103e MD	341	}
a07e103e MD	342
be053b2d	343	if (devm_request_irq(dev, irq[1], em_gio_irq_handler, 0, name, p)) {
66ad6629	344	dev_err(dev, "failed to request high IRQ\n");
19ec11a2	345	return -ENOENT;
a07e103e MD	346	}
a07e103e MD	347
66ad6629	348	ret = devm_gpiochip_add_data(dev, gpio_chip, p);
a07e103e	349	if (ret) {
66ad6629	350	dev_err(dev, "failed to add GPIO controller\n");
19ec11a2	351	return ret;
a07e103e	352	}
640efa08	353
a07e103e	354	return 0;
a07e103e MD	355	}
a07e103e MD	356
753c5983 MD	357	static const struct of_device_id em_gio_dt_ids[] = {
	358	{ .compatible = "renesas,em-gio", },
	359	{},
	360	};
	361	MODULE_DEVICE_TABLE(of, em_gio_dt_ids);
	362
a07e103e MD	363	static struct platform_driver em_gio_device_driver = {
a07e103e MD	364	.probe = em_gio_probe,
a07e103e MD	365	.driver = {
a07e103e MD	366	.name = "em_gio",
753c5983	367	.of_match_table = em_gio_dt_ids,
a07e103e MD	368	}
	369	};
	370
753c5983 MD	371	static int __init em_gio_init(void)
	372	{
	373	return platform_driver_register(&em_gio_device_driver);
	374	}
	375	postcore_initcall(em_gio_init);
	376
	377	static void __exit em_gio_exit(void)
	378	{
	379	platform_driver_unregister(&em_gio_device_driver);
	380	}
	381	module_exit(em_gio_exit);
a07e103e MD	382
	383	MODULE_AUTHOR("Magnus Damm");
	384	MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
	385	MODULE_LICENSE("GPL v2");