projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'landlock-6.8-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/mic...
[linux-block.git] / drivers / gpio / gpio-eic-sprd.c
CommitLineData
25518e02
BW		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Spreadtrum Communications Inc.
4 * Copyright (C) 2018 Linaro Ltd.
5 */
6
7#include <linux/bitops.h>
8#include <linux/gpio/driver.h>
9#include <linux/interrupt.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
b3241565 12#include <linux/notifier.h>
e91d0f05 13#include <linux/of.h>
25518e02
BW		 14#include <linux/platform_device.h>
15#include <linux/spinlock.h>
16
17/* EIC registers definition */
18#define SPRD_EIC_DBNC_DATA 0x0
19#define SPRD_EIC_DBNC_DMSK 0x4
20#define SPRD_EIC_DBNC_IEV 0x14
21#define SPRD_EIC_DBNC_IE 0x18
22#define SPRD_EIC_DBNC_RIS 0x1c
23#define SPRD_EIC_DBNC_MIS 0x20
24#define SPRD_EIC_DBNC_IC 0x24
25#define SPRD_EIC_DBNC_TRIG 0x28
26#define SPRD_EIC_DBNC_CTRL0 0x40
27
28#define SPRD_EIC_LATCH_INTEN 0x0
29#define SPRD_EIC_LATCH_INTRAW 0x4
30#define SPRD_EIC_LATCH_INTMSK 0x8
31#define SPRD_EIC_LATCH_INTCLR 0xc
32#define SPRD_EIC_LATCH_INTPOL 0x10
33#define SPRD_EIC_LATCH_INTMODE 0x14
34
35#define SPRD_EIC_ASYNC_INTIE 0x0
36#define SPRD_EIC_ASYNC_INTRAW 0x4
37#define SPRD_EIC_ASYNC_INTMSK 0x8
38#define SPRD_EIC_ASYNC_INTCLR 0xc
39#define SPRD_EIC_ASYNC_INTMODE 0x10
40#define SPRD_EIC_ASYNC_INTBOTH 0x14
41#define SPRD_EIC_ASYNC_INTPOL 0x18
42#define SPRD_EIC_ASYNC_DATA 0x1c
43
44#define SPRD_EIC_SYNC_INTIE 0x0
45#define SPRD_EIC_SYNC_INTRAW 0x4
46#define SPRD_EIC_SYNC_INTMSK 0x8
47#define SPRD_EIC_SYNC_INTCLR 0xc
48#define SPRD_EIC_SYNC_INTMODE 0x10
49#define SPRD_EIC_SYNC_INTBOTH 0x14
50#define SPRD_EIC_SYNC_INTPOL 0x18
51#define SPRD_EIC_SYNC_DATA 0x1c
52
53/*
54 * The digital-chip EIC controller can support maximum 3 banks, and each bank
55 * contains 8 EICs.
56 */
57#define SPRD_EIC_MAX_BANK 3
58#define SPRD_EIC_PER_BANK_NR 8
59#define SPRD_EIC_DATA_MASK GENMASK(7, 0)
60#define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
61#define SPRD_EIC_DBNC_MASK GENMASK(11, 0)
62
63/*
64 * The Spreadtrum EIC (external interrupt controller) can be used only in
65 * input mode to generate interrupts if detecting input signals.
66 *
67 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
68 * debounce EIC, latch EIC, async EIC and sync EIC,
69 *
70 * The debounce EIC is used to capture the input signals' stable status
71 * (millisecond resolution) and a single-trigger mechanism is introduced
72 * into this sub-module to enhance the input event detection reliability.
73 * The debounce range is from 1ms to 4s with a step size of 1ms.
74 *
75 * The latch EIC is used to latch some special power down signals and
76 * generate interrupts, since the latch EIC does not depend on the APB clock
77 * to capture signals.
78 *
79 * The async EIC uses a 32k clock to capture the short signals (microsecond
80 * resolution) to generate interrupts by level or edge trigger.
81 *
82 * The EIC-sync is similar with GPIO's input function, which is a synchronized
83 * signal input register.
84 */
85enum sprd_eic_type {
86 SPRD_EIC_DEBOUNCE,
87 SPRD_EIC_LATCH,
88 SPRD_EIC_ASYNC,
89 SPRD_EIC_SYNC,
90 SPRD_EIC_MAX,
91};
92
93struct sprd_eic {
94 struct gpio_chip chip;
b3241565 95 struct notifier_block irq_nb;
25518e02
BW		 96 void __iomem *base[SPRD_EIC_MAX_BANK];
97 enum sprd_eic_type type;
98 spinlock_t lock;
99 int irq;
100};
101
b3241565
BG		 102static ATOMIC_NOTIFIER_HEAD(sprd_eic_irq_notifier);
103
104static struct sprd_eic *to_sprd_eic(struct notifier_block *nb)
105{
106 return container_of(nb, struct sprd_eic, irq_nb);
107}
108
25518e02
BW		 109struct sprd_eic_variant_data {
110 enum sprd_eic_type type;
111 u32 num_eics;
112};
113
114static const char *sprd_eic_label_name[SPRD_EIC_MAX] = {
115 "eic-debounce", "eic-latch", "eic-async",
116 "eic-sync",
117};
118
119static const struct sprd_eic_variant_data sc9860_eic_dbnc_data = {
120 .type = SPRD_EIC_DEBOUNCE,
121 .num_eics = 8,
122};
123
124static const struct sprd_eic_variant_data sc9860_eic_latch_data = {
125 .type = SPRD_EIC_LATCH,
126 .num_eics = 8,
127};
128
129static const struct sprd_eic_variant_data sc9860_eic_async_data = {
130 .type = SPRD_EIC_ASYNC,
131 .num_eics = 8,
132};
133
134static const struct sprd_eic_variant_data sc9860_eic_sync_data = {
135 .type = SPRD_EIC_SYNC,
136 .num_eics = 8,
137};
138
139static inline void __iomem *sprd_eic_offset_base(struct sprd_eic *sprd_eic,
140 unsigned int bank)
141{
142 if (bank >= SPRD_EIC_MAX_BANK)
143 return NULL;
144
145 return sprd_eic->base[bank];
146}
147
148static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset,
149 u16 reg, unsigned int val)
150{
151 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
152 void __iomem *base =
153 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
154 unsigned long flags;
155 u32 tmp;
156
157 spin_lock_irqsave(&sprd_eic->lock, flags);
158 tmp = readl_relaxed(base + reg);
159
160 if (val)
161 tmp |= BIT(SPRD_EIC_BIT(offset));
162 else
163 tmp &= ~BIT(SPRD_EIC_BIT(offset));
164
165 writel_relaxed(tmp, base + reg);
166 spin_unlock_irqrestore(&sprd_eic->lock, flags);
167}
168
169static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
170{
171 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
172 void __iomem *base =
173 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
174
175 return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset)));
176}
177
178static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset)
179{
180 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1);
181 return 0;
182}
183
184static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset)
185{
186 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0);
187}
188
189static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset)
190{
09d158d5
NH		 191 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
192
193 switch (sprd_eic->type) {
194 case SPRD_EIC_DEBOUNCE:
195 return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA);
196 case SPRD_EIC_ASYNC:
197 return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA);
198 case SPRD_EIC_SYNC:
199 return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA);
200 default:
201 return -ENOTSUPP;
202 }
25518e02
BW		 203}
204
205static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset)
206{
207 /* EICs are always input, nothing need to do here. */
208 return 0;
209}
210
211static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value)
212{
213 /* EICs are always input, nothing need to do here. */
214}
215
216static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset,
217 unsigned int debounce)
218{
219 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
220 void __iomem *base =
221 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
222 u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4;
223 u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK;
224
225 value |= (debounce / 1000) & SPRD_EIC_DBNC_MASK;
226 writel_relaxed(value, base + reg);
227
228 return 0;
229}
230
231static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset,
232 unsigned long config)
233{
234 unsigned long param = pinconf_to_config_param(config);
235 u32 arg = pinconf_to_config_argument(config);
236
237 if (param == PIN_CONFIG_INPUT_DEBOUNCE)
238 return sprd_eic_set_debounce(chip, offset, arg);
239
240 return -ENOTSUPP;
241}
242
243static void sprd_eic_irq_mask(struct irq_data *data)
244{
245 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
246 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
247 u32 offset = irqd_to_hwirq(data);
248
249 switch (sprd_eic->type) {
250 case SPRD_EIC_DEBOUNCE:
251 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0);
252 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0);
253 break;
254 case SPRD_EIC_LATCH:
255 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0);
256 break;
257 case SPRD_EIC_ASYNC:
258 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0);
259 break;
260 case SPRD_EIC_SYNC:
261 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0);
262 break;
263 default:
264 dev_err(chip->parent, "Unsupported EIC type.\n");
265 }
2788938b
CG		 266
267 gpiochip_disable_irq(chip, offset);
25518e02
BW		 268}
269
270static void sprd_eic_irq_unmask(struct irq_data *data)
271{
272 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
273 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
274 u32 offset = irqd_to_hwirq(data);
275
2788938b
CG		 276 gpiochip_enable_irq(chip, offset);
277
25518e02
BW		 278 switch (sprd_eic->type) {
279 case SPRD_EIC_DEBOUNCE:
280 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1);
281 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1);
282 break;
283 case SPRD_EIC_LATCH:
284 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1);
285 break;
286 case SPRD_EIC_ASYNC:
287 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1);
288 break;
289 case SPRD_EIC_SYNC:
290 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1);
291 break;
292 default:
293 dev_err(chip->parent, "Unsupported EIC type.\n");
294 }
295}
296
297static void sprd_eic_irq_ack(struct irq_data *data)
298{
299 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
300 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
301 u32 offset = irqd_to_hwirq(data);
302
303 switch (sprd_eic->type) {
304 case SPRD_EIC_DEBOUNCE:
305 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
306 break;
307 case SPRD_EIC_LATCH:
308 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
309 break;
310 case SPRD_EIC_ASYNC:
311 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
312 break;
313 case SPRD_EIC_SYNC:
314 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
315 break;
316 default:
317 dev_err(chip->parent, "Unsupported EIC type.\n");
318 }
319}
320
321static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
322{
323 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
324 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
325 u32 offset = irqd_to_hwirq(data);
7bf0d7f6 326 int state;
25518e02
BW		 327
328 switch (sprd_eic->type) {
329 case SPRD_EIC_DEBOUNCE:
330 switch (flow_type) {
331 case IRQ_TYPE_LEVEL_HIGH:
332 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
84aef4ed 333 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
25518e02
BW		 334 break;
335 case IRQ_TYPE_LEVEL_LOW:
336 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
84aef4ed 337 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
25518e02 338 break;
7bf0d7f6
BW		 339 case IRQ_TYPE_EDGE_RISING:
340 case IRQ_TYPE_EDGE_FALLING:
341 case IRQ_TYPE_EDGE_BOTH:
342 state = sprd_eic_get(chip, offset);
84aef4ed 343 if (state) {
7bf0d7f6
BW		 344 sprd_eic_update(chip, offset,
345 SPRD_EIC_DBNC_IEV, 0);
84aef4ed
WL		 346 sprd_eic_update(chip, offset,
347 SPRD_EIC_DBNC_IC, 1);
348 } else {
7bf0d7f6
BW		 349 sprd_eic_update(chip, offset,
350 SPRD_EIC_DBNC_IEV, 1);
84aef4ed
WL		 351 sprd_eic_update(chip, offset,
352 SPRD_EIC_DBNC_IC, 1);
353 }
7bf0d7f6 354 break;
25518e02
BW		 355 default:
356 return -ENOTSUPP;
357 }
358
359 irq_set_handler_locked(data, handle_level_irq);
360 break;
361 case SPRD_EIC_LATCH:
362 switch (flow_type) {
363 case IRQ_TYPE_LEVEL_HIGH:
364 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
84aef4ed 365 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
25518e02
BW		 366 break;
367 case IRQ_TYPE_LEVEL_LOW:
368 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
84aef4ed 369 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
25518e02 370 break;
7bf0d7f6
BW		 371 case IRQ_TYPE_EDGE_RISING:
372 case IRQ_TYPE_EDGE_FALLING:
373 case IRQ_TYPE_EDGE_BOTH:
374 state = sprd_eic_get(chip, offset);
84aef4ed 375 if (state) {
7bf0d7f6
BW		 376 sprd_eic_update(chip, offset,
377 SPRD_EIC_LATCH_INTPOL, 0);
84aef4ed
WL		 378 sprd_eic_update(chip, offset,
379 SPRD_EIC_LATCH_INTCLR, 1);
380 } else {
7bf0d7f6
BW		 381 sprd_eic_update(chip, offset,
382 SPRD_EIC_LATCH_INTPOL, 1);
84aef4ed
WL		 383 sprd_eic_update(chip, offset,
384 SPRD_EIC_LATCH_INTCLR, 1);
385 }
7bf0d7f6 386 break;
25518e02
BW		 387 default:
388 return -ENOTSUPP;
389 }
390
391 irq_set_handler_locked(data, handle_level_irq);
392 break;
393 case SPRD_EIC_ASYNC:
394 switch (flow_type) {
395 case IRQ_TYPE_EDGE_RISING:
396 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
397 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
398 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
84aef4ed 399 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
25518e02
BW		 400 irq_set_handler_locked(data, handle_edge_irq);
401 break;
402 case IRQ_TYPE_EDGE_FALLING:
403 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
404 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
405 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
84aef4ed 406 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
25518e02
BW		 407 irq_set_handler_locked(data, handle_edge_irq);
408 break;
409 case IRQ_TYPE_EDGE_BOTH:
f785ffb6 410 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
25518e02 411 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1);
84aef4ed 412 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
25518e02
BW		 413 irq_set_handler_locked(data, handle_edge_irq);
414 break;
415 case IRQ_TYPE_LEVEL_HIGH:
416 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
417 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
418 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
84aef4ed 419 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
25518e02
BW		 420 irq_set_handler_locked(data, handle_level_irq);
421 break;
422 case IRQ_TYPE_LEVEL_LOW:
423 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
424 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
425 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
84aef4ed 426 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
25518e02
BW		 427 irq_set_handler_locked(data, handle_level_irq);
428 break;
429 default:
430 return -ENOTSUPP;
431 }
432 break;
433 case SPRD_EIC_SYNC:
434 switch (flow_type) {
435 case IRQ_TYPE_EDGE_RISING:
436 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
437 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
438 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
84aef4ed 439 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
25518e02
BW		 440 irq_set_handler_locked(data, handle_edge_irq);
441 break;
442 case IRQ_TYPE_EDGE_FALLING:
443 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
444 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
445 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
84aef4ed 446 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
25518e02
BW		 447 irq_set_handler_locked(data, handle_edge_irq);
448 break;
449 case IRQ_TYPE_EDGE_BOTH:
102bbe34 450 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
25518e02 451 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1);
84aef4ed 452 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
25518e02
BW		 453 irq_set_handler_locked(data, handle_edge_irq);
454 break;
455 case IRQ_TYPE_LEVEL_HIGH:
456 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
457 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
458 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
84aef4ed 459 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
25518e02
BW		 460 irq_set_handler_locked(data, handle_level_irq);
461 break;
462 case IRQ_TYPE_LEVEL_LOW:
463 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
464 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
465 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
84aef4ed 466 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
25518e02
BW		 467 irq_set_handler_locked(data, handle_level_irq);
468 break;
469 default:
470 return -ENOTSUPP;
471 }
5340f23d 472 break;
25518e02
BW		 473 default:
474 dev_err(chip->parent, "Unsupported EIC type.\n");
475 return -ENOTSUPP;
476 }
477
478 return 0;
479}
480
7bf0d7f6
BW		 481static void sprd_eic_toggle_trigger(struct gpio_chip *chip, unsigned int irq,
482 unsigned int offset)
483{
484 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
485 struct irq_data *data = irq_get_irq_data(irq);
486 u32 trigger = irqd_get_trigger_type(data);
487 int state, post_state;
488
489 /*
490 * The debounce EIC and latch EIC can only support level trigger, so we
491 * can toggle the level trigger to emulate the edge trigger.
492 */
493 if ((sprd_eic->type != SPRD_EIC_DEBOUNCE &&
494 sprd_eic->type != SPRD_EIC_LATCH) ||
495 !(trigger & IRQ_TYPE_EDGE_BOTH))
496 return;
497
498 sprd_eic_irq_mask(data);
499 state = sprd_eic_get(chip, offset);
500
501retry:
502 switch (sprd_eic->type) {
503 case SPRD_EIC_DEBOUNCE:
504 if (state)
505 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
506 else
507 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
508 break;
509 case SPRD_EIC_LATCH:
510 if (state)
511 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
512 else
513 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
514 break;
515 default:
516 sprd_eic_irq_unmask(data);
517 return;
518 }
519
520 post_state = sprd_eic_get(chip, offset);
521 if (state != post_state) {
522 dev_warn(chip->parent, "EIC level was changed.\n");
523 state = post_state;
524 goto retry;
525 }
526
527 sprd_eic_irq_unmask(data);
528}
529
25518e02
BW		 530static void sprd_eic_handle_one_type(struct gpio_chip *chip)
531{
532 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
533 u32 bank, n, girq;
534
535 for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) {
536 void __iomem *base = sprd_eic_offset_base(sprd_eic, bank);
537 unsigned long reg;
538
539 switch (sprd_eic->type) {
540 case SPRD_EIC_DEBOUNCE:
541 reg = readl_relaxed(base + SPRD_EIC_DBNC_MIS) &
542 SPRD_EIC_DATA_MASK;
543 break;
544 case SPRD_EIC_LATCH:
545 reg = readl_relaxed(base + SPRD_EIC_LATCH_INTMSK) &
546 SPRD_EIC_DATA_MASK;
547 break;
548 case SPRD_EIC_ASYNC:
549 reg = readl_relaxed(base + SPRD_EIC_ASYNC_INTMSK) &
550 SPRD_EIC_DATA_MASK;
551 break;
552 case SPRD_EIC_SYNC:
553 reg = readl_relaxed(base + SPRD_EIC_SYNC_INTMSK) &
554 SPRD_EIC_DATA_MASK;
555 break;
556 default:
557 dev_err(chip->parent, "Unsupported EIC type.\n");
558 return;
559 }
560
561 for_each_set_bit(n, &reg, SPRD_EIC_PER_BANK_NR) {
e91aafcb
BC		 562 u32 offset = bank * SPRD_EIC_PER_BANK_NR + n;
563
564 girq = irq_find_mapping(chip->irq.domain, offset);
25518e02
BW		 565
566 generic_handle_irq(girq);
e91aafcb 567 sprd_eic_toggle_trigger(chip, girq, offset);
25518e02
BW		 568 }
569 }
570}
571
572static void sprd_eic_irq_handler(struct irq_desc *desc)
573{
574 struct irq_chip *ic = irq_desc_get_chip(desc);
25518e02
BW		 575
576 chained_irq_enter(ic, desc);
577
578 /*
579 * Since the digital-chip EIC 4 sub-modules (debounce, latch, async
b3241565
BG		 580 * and sync) share one same interrupt line, we should notify all of
581 * them to let them check if there are EIC interrupts were triggered.
25518e02 582 */
b3241565 583 atomic_notifier_call_chain(&sprd_eic_irq_notifier, 0, NULL);
25518e02
BW		 584
585 chained_irq_exit(ic, desc);
586}
587
b3241565
BG		 588static int sprd_eic_irq_notify(struct notifier_block *nb, unsigned long action,
589 void *data)
590{
591 struct sprd_eic *sprd_eic = to_sprd_eic(nb);
592
593 sprd_eic_handle_one_type(&sprd_eic->chip);
594
595 return NOTIFY_OK;
596}
597
2788938b
CG		 598static const struct irq_chip sprd_eic_irq = {
599 .name = "sprd-eic",
600 .irq_ack = sprd_eic_irq_ack,
601 .irq_mask = sprd_eic_irq_mask,
602 .irq_unmask = sprd_eic_irq_unmask,
603 .irq_set_type = sprd_eic_irq_set_type,
604 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
605 GPIOCHIP_IRQ_RESOURCE_HELPERS,
606};
dbd31c71
BG		 607
608static void sprd_eic_unregister_notifier(void *data)
609{
610 struct notifier_block *nb = data;
611
612 atomic_notifier_chain_unregister(&sprd_eic_irq_notifier, nb);
613}
614
25518e02
BW		 615static int sprd_eic_probe(struct platform_device *pdev)
616{
617 const struct sprd_eic_variant_data *pdata;
7777fa92 618 struct device *dev = &pdev->dev;
25518e02
BW		 619 struct gpio_irq_chip *irq;
620 struct sprd_eic *sprd_eic;
4ed7d7dd 621 struct resource *res;
25518e02
BW		 622 int ret, i;
623
7777fa92 624 pdata = of_device_get_match_data(dev);
25518e02 625 if (!pdata) {
7777fa92 626 dev_err(dev, "No matching driver data found.\n");
25518e02
BW		 627 return -EINVAL;
628 }
629
7777fa92 630 sprd_eic = devm_kzalloc(dev, sizeof(*sprd_eic), GFP_KERNEL);
25518e02
BW		 631 if (!sprd_eic)
632 return -ENOMEM;
633
634 spin_lock_init(&sprd_eic->lock);
635 sprd_eic->type = pdata->type;
636
637 sprd_eic->irq = platform_get_irq(pdev, 0);
15bddb7d 638 if (sprd_eic->irq < 0)
25518e02 639 return sprd_eic->irq;
25518e02
BW		 640
641 for (i = 0; i < SPRD_EIC_MAX_BANK; i++) {
642 /*
643 * We can have maximum 3 banks EICs, and each EIC has
644 * its own base address. But some platform maybe only
645 * have one bank EIC, thus base[1] and base[2] can be
646 * optional.
647 */
4ed7d7dd
BW		 648 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
649 if (!res)
263ade71 650 break;
4ed7d7dd 651
7777fa92 652 sprd_eic->base[i] = devm_ioremap_resource(dev, res);
4ed7d7dd
BW		 653 if (IS_ERR(sprd_eic->base[i]))
654 return PTR_ERR(sprd_eic->base[i]);
25518e02
BW		 655 }
656
657 sprd_eic->chip.label = sprd_eic_label_name[sprd_eic->type];
658 sprd_eic->chip.ngpio = pdata->num_eics;
659 sprd_eic->chip.base = -1;
7777fa92 660 sprd_eic->chip.parent = dev;
25518e02
BW		 661 sprd_eic->chip.direction_input = sprd_eic_direction_input;
662 switch (sprd_eic->type) {
663 case SPRD_EIC_DEBOUNCE:
664 sprd_eic->chip.request = sprd_eic_request;
665 sprd_eic->chip.free = sprd_eic_free;
666 sprd_eic->chip.set_config = sprd_eic_set_config;
667 sprd_eic->chip.set = sprd_eic_set;
df561f66 668 fallthrough;
25518e02 669 case SPRD_EIC_ASYNC:
25518e02
BW		 670 case SPRD_EIC_SYNC:
671 sprd_eic->chip.get = sprd_eic_get;
672 break;
673 case SPRD_EIC_LATCH:
25518e02
BW		 674 default:
675 break;
676 }
677
25518e02 678 irq = &sprd_eic->chip.irq;
2788938b 679 gpio_irq_chip_set_chip(irq, &sprd_eic_irq);
25518e02
BW		 680 irq->handler = handle_bad_irq;
681 irq->default_type = IRQ_TYPE_NONE;
682 irq->parent_handler = sprd_eic_irq_handler;
683 irq->parent_handler_data = sprd_eic;
684 irq->num_parents = 1;
685 irq->parents = &sprd_eic->irq;
686
7777fa92 687 ret = devm_gpiochip_add_data(dev, &sprd_eic->chip, sprd_eic);
25518e02 688 if (ret < 0) {
7777fa92 689 dev_err(dev, "Could not register gpiochip %d.\n", ret);
25518e02
BW		 690 return ret;
691 }
692
b3241565 693 sprd_eic->irq_nb.notifier_call = sprd_eic_irq_notify;
dbd31c71
BG		 694 ret = atomic_notifier_chain_register(&sprd_eic_irq_notifier,
695 &sprd_eic->irq_nb);
696 if (ret)
7777fa92 697 return dev_err_probe(dev, ret,
dbd31c71
BG		 698 "Failed to register with the interrupt notifier");
699
7777fa92 700 return devm_add_action_or_reset(dev, sprd_eic_unregister_notifier,
dbd31c71 701 &sprd_eic->irq_nb);
25518e02
BW		 702}
703
704static const struct of_device_id sprd_eic_of_match[] = {
705 {
706 .compatible = "sprd,sc9860-eic-debounce",
707 .data = &sc9860_eic_dbnc_data,
708 },
709 {
710 .compatible = "sprd,sc9860-eic-latch",
711 .data = &sc9860_eic_latch_data,
712 },
713 {
714 .compatible = "sprd,sc9860-eic-async",
715 .data = &sc9860_eic_async_data,
716 },
717 {
718 .compatible = "sprd,sc9860-eic-sync",
719 .data = &sc9860_eic_sync_data,
720 },
721 {
722 /* end of list */
723 }
724};
725MODULE_DEVICE_TABLE(of, sprd_eic_of_match);
726
727static struct platform_driver sprd_eic_driver = {
728 .probe = sprd_eic_probe,
729 .driver = {
730 .name = "sprd-eic",
731 .of_match_table = sprd_eic_of_match,
732 },
733};
734
735module_platform_driver(sprd_eic_driver);
736
737MODULE_DESCRIPTION("Spreadtrum EIC driver");
738MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)