Commit | Line | Data |
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7779b345 JI |
1 | /* |
2 | * Copyright (c) 2011 Jamie Iles | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * All enquiries to support@picochip.com | |
9 | */ | |
e6cb3486 | 10 | #include <linux/acpi.h> |
0f4630f3 LW |
11 | #include <linux/gpio/driver.h> |
12 | /* FIXME: for gpio_get_value(), replace this with direct register read */ | |
13 | #include <linux/gpio.h> | |
7779b345 JI |
14 | #include <linux/err.h> |
15 | #include <linux/init.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/ioport.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/irqdomain.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_address.h> | |
a72b8c4a | 24 | #include <linux/of_device.h> |
7779b345 JI |
25 | #include <linux/of_irq.h> |
26 | #include <linux/platform_device.h> | |
4ba8cfa7 | 27 | #include <linux/property.h> |
7779b345 | 28 | #include <linux/spinlock.h> |
3d2613c4 WC |
29 | #include <linux/platform_data/gpio-dwapb.h> |
30 | #include <linux/slab.h> | |
7779b345 | 31 | |
e6cb3486 JQ |
32 | #include "gpiolib.h" |
33 | ||
7779b345 JI |
34 | #define GPIO_SWPORTA_DR 0x00 |
35 | #define GPIO_SWPORTA_DDR 0x04 | |
36 | #define GPIO_SWPORTB_DR 0x0c | |
37 | #define GPIO_SWPORTB_DDR 0x10 | |
38 | #define GPIO_SWPORTC_DR 0x18 | |
39 | #define GPIO_SWPORTC_DDR 0x1c | |
40 | #define GPIO_SWPORTD_DR 0x24 | |
41 | #define GPIO_SWPORTD_DDR 0x28 | |
42 | #define GPIO_INTEN 0x30 | |
43 | #define GPIO_INTMASK 0x34 | |
44 | #define GPIO_INTTYPE_LEVEL 0x38 | |
45 | #define GPIO_INT_POLARITY 0x3c | |
46 | #define GPIO_INTSTATUS 0x40 | |
5d60d9ef | 47 | #define GPIO_PORTA_DEBOUNCE 0x48 |
7779b345 JI |
48 | #define GPIO_PORTA_EOI 0x4c |
49 | #define GPIO_EXT_PORTA 0x50 | |
50 | #define GPIO_EXT_PORTB 0x54 | |
51 | #define GPIO_EXT_PORTC 0x58 | |
52 | #define GPIO_EXT_PORTD 0x5c | |
53 | ||
54 | #define DWAPB_MAX_PORTS 4 | |
55 | #define GPIO_EXT_PORT_SIZE (GPIO_EXT_PORTB - GPIO_EXT_PORTA) | |
56 | #define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR) | |
57 | #define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR) | |
58 | ||
a72b8c4a HT |
59 | #define GPIO_REG_OFFSET_V2 1 |
60 | ||
61 | #define GPIO_INTMASK_V2 0x44 | |
62 | #define GPIO_INTTYPE_LEVEL_V2 0x34 | |
63 | #define GPIO_INT_POLARITY_V2 0x38 | |
64 | #define GPIO_INTSTATUS_V2 0x3c | |
65 | #define GPIO_PORTA_EOI_V2 0x40 | |
66 | ||
7779b345 JI |
67 | struct dwapb_gpio; |
68 | ||
1e960dbb WC |
69 | #ifdef CONFIG_PM_SLEEP |
70 | /* Store GPIO context across system-wide suspend/resume transitions */ | |
71 | struct dwapb_context { | |
72 | u32 data; | |
73 | u32 dir; | |
74 | u32 ext; | |
75 | u32 int_en; | |
76 | u32 int_mask; | |
77 | u32 int_type; | |
78 | u32 int_pol; | |
79 | u32 int_deb; | |
6437c7ba | 80 | u32 wake_en; |
1e960dbb WC |
81 | }; |
82 | #endif | |
83 | ||
7779b345 | 84 | struct dwapb_gpio_port { |
0f4630f3 | 85 | struct gpio_chip gc; |
7779b345 JI |
86 | bool is_registered; |
87 | struct dwapb_gpio *gpio; | |
1e960dbb WC |
88 | #ifdef CONFIG_PM_SLEEP |
89 | struct dwapb_context *ctx; | |
90 | #endif | |
91 | unsigned int idx; | |
7779b345 JI |
92 | }; |
93 | ||
94 | struct dwapb_gpio { | |
95 | struct device *dev; | |
96 | void __iomem *regs; | |
97 | struct dwapb_gpio_port *ports; | |
98 | unsigned int nr_ports; | |
99 | struct irq_domain *domain; | |
a72b8c4a | 100 | unsigned int flags; |
7779b345 JI |
101 | }; |
102 | ||
a72b8c4a HT |
103 | static inline u32 gpio_reg_v2_convert(unsigned int offset) |
104 | { | |
105 | switch (offset) { | |
106 | case GPIO_INTMASK: | |
107 | return GPIO_INTMASK_V2; | |
108 | case GPIO_INTTYPE_LEVEL: | |
109 | return GPIO_INTTYPE_LEVEL_V2; | |
110 | case GPIO_INT_POLARITY: | |
111 | return GPIO_INT_POLARITY_V2; | |
112 | case GPIO_INTSTATUS: | |
113 | return GPIO_INTSTATUS_V2; | |
114 | case GPIO_PORTA_EOI: | |
115 | return GPIO_PORTA_EOI_V2; | |
116 | } | |
117 | ||
118 | return offset; | |
119 | } | |
120 | ||
121 | static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset) | |
122 | { | |
123 | if (gpio->flags & GPIO_REG_OFFSET_V2) | |
124 | return gpio_reg_v2_convert(offset); | |
125 | ||
126 | return offset; | |
127 | } | |
128 | ||
67809b97 WC |
129 | static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset) |
130 | { | |
0f4630f3 | 131 | struct gpio_chip *gc = &gpio->ports[0].gc; |
67809b97 WC |
132 | void __iomem *reg_base = gpio->regs; |
133 | ||
a72b8c4a | 134 | return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset)); |
67809b97 WC |
135 | } |
136 | ||
137 | static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset, | |
138 | u32 val) | |
139 | { | |
0f4630f3 | 140 | struct gpio_chip *gc = &gpio->ports[0].gc; |
67809b97 WC |
141 | void __iomem *reg_base = gpio->regs; |
142 | ||
a72b8c4a | 143 | gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val); |
67809b97 WC |
144 | } |
145 | ||
7779b345 JI |
146 | static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset) |
147 | { | |
0f4630f3 | 148 | struct dwapb_gpio_port *port = gpiochip_get_data(gc); |
7779b345 JI |
149 | struct dwapb_gpio *gpio = port->gpio; |
150 | ||
151 | return irq_find_mapping(gpio->domain, offset); | |
152 | } | |
153 | ||
154 | static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs) | |
155 | { | |
67809b97 | 156 | u32 v = dwapb_read(gpio, GPIO_INT_POLARITY); |
7779b345 | 157 | |
0f4630f3 | 158 | if (gpio_get_value(gpio->ports[0].gc.base + offs)) |
7779b345 JI |
159 | v &= ~BIT(offs); |
160 | else | |
161 | v |= BIT(offs); | |
162 | ||
67809b97 | 163 | dwapb_write(gpio, GPIO_INT_POLARITY, v); |
7779b345 JI |
164 | } |
165 | ||
3d2613c4 | 166 | static u32 dwapb_do_irq(struct dwapb_gpio *gpio) |
7779b345 | 167 | { |
5664aa1c | 168 | u32 irq_status = dwapb_read(gpio, GPIO_INTSTATUS); |
3d2613c4 | 169 | u32 ret = irq_status; |
7779b345 JI |
170 | |
171 | while (irq_status) { | |
172 | int hwirq = fls(irq_status) - 1; | |
173 | int gpio_irq = irq_find_mapping(gpio->domain, hwirq); | |
174 | ||
175 | generic_handle_irq(gpio_irq); | |
176 | irq_status &= ~BIT(hwirq); | |
177 | ||
178 | if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK) | |
179 | == IRQ_TYPE_EDGE_BOTH) | |
180 | dwapb_toggle_trigger(gpio, hwirq); | |
181 | } | |
182 | ||
3d2613c4 WC |
183 | return ret; |
184 | } | |
185 | ||
bd0b9ac4 | 186 | static void dwapb_irq_handler(struct irq_desc *desc) |
3d2613c4 | 187 | { |
476f8b4c | 188 | struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc); |
3d2613c4 WC |
189 | struct irq_chip *chip = irq_desc_get_chip(desc); |
190 | ||
191 | dwapb_do_irq(gpio); | |
192 | ||
7779b345 JI |
193 | if (chip->irq_eoi) |
194 | chip->irq_eoi(irq_desc_get_irq_data(desc)); | |
195 | } | |
196 | ||
197 | static void dwapb_irq_enable(struct irq_data *d) | |
198 | { | |
199 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
200 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 201 | struct gpio_chip *gc = &gpio->ports[0].gc; |
7779b345 JI |
202 | unsigned long flags; |
203 | u32 val; | |
204 | ||
0f4630f3 | 205 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
67809b97 | 206 | val = dwapb_read(gpio, GPIO_INTEN); |
7779b345 | 207 | val |= BIT(d->hwirq); |
67809b97 | 208 | dwapb_write(gpio, GPIO_INTEN, val); |
0f4630f3 | 209 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
7779b345 JI |
210 | } |
211 | ||
212 | static void dwapb_irq_disable(struct irq_data *d) | |
213 | { | |
214 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
215 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 216 | struct gpio_chip *gc = &gpio->ports[0].gc; |
7779b345 JI |
217 | unsigned long flags; |
218 | u32 val; | |
219 | ||
0f4630f3 | 220 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
67809b97 | 221 | val = dwapb_read(gpio, GPIO_INTEN); |
7779b345 | 222 | val &= ~BIT(d->hwirq); |
67809b97 | 223 | dwapb_write(gpio, GPIO_INTEN, val); |
0f4630f3 | 224 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
7779b345 JI |
225 | } |
226 | ||
57ef0428 | 227 | static int dwapb_irq_reqres(struct irq_data *d) |
7779b345 JI |
228 | { |
229 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
230 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 231 | struct gpio_chip *gc = &gpio->ports[0].gc; |
7779b345 | 232 | |
0f4630f3 | 233 | if (gpiochip_lock_as_irq(gc, irqd_to_hwirq(d))) { |
7779b345 JI |
234 | dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n", |
235 | irqd_to_hwirq(d)); | |
57ef0428 LW |
236 | return -EINVAL; |
237 | } | |
7779b345 JI |
238 | return 0; |
239 | } | |
240 | ||
57ef0428 | 241 | static void dwapb_irq_relres(struct irq_data *d) |
7779b345 JI |
242 | { |
243 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
244 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 245 | struct gpio_chip *gc = &gpio->ports[0].gc; |
7779b345 | 246 | |
0f4630f3 | 247 | gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d)); |
7779b345 JI |
248 | } |
249 | ||
250 | static int dwapb_irq_set_type(struct irq_data *d, u32 type) | |
251 | { | |
252 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
253 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 254 | struct gpio_chip *gc = &gpio->ports[0].gc; |
7779b345 JI |
255 | int bit = d->hwirq; |
256 | unsigned long level, polarity, flags; | |
257 | ||
258 | if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | | |
259 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | |
260 | return -EINVAL; | |
261 | ||
0f4630f3 | 262 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
67809b97 WC |
263 | level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); |
264 | polarity = dwapb_read(gpio, GPIO_INT_POLARITY); | |
7779b345 JI |
265 | |
266 | switch (type) { | |
267 | case IRQ_TYPE_EDGE_BOTH: | |
268 | level |= BIT(bit); | |
269 | dwapb_toggle_trigger(gpio, bit); | |
270 | break; | |
271 | case IRQ_TYPE_EDGE_RISING: | |
272 | level |= BIT(bit); | |
273 | polarity |= BIT(bit); | |
274 | break; | |
275 | case IRQ_TYPE_EDGE_FALLING: | |
276 | level |= BIT(bit); | |
277 | polarity &= ~BIT(bit); | |
278 | break; | |
279 | case IRQ_TYPE_LEVEL_HIGH: | |
280 | level &= ~BIT(bit); | |
281 | polarity |= BIT(bit); | |
282 | break; | |
283 | case IRQ_TYPE_LEVEL_LOW: | |
284 | level &= ~BIT(bit); | |
285 | polarity &= ~BIT(bit); | |
286 | break; | |
287 | } | |
288 | ||
6a2f4b7d SAS |
289 | irq_setup_alt_chip(d, type); |
290 | ||
67809b97 | 291 | dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level); |
edadced2 XC |
292 | if (type != IRQ_TYPE_EDGE_BOTH) |
293 | dwapb_write(gpio, GPIO_INT_POLARITY, polarity); | |
0f4630f3 | 294 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
7779b345 JI |
295 | |
296 | return 0; | |
297 | } | |
298 | ||
6437c7ba HT |
299 | #ifdef CONFIG_PM_SLEEP |
300 | static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable) | |
301 | { | |
302 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
303 | struct dwapb_gpio *gpio = igc->private; | |
304 | struct dwapb_context *ctx = gpio->ports[0].ctx; | |
305 | ||
306 | if (enable) | |
307 | ctx->wake_en |= BIT(d->hwirq); | |
308 | else | |
309 | ctx->wake_en &= ~BIT(d->hwirq); | |
310 | ||
311 | return 0; | |
312 | } | |
313 | #endif | |
314 | ||
5d60d9ef WC |
315 | static int dwapb_gpio_set_debounce(struct gpio_chip *gc, |
316 | unsigned offset, unsigned debounce) | |
317 | { | |
0f4630f3 | 318 | struct dwapb_gpio_port *port = gpiochip_get_data(gc); |
5d60d9ef WC |
319 | struct dwapb_gpio *gpio = port->gpio; |
320 | unsigned long flags, val_deb; | |
0f4630f3 | 321 | unsigned long mask = gc->pin2mask(gc, offset); |
5d60d9ef | 322 | |
0f4630f3 | 323 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
5d60d9ef WC |
324 | |
325 | val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); | |
326 | if (debounce) | |
327 | dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask); | |
328 | else | |
329 | dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask); | |
330 | ||
0f4630f3 | 331 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
5d60d9ef WC |
332 | |
333 | return 0; | |
334 | } | |
335 | ||
2956b5d9 MW |
336 | static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset, |
337 | unsigned long config) | |
338 | { | |
339 | u32 debounce; | |
340 | ||
341 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
342 | return -ENOTSUPP; | |
343 | ||
344 | debounce = pinconf_to_config_argument(config); | |
345 | return dwapb_gpio_set_debounce(gc, offset, debounce); | |
346 | } | |
347 | ||
3d2613c4 WC |
348 | static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id) |
349 | { | |
350 | u32 worked; | |
351 | struct dwapb_gpio *gpio = dev_id; | |
352 | ||
353 | worked = dwapb_do_irq(gpio); | |
354 | ||
355 | return worked ? IRQ_HANDLED : IRQ_NONE; | |
356 | } | |
357 | ||
7779b345 | 358 | static void dwapb_configure_irqs(struct dwapb_gpio *gpio, |
3d2613c4 WC |
359 | struct dwapb_gpio_port *port, |
360 | struct dwapb_port_property *pp) | |
7779b345 | 361 | { |
0f4630f3 | 362 | struct gpio_chip *gc = &port->gc; |
4ba8cfa7 | 363 | struct fwnode_handle *fwnode = pp->fwnode; |
3d2613c4 | 364 | struct irq_chip_generic *irq_gc = NULL; |
7779b345 JI |
365 | unsigned int hwirq, ngpio = gc->ngpio; |
366 | struct irq_chip_type *ct; | |
3d2613c4 | 367 | int err, i; |
7779b345 | 368 | |
4ba8cfa7 JQ |
369 | gpio->domain = irq_domain_create_linear(fwnode, ngpio, |
370 | &irq_generic_chip_ops, gpio); | |
7779b345 JI |
371 | if (!gpio->domain) |
372 | return; | |
373 | ||
6a2f4b7d | 374 | err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2, |
7779b345 JI |
375 | "gpio-dwapb", handle_level_irq, |
376 | IRQ_NOREQUEST, 0, | |
377 | IRQ_GC_INIT_NESTED_LOCK); | |
378 | if (err) { | |
379 | dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n"); | |
380 | irq_domain_remove(gpio->domain); | |
381 | gpio->domain = NULL; | |
382 | return; | |
383 | } | |
384 | ||
385 | irq_gc = irq_get_domain_generic_chip(gpio->domain, 0); | |
386 | if (!irq_gc) { | |
387 | irq_domain_remove(gpio->domain); | |
388 | gpio->domain = NULL; | |
389 | return; | |
390 | } | |
391 | ||
392 | irq_gc->reg_base = gpio->regs; | |
393 | irq_gc->private = gpio; | |
394 | ||
6a2f4b7d SAS |
395 | for (i = 0; i < 2; i++) { |
396 | ct = &irq_gc->chip_types[i]; | |
397 | ct->chip.irq_ack = irq_gc_ack_set_bit; | |
398 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
399 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
400 | ct->chip.irq_set_type = dwapb_irq_set_type; | |
401 | ct->chip.irq_enable = dwapb_irq_enable; | |
402 | ct->chip.irq_disable = dwapb_irq_disable; | |
403 | ct->chip.irq_request_resources = dwapb_irq_reqres; | |
404 | ct->chip.irq_release_resources = dwapb_irq_relres; | |
6437c7ba HT |
405 | #ifdef CONFIG_PM_SLEEP |
406 | ct->chip.irq_set_wake = dwapb_irq_set_wake; | |
407 | #endif | |
a72b8c4a HT |
408 | ct->regs.ack = gpio_reg_convert(gpio, GPIO_PORTA_EOI); |
409 | ct->regs.mask = gpio_reg_convert(gpio, GPIO_INTMASK); | |
6a2f4b7d SAS |
410 | ct->type = IRQ_TYPE_LEVEL_MASK; |
411 | } | |
412 | ||
413 | irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; | |
414 | irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; | |
415 | irq_gc->chip_types[1].handler = handle_edge_irq; | |
7779b345 | 416 | |
3d2613c4 | 417 | if (!pp->irq_shared) { |
6218b88d TG |
418 | irq_set_chained_handler_and_data(pp->irq, dwapb_irq_handler, |
419 | gpio); | |
3d2613c4 WC |
420 | } else { |
421 | /* | |
422 | * Request a shared IRQ since where MFD would have devices | |
423 | * using the same irq pin | |
424 | */ | |
425 | err = devm_request_irq(gpio->dev, pp->irq, | |
426 | dwapb_irq_handler_mfd, | |
427 | IRQF_SHARED, "gpio-dwapb-mfd", gpio); | |
428 | if (err) { | |
429 | dev_err(gpio->dev, "error requesting IRQ\n"); | |
430 | irq_domain_remove(gpio->domain); | |
431 | gpio->domain = NULL; | |
432 | return; | |
433 | } | |
434 | } | |
7779b345 JI |
435 | |
436 | for (hwirq = 0 ; hwirq < ngpio ; hwirq++) | |
437 | irq_create_mapping(gpio->domain, hwirq); | |
438 | ||
0f4630f3 | 439 | port->gc.to_irq = dwapb_gpio_to_irq; |
7779b345 JI |
440 | } |
441 | ||
442 | static void dwapb_irq_teardown(struct dwapb_gpio *gpio) | |
443 | { | |
444 | struct dwapb_gpio_port *port = &gpio->ports[0]; | |
0f4630f3 | 445 | struct gpio_chip *gc = &port->gc; |
7779b345 JI |
446 | unsigned int ngpio = gc->ngpio; |
447 | irq_hw_number_t hwirq; | |
448 | ||
449 | if (!gpio->domain) | |
450 | return; | |
451 | ||
452 | for (hwirq = 0 ; hwirq < ngpio ; hwirq++) | |
453 | irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq)); | |
454 | ||
455 | irq_domain_remove(gpio->domain); | |
456 | gpio->domain = NULL; | |
457 | } | |
458 | ||
459 | static int dwapb_gpio_add_port(struct dwapb_gpio *gpio, | |
3d2613c4 | 460 | struct dwapb_port_property *pp, |
7779b345 JI |
461 | unsigned int offs) |
462 | { | |
463 | struct dwapb_gpio_port *port; | |
7779b345 JI |
464 | void __iomem *dat, *set, *dirout; |
465 | int err; | |
466 | ||
7779b345 JI |
467 | port = &gpio->ports[offs]; |
468 | port->gpio = gpio; | |
1e960dbb WC |
469 | port->idx = pp->idx; |
470 | ||
471 | #ifdef CONFIG_PM_SLEEP | |
472 | port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL); | |
473 | if (!port->ctx) | |
474 | return -ENOMEM; | |
475 | #endif | |
7779b345 | 476 | |
3d2613c4 WC |
477 | dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_SIZE); |
478 | set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_SIZE); | |
7779b345 | 479 | dirout = gpio->regs + GPIO_SWPORTA_DDR + |
3d2613c4 | 480 | (pp->idx * GPIO_SWPORT_DDR_SIZE); |
7779b345 | 481 | |
0f4630f3 | 482 | err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout, |
7779b345 JI |
483 | NULL, false); |
484 | if (err) { | |
e8159181 JQ |
485 | dev_err(gpio->dev, "failed to init gpio chip for port%d\n", |
486 | port->idx); | |
7779b345 JI |
487 | return err; |
488 | } | |
489 | ||
3d2613c4 | 490 | #ifdef CONFIG_OF_GPIO |
4ba8cfa7 | 491 | port->gc.of_node = to_of_node(pp->fwnode); |
3d2613c4 | 492 | #endif |
0f4630f3 LW |
493 | port->gc.ngpio = pp->ngpio; |
494 | port->gc.base = pp->gpio_base; | |
7779b345 | 495 | |
5d60d9ef WC |
496 | /* Only port A support debounce */ |
497 | if (pp->idx == 0) | |
2956b5d9 | 498 | port->gc.set_config = dwapb_gpio_set_config; |
5d60d9ef | 499 | |
3d2613c4 WC |
500 | if (pp->irq) |
501 | dwapb_configure_irqs(gpio, port, pp); | |
7779b345 | 502 | |
0f4630f3 | 503 | err = gpiochip_add_data(&port->gc, port); |
7779b345 | 504 | if (err) |
e8159181 JQ |
505 | dev_err(gpio->dev, "failed to register gpiochip for port%d\n", |
506 | port->idx); | |
7779b345 JI |
507 | else |
508 | port->is_registered = true; | |
509 | ||
e6cb3486 JQ |
510 | /* Add GPIO-signaled ACPI event support */ |
511 | if (pp->irq) | |
512 | acpi_gpiochip_request_interrupts(&port->gc); | |
513 | ||
7779b345 JI |
514 | return err; |
515 | } | |
516 | ||
517 | static void dwapb_gpio_unregister(struct dwapb_gpio *gpio) | |
518 | { | |
519 | unsigned int m; | |
520 | ||
521 | for (m = 0; m < gpio->nr_ports; ++m) | |
522 | if (gpio->ports[m].is_registered) | |
0f4630f3 | 523 | gpiochip_remove(&gpio->ports[m].gc); |
7779b345 JI |
524 | } |
525 | ||
3d2613c4 | 526 | static struct dwapb_platform_data * |
4ba8cfa7 | 527 | dwapb_gpio_get_pdata(struct device *dev) |
3d2613c4 | 528 | { |
4ba8cfa7 | 529 | struct fwnode_handle *fwnode; |
3d2613c4 WC |
530 | struct dwapb_platform_data *pdata; |
531 | struct dwapb_port_property *pp; | |
532 | int nports; | |
533 | int i; | |
534 | ||
4ba8cfa7 | 535 | nports = device_get_child_node_count(dev); |
3d2613c4 WC |
536 | if (nports == 0) |
537 | return ERR_PTR(-ENODEV); | |
538 | ||
da9df93e | 539 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); |
3d2613c4 WC |
540 | if (!pdata) |
541 | return ERR_PTR(-ENOMEM); | |
542 | ||
da9df93e AL |
543 | pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL); |
544 | if (!pdata->properties) | |
3d2613c4 | 545 | return ERR_PTR(-ENOMEM); |
3d2613c4 WC |
546 | |
547 | pdata->nports = nports; | |
548 | ||
549 | i = 0; | |
4ba8cfa7 | 550 | device_for_each_child_node(dev, fwnode) { |
3d2613c4 | 551 | pp = &pdata->properties[i++]; |
4ba8cfa7 | 552 | pp->fwnode = fwnode; |
3d2613c4 | 553 | |
4ba8cfa7 | 554 | if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) || |
3d2613c4 | 555 | pp->idx >= DWAPB_MAX_PORTS) { |
e8159181 JQ |
556 | dev_err(dev, |
557 | "missing/invalid port index for port%d\n", i); | |
bfab7c8f | 558 | fwnode_handle_put(fwnode); |
3d2613c4 WC |
559 | return ERR_PTR(-EINVAL); |
560 | } | |
561 | ||
4ba8cfa7 | 562 | if (fwnode_property_read_u32(fwnode, "snps,nr-gpios", |
3d2613c4 | 563 | &pp->ngpio)) { |
e8159181 JQ |
564 | dev_info(dev, |
565 | "failed to get number of gpios for port%d\n", | |
566 | i); | |
3d2613c4 WC |
567 | pp->ngpio = 32; |
568 | } | |
569 | ||
570 | /* | |
571 | * Only port A can provide interrupts in all configurations of | |
572 | * the IP. | |
573 | */ | |
4ba8cfa7 JQ |
574 | if (dev->of_node && pp->idx == 0 && |
575 | fwnode_property_read_bool(fwnode, | |
576 | "interrupt-controller")) { | |
577 | pp->irq = irq_of_parse_and_map(to_of_node(fwnode), 0); | |
e8159181 JQ |
578 | if (!pp->irq) |
579 | dev_warn(dev, "no irq for port%d\n", pp->idx); | |
3d2613c4 WC |
580 | } |
581 | ||
e6cb3486 JQ |
582 | if (has_acpi_companion(dev) && pp->idx == 0) |
583 | pp->irq = platform_get_irq(to_platform_device(dev), 0); | |
584 | ||
3d2613c4 WC |
585 | pp->irq_shared = false; |
586 | pp->gpio_base = -1; | |
3d2613c4 WC |
587 | } |
588 | ||
589 | return pdata; | |
590 | } | |
591 | ||
a72b8c4a HT |
592 | static const struct of_device_id dwapb_of_match[] = { |
593 | { .compatible = "snps,dw-apb-gpio", .data = (void *)0}, | |
594 | { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2}, | |
595 | { /* Sentinel */ } | |
596 | }; | |
597 | MODULE_DEVICE_TABLE(of, dwapb_of_match); | |
598 | ||
599 | static const struct acpi_device_id dwapb_acpi_match[] = { | |
600 | {"HISI0181", 0}, | |
601 | {"APMC0D07", 0}, | |
602 | {"APMC0D81", GPIO_REG_OFFSET_V2}, | |
603 | { } | |
604 | }; | |
605 | MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match); | |
606 | ||
7779b345 JI |
607 | static int dwapb_gpio_probe(struct platform_device *pdev) |
608 | { | |
3d2613c4 | 609 | unsigned int i; |
7779b345 JI |
610 | struct resource *res; |
611 | struct dwapb_gpio *gpio; | |
7779b345 | 612 | int err; |
3d2613c4 WC |
613 | struct device *dev = &pdev->dev; |
614 | struct dwapb_platform_data *pdata = dev_get_platdata(dev); | |
3d2613c4 | 615 | |
da9df93e | 616 | if (!pdata) { |
4ba8cfa7 | 617 | pdata = dwapb_gpio_get_pdata(dev); |
3d2613c4 WC |
618 | if (IS_ERR(pdata)) |
619 | return PTR_ERR(pdata); | |
620 | } | |
7779b345 | 621 | |
da9df93e AL |
622 | if (!pdata->nports) |
623 | return -ENODEV; | |
7779b345 | 624 | |
3d2613c4 | 625 | gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); |
da9df93e AL |
626 | if (!gpio) |
627 | return -ENOMEM; | |
628 | ||
3d2613c4 WC |
629 | gpio->dev = &pdev->dev; |
630 | gpio->nr_ports = pdata->nports; | |
631 | ||
632 | gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports, | |
7779b345 | 633 | sizeof(*gpio->ports), GFP_KERNEL); |
da9df93e AL |
634 | if (!gpio->ports) |
635 | return -ENOMEM; | |
7779b345 JI |
636 | |
637 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
638 | gpio->regs = devm_ioremap_resource(&pdev->dev, res); | |
da9df93e AL |
639 | if (IS_ERR(gpio->regs)) |
640 | return PTR_ERR(gpio->regs); | |
7779b345 | 641 | |
a72b8c4a HT |
642 | gpio->flags = 0; |
643 | if (dev->of_node) { | |
644 | const struct of_device_id *of_devid; | |
645 | ||
646 | of_devid = of_match_device(dwapb_of_match, dev); | |
647 | if (of_devid) { | |
648 | if (of_devid->data) | |
649 | gpio->flags = (uintptr_t)of_devid->data; | |
650 | } | |
651 | } else if (has_acpi_companion(dev)) { | |
652 | const struct acpi_device_id *acpi_id; | |
653 | ||
654 | acpi_id = acpi_match_device(dwapb_acpi_match, dev); | |
655 | if (acpi_id) { | |
656 | if (acpi_id->driver_data) | |
657 | gpio->flags = acpi_id->driver_data; | |
658 | } | |
659 | } | |
660 | ||
3d2613c4 WC |
661 | for (i = 0; i < gpio->nr_ports; i++) { |
662 | err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i); | |
7779b345 JI |
663 | if (err) |
664 | goto out_unregister; | |
665 | } | |
666 | platform_set_drvdata(pdev, gpio); | |
667 | ||
da9df93e | 668 | return 0; |
7779b345 JI |
669 | |
670 | out_unregister: | |
671 | dwapb_gpio_unregister(gpio); | |
672 | dwapb_irq_teardown(gpio); | |
673 | ||
7779b345 JI |
674 | return err; |
675 | } | |
676 | ||
677 | static int dwapb_gpio_remove(struct platform_device *pdev) | |
678 | { | |
679 | struct dwapb_gpio *gpio = platform_get_drvdata(pdev); | |
680 | ||
681 | dwapb_gpio_unregister(gpio); | |
682 | dwapb_irq_teardown(gpio); | |
683 | ||
684 | return 0; | |
685 | } | |
686 | ||
1e960dbb WC |
687 | #ifdef CONFIG_PM_SLEEP |
688 | static int dwapb_gpio_suspend(struct device *dev) | |
689 | { | |
690 | struct platform_device *pdev = to_platform_device(dev); | |
691 | struct dwapb_gpio *gpio = platform_get_drvdata(pdev); | |
0f4630f3 | 692 | struct gpio_chip *gc = &gpio->ports[0].gc; |
1e960dbb WC |
693 | unsigned long flags; |
694 | int i; | |
695 | ||
0f4630f3 | 696 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
1e960dbb WC |
697 | for (i = 0; i < gpio->nr_ports; i++) { |
698 | unsigned int offset; | |
699 | unsigned int idx = gpio->ports[i].idx; | |
700 | struct dwapb_context *ctx = gpio->ports[i].ctx; | |
701 | ||
58a3b92d | 702 | BUG_ON(!ctx); |
1e960dbb WC |
703 | |
704 | offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE; | |
705 | ctx->dir = dwapb_read(gpio, offset); | |
706 | ||
707 | offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE; | |
708 | ctx->data = dwapb_read(gpio, offset); | |
709 | ||
710 | offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE; | |
711 | ctx->ext = dwapb_read(gpio, offset); | |
712 | ||
713 | /* Only port A can provide interrupts */ | |
714 | if (idx == 0) { | |
715 | ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK); | |
716 | ctx->int_en = dwapb_read(gpio, GPIO_INTEN); | |
717 | ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY); | |
718 | ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); | |
719 | ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); | |
720 | ||
721 | /* Mask out interrupts */ | |
6437c7ba HT |
722 | dwapb_write(gpio, GPIO_INTMASK, |
723 | 0xffffffff & ~ctx->wake_en); | |
1e960dbb WC |
724 | } |
725 | } | |
0f4630f3 | 726 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
1e960dbb WC |
727 | |
728 | return 0; | |
729 | } | |
730 | ||
731 | static int dwapb_gpio_resume(struct device *dev) | |
732 | { | |
733 | struct platform_device *pdev = to_platform_device(dev); | |
734 | struct dwapb_gpio *gpio = platform_get_drvdata(pdev); | |
0f4630f3 | 735 | struct gpio_chip *gc = &gpio->ports[0].gc; |
1e960dbb WC |
736 | unsigned long flags; |
737 | int i; | |
738 | ||
0f4630f3 | 739 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
1e960dbb WC |
740 | for (i = 0; i < gpio->nr_ports; i++) { |
741 | unsigned int offset; | |
742 | unsigned int idx = gpio->ports[i].idx; | |
743 | struct dwapb_context *ctx = gpio->ports[i].ctx; | |
744 | ||
58a3b92d | 745 | BUG_ON(!ctx); |
1e960dbb WC |
746 | |
747 | offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE; | |
748 | dwapb_write(gpio, offset, ctx->data); | |
749 | ||
750 | offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE; | |
751 | dwapb_write(gpio, offset, ctx->dir); | |
752 | ||
753 | offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE; | |
754 | dwapb_write(gpio, offset, ctx->ext); | |
755 | ||
756 | /* Only port A can provide interrupts */ | |
757 | if (idx == 0) { | |
758 | dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type); | |
759 | dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol); | |
760 | dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb); | |
761 | dwapb_write(gpio, GPIO_INTEN, ctx->int_en); | |
762 | dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask); | |
763 | ||
764 | /* Clear out spurious interrupts */ | |
765 | dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff); | |
766 | } | |
767 | } | |
0f4630f3 | 768 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
1e960dbb WC |
769 | |
770 | return 0; | |
771 | } | |
772 | #endif | |
773 | ||
774 | static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend, | |
775 | dwapb_gpio_resume); | |
776 | ||
7779b345 JI |
777 | static struct platform_driver dwapb_gpio_driver = { |
778 | .driver = { | |
779 | .name = "gpio-dwapb", | |
1e960dbb | 780 | .pm = &dwapb_gpio_pm_ops, |
7779b345 | 781 | .of_match_table = of_match_ptr(dwapb_of_match), |
e6cb3486 | 782 | .acpi_match_table = ACPI_PTR(dwapb_acpi_match), |
7779b345 JI |
783 | }, |
784 | .probe = dwapb_gpio_probe, | |
785 | .remove = dwapb_gpio_remove, | |
786 | }; | |
787 | ||
788 | module_platform_driver(dwapb_gpio_driver); | |
789 | ||
790 | MODULE_LICENSE("GPL"); | |
791 | MODULE_AUTHOR("Jamie Iles"); | |
792 | MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver"); |