Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
7779b345 JI |
2 | /* |
3 | * Copyright (c) 2011 Jamie Iles | |
4 | * | |
7779b345 JI |
5 | * All enquiries to support@picochip.com |
6 | */ | |
e6cb3486 | 7 | #include <linux/acpi.h> |
e6bf3773 | 8 | #include <linux/clk.h> |
7779b345 | 9 | #include <linux/err.h> |
e6bf3773 | 10 | #include <linux/gpio/driver.h> |
7779b345 JI |
11 | #include <linux/init.h> |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/irq.h> | |
043a0c9f | 16 | #include <linux/mod_devicetable.h> |
7779b345 | 17 | #include <linux/module.h> |
7779b345 | 18 | #include <linux/platform_device.h> |
4ba8cfa7 | 19 | #include <linux/property.h> |
07901a94 | 20 | #include <linux/reset.h> |
3d2613c4 | 21 | #include <linux/slab.h> |
043a0c9f | 22 | #include <linux/spinlock.h> |
7779b345 | 23 | |
77cb907a | 24 | #include "gpiolib-acpi.h" |
e6cb3486 | 25 | |
7779b345 JI |
26 | #define GPIO_SWPORTA_DR 0x00 |
27 | #define GPIO_SWPORTA_DDR 0x04 | |
28 | #define GPIO_SWPORTB_DR 0x0c | |
29 | #define GPIO_SWPORTB_DDR 0x10 | |
30 | #define GPIO_SWPORTC_DR 0x18 | |
31 | #define GPIO_SWPORTC_DDR 0x1c | |
32 | #define GPIO_SWPORTD_DR 0x24 | |
33 | #define GPIO_SWPORTD_DDR 0x28 | |
34 | #define GPIO_INTEN 0x30 | |
35 | #define GPIO_INTMASK 0x34 | |
36 | #define GPIO_INTTYPE_LEVEL 0x38 | |
37 | #define GPIO_INT_POLARITY 0x3c | |
38 | #define GPIO_INTSTATUS 0x40 | |
5d60d9ef | 39 | #define GPIO_PORTA_DEBOUNCE 0x48 |
7779b345 JI |
40 | #define GPIO_PORTA_EOI 0x4c |
41 | #define GPIO_EXT_PORTA 0x50 | |
42 | #define GPIO_EXT_PORTB 0x54 | |
43 | #define GPIO_EXT_PORTC 0x58 | |
44 | #define GPIO_EXT_PORTD 0x5c | |
45 | ||
c58220cb | 46 | #define DWAPB_DRIVER_NAME "gpio-dwapb" |
7779b345 | 47 | #define DWAPB_MAX_PORTS 4 |
5111c2b6 | 48 | #define DWAPB_MAX_GPIOS 32 |
c58220cb | 49 | |
89f99feb LW |
50 | #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */ |
51 | #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */ | |
52 | #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */ | |
7779b345 | 53 | |
e1610431 | 54 | #define GPIO_REG_OFFSET_V1 0 |
a72b8c4a | 55 | #define GPIO_REG_OFFSET_V2 1 |
e1610431 | 56 | #define GPIO_REG_OFFSET_MASK BIT(0) |
a72b8c4a HT |
57 | |
58 | #define GPIO_INTMASK_V2 0x44 | |
59 | #define GPIO_INTTYPE_LEVEL_V2 0x34 | |
60 | #define GPIO_INT_POLARITY_V2 0x38 | |
61 | #define GPIO_INTSTATUS_V2 0x3c | |
62 | #define GPIO_PORTA_EOI_V2 0x40 | |
63 | ||
5c544c92 SS |
64 | #define DWAPB_NR_CLOCKS 2 |
65 | ||
7779b345 JI |
66 | struct dwapb_gpio; |
67 | ||
5111c2b6 AS |
68 | struct dwapb_port_property { |
69 | struct fwnode_handle *fwnode; | |
70 | unsigned int idx; | |
71 | unsigned int ngpio; | |
72 | unsigned int gpio_base; | |
73 | int irq[DWAPB_MAX_GPIOS]; | |
74 | }; | |
75 | ||
76 | struct dwapb_platform_data { | |
77 | struct dwapb_port_property *properties; | |
78 | unsigned int nports; | |
79 | }; | |
80 | ||
1e960dbb WC |
81 | #ifdef CONFIG_PM_SLEEP |
82 | /* Store GPIO context across system-wide suspend/resume transitions */ | |
83 | struct dwapb_context { | |
84 | u32 data; | |
85 | u32 dir; | |
86 | u32 ext; | |
87 | u32 int_en; | |
88 | u32 int_mask; | |
89 | u32 int_type; | |
90 | u32 int_pol; | |
91 | u32 int_deb; | |
6437c7ba | 92 | u32 wake_en; |
1e960dbb WC |
93 | }; |
94 | #endif | |
95 | ||
0ea68393 | 96 | struct dwapb_gpio_port_irqchip { |
0ea68393 SS |
97 | unsigned int nr_irqs; |
98 | unsigned int irq[DWAPB_MAX_GPIOS]; | |
99 | }; | |
100 | ||
7779b345 | 101 | struct dwapb_gpio_port { |
0f4630f3 | 102 | struct gpio_chip gc; |
0ea68393 | 103 | struct dwapb_gpio_port_irqchip *pirq; |
7779b345 | 104 | struct dwapb_gpio *gpio; |
1e960dbb WC |
105 | #ifdef CONFIG_PM_SLEEP |
106 | struct dwapb_context *ctx; | |
107 | #endif | |
108 | unsigned int idx; | |
7779b345 | 109 | }; |
0ea68393 SS |
110 | #define to_dwapb_gpio(_gc) \ |
111 | (container_of(_gc, struct dwapb_gpio_port, gc)->gpio) | |
7779b345 JI |
112 | |
113 | struct dwapb_gpio { | |
114 | struct device *dev; | |
115 | void __iomem *regs; | |
116 | struct dwapb_gpio_port *ports; | |
117 | unsigned int nr_ports; | |
a72b8c4a | 118 | unsigned int flags; |
07901a94 | 119 | struct reset_control *rst; |
5c544c92 | 120 | struct clk_bulk_data clks[DWAPB_NR_CLOCKS]; |
7779b345 JI |
121 | }; |
122 | ||
a72b8c4a HT |
123 | static inline u32 gpio_reg_v2_convert(unsigned int offset) |
124 | { | |
125 | switch (offset) { | |
126 | case GPIO_INTMASK: | |
127 | return GPIO_INTMASK_V2; | |
128 | case GPIO_INTTYPE_LEVEL: | |
129 | return GPIO_INTTYPE_LEVEL_V2; | |
130 | case GPIO_INT_POLARITY: | |
131 | return GPIO_INT_POLARITY_V2; | |
132 | case GPIO_INTSTATUS: | |
133 | return GPIO_INTSTATUS_V2; | |
134 | case GPIO_PORTA_EOI: | |
135 | return GPIO_PORTA_EOI_V2; | |
136 | } | |
137 | ||
138 | return offset; | |
139 | } | |
140 | ||
141 | static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset) | |
142 | { | |
e1610431 | 143 | if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2) |
a72b8c4a HT |
144 | return gpio_reg_v2_convert(offset); |
145 | ||
146 | return offset; | |
147 | } | |
148 | ||
67809b97 WC |
149 | static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset) |
150 | { | |
0f4630f3 | 151 | struct gpio_chip *gc = &gpio->ports[0].gc; |
67809b97 WC |
152 | void __iomem *reg_base = gpio->regs; |
153 | ||
a72b8c4a | 154 | return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset)); |
67809b97 WC |
155 | } |
156 | ||
157 | static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset, | |
158 | u32 val) | |
159 | { | |
0f4630f3 | 160 | struct gpio_chip *gc = &gpio->ports[0].gc; |
67809b97 WC |
161 | void __iomem *reg_base = gpio->regs; |
162 | ||
a72b8c4a | 163 | gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val); |
67809b97 WC |
164 | } |
165 | ||
62c16234 LW |
166 | static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs) |
167 | { | |
168 | struct dwapb_gpio_port *port; | |
169 | int i; | |
170 | ||
171 | for (i = 0; i < gpio->nr_ports; i++) { | |
172 | port = &gpio->ports[i]; | |
f9f890ba | 173 | if (port->idx == offs / DWAPB_MAX_GPIOS) |
62c16234 LW |
174 | return port; |
175 | } | |
176 | ||
177 | return NULL; | |
178 | } | |
179 | ||
7779b345 JI |
180 | static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs) |
181 | { | |
62c16234 LW |
182 | struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs); |
183 | struct gpio_chip *gc; | |
184 | u32 pol; | |
185 | int val; | |
186 | ||
187 | if (!port) | |
188 | return; | |
189 | gc = &port->gc; | |
7779b345 | 190 | |
62c16234 LW |
191 | pol = dwapb_read(gpio, GPIO_INT_POLARITY); |
192 | /* Just read the current value right out of the data register */ | |
f9f890ba | 193 | val = gc->get(gc, offs % DWAPB_MAX_GPIOS); |
62c16234 LW |
194 | if (val) |
195 | pol &= ~BIT(offs); | |
7779b345 | 196 | else |
62c16234 | 197 | pol |= BIT(offs); |
7779b345 | 198 | |
62c16234 | 199 | dwapb_write(gpio, GPIO_INT_POLARITY, pol); |
7779b345 JI |
200 | } |
201 | ||
3d2613c4 | 202 | static u32 dwapb_do_irq(struct dwapb_gpio *gpio) |
7779b345 | 203 | { |
0ea68393 | 204 | struct gpio_chip *gc = &gpio->ports[0].gc; |
038aa1f0 | 205 | unsigned long irq_status; |
e092bc50 | 206 | irq_hw_number_t hwirq; |
7779b345 | 207 | |
038aa1f0 | 208 | irq_status = dwapb_read(gpio, GPIO_INTSTATUS); |
f9f890ba | 209 | for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) { |
0ea68393 | 210 | int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq); |
038aa1f0 | 211 | u32 irq_type = irq_get_trigger_type(gpio_irq); |
7779b345 JI |
212 | |
213 | generic_handle_irq(gpio_irq); | |
7779b345 | 214 | |
038aa1f0 | 215 | if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
7779b345 JI |
216 | dwapb_toggle_trigger(gpio, hwirq); |
217 | } | |
218 | ||
038aa1f0 | 219 | return irq_status; |
3d2613c4 WC |
220 | } |
221 | ||
bd0b9ac4 | 222 | static void dwapb_irq_handler(struct irq_desc *desc) |
3d2613c4 | 223 | { |
476f8b4c | 224 | struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc); |
3d2613c4 WC |
225 | struct irq_chip *chip = irq_desc_get_chip(desc); |
226 | ||
9b0aef32 | 227 | chained_irq_enter(chip, desc); |
3d2613c4 | 228 | dwapb_do_irq(gpio); |
9b0aef32 | 229 | chained_irq_exit(chip, desc); |
7779b345 JI |
230 | } |
231 | ||
75c1236a SS |
232 | static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id) |
233 | { | |
234 | return IRQ_RETVAL(dwapb_do_irq(dev_id)); | |
235 | } | |
236 | ||
0ea68393 SS |
237 | static void dwapb_irq_ack(struct irq_data *d) |
238 | { | |
239 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
240 | struct dwapb_gpio *gpio = to_dwapb_gpio(gc); | |
241 | u32 val = BIT(irqd_to_hwirq(d)); | |
242 | unsigned long flags; | |
243 | ||
3c938cc5 | 244 | raw_spin_lock_irqsave(&gc->bgpio_lock, flags); |
0ea68393 | 245 | dwapb_write(gpio, GPIO_PORTA_EOI, val); |
3c938cc5 | 246 | raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
0ea68393 SS |
247 | } |
248 | ||
249 | static void dwapb_irq_mask(struct irq_data *d) | |
250 | { | |
251 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
252 | struct dwapb_gpio *gpio = to_dwapb_gpio(gc); | |
cfc2b00e | 253 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
0ea68393 SS |
254 | unsigned long flags; |
255 | u32 val; | |
256 | ||
3c938cc5 | 257 | raw_spin_lock_irqsave(&gc->bgpio_lock, flags); |
cfc2b00e | 258 | val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq); |
0ea68393 | 259 | dwapb_write(gpio, GPIO_INTMASK, val); |
3c938cc5 | 260 | raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
cfc2b00e GU |
261 | |
262 | gpiochip_disable_irq(gc, hwirq); | |
0ea68393 SS |
263 | } |
264 | ||
265 | static void dwapb_irq_unmask(struct irq_data *d) | |
266 | { | |
267 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
268 | struct dwapb_gpio *gpio = to_dwapb_gpio(gc); | |
cfc2b00e | 269 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
0ea68393 SS |
270 | unsigned long flags; |
271 | u32 val; | |
272 | ||
cfc2b00e GU |
273 | gpiochip_enable_irq(gc, hwirq); |
274 | ||
3c938cc5 | 275 | raw_spin_lock_irqsave(&gc->bgpio_lock, flags); |
cfc2b00e | 276 | val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq); |
0ea68393 | 277 | dwapb_write(gpio, GPIO_INTMASK, val); |
3c938cc5 | 278 | raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
0ea68393 SS |
279 | } |
280 | ||
7779b345 JI |
281 | static void dwapb_irq_enable(struct irq_data *d) |
282 | { | |
0ea68393 SS |
283 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
284 | struct dwapb_gpio *gpio = to_dwapb_gpio(gc); | |
1cc3542c | 285 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
7779b345 JI |
286 | unsigned long flags; |
287 | u32 val; | |
288 | ||
3c938cc5 | 289 | raw_spin_lock_irqsave(&gc->bgpio_lock, flags); |
1cc3542c | 290 | val = dwapb_read(gpio, GPIO_INTEN) | BIT(hwirq); |
67809b97 | 291 | dwapb_write(gpio, GPIO_INTEN, val); |
1cc3542c | 292 | val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq); |
293 | dwapb_write(gpio, GPIO_INTMASK, val); | |
3c938cc5 | 294 | raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
7779b345 JI |
295 | } |
296 | ||
297 | static void dwapb_irq_disable(struct irq_data *d) | |
298 | { | |
0ea68393 SS |
299 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
300 | struct dwapb_gpio *gpio = to_dwapb_gpio(gc); | |
1cc3542c | 301 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
7779b345 JI |
302 | unsigned long flags; |
303 | u32 val; | |
304 | ||
3c938cc5 | 305 | raw_spin_lock_irqsave(&gc->bgpio_lock, flags); |
1cc3542c | 306 | val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq); |
307 | dwapb_write(gpio, GPIO_INTMASK, val); | |
308 | val = dwapb_read(gpio, GPIO_INTEN) & ~BIT(hwirq); | |
67809b97 | 309 | dwapb_write(gpio, GPIO_INTEN, val); |
3c938cc5 | 310 | raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
7779b345 JI |
311 | } |
312 | ||
7779b345 JI |
313 | static int dwapb_irq_set_type(struct irq_data *d, u32 type) |
314 | { | |
0ea68393 SS |
315 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
316 | struct dwapb_gpio *gpio = to_dwapb_gpio(gc); | |
e092bc50 | 317 | irq_hw_number_t bit = irqd_to_hwirq(d); |
7779b345 JI |
318 | unsigned long level, polarity, flags; |
319 | ||
3c938cc5 | 320 | raw_spin_lock_irqsave(&gc->bgpio_lock, flags); |
67809b97 WC |
321 | level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); |
322 | polarity = dwapb_read(gpio, GPIO_INT_POLARITY); | |
7779b345 JI |
323 | |
324 | switch (type) { | |
325 | case IRQ_TYPE_EDGE_BOTH: | |
326 | level |= BIT(bit); | |
327 | dwapb_toggle_trigger(gpio, bit); | |
328 | break; | |
329 | case IRQ_TYPE_EDGE_RISING: | |
330 | level |= BIT(bit); | |
331 | polarity |= BIT(bit); | |
332 | break; | |
333 | case IRQ_TYPE_EDGE_FALLING: | |
334 | level |= BIT(bit); | |
335 | polarity &= ~BIT(bit); | |
336 | break; | |
337 | case IRQ_TYPE_LEVEL_HIGH: | |
338 | level &= ~BIT(bit); | |
339 | polarity |= BIT(bit); | |
340 | break; | |
341 | case IRQ_TYPE_LEVEL_LOW: | |
342 | level &= ~BIT(bit); | |
343 | polarity &= ~BIT(bit); | |
344 | break; | |
345 | } | |
346 | ||
0ea68393 SS |
347 | if (type & IRQ_TYPE_LEVEL_MASK) |
348 | irq_set_handler_locked(d, handle_level_irq); | |
349 | else if (type & IRQ_TYPE_EDGE_BOTH) | |
350 | irq_set_handler_locked(d, handle_edge_irq); | |
6a2f4b7d | 351 | |
67809b97 | 352 | dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level); |
edadced2 XC |
353 | if (type != IRQ_TYPE_EDGE_BOTH) |
354 | dwapb_write(gpio, GPIO_INT_POLARITY, polarity); | |
3c938cc5 | 355 | raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
7779b345 JI |
356 | |
357 | return 0; | |
358 | } | |
359 | ||
6437c7ba HT |
360 | #ifdef CONFIG_PM_SLEEP |
361 | static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable) | |
362 | { | |
3fe37204 JH |
363 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
364 | struct dwapb_gpio *gpio = to_dwapb_gpio(gc); | |
6437c7ba | 365 | struct dwapb_context *ctx = gpio->ports[0].ctx; |
e092bc50 | 366 | irq_hw_number_t bit = irqd_to_hwirq(d); |
6437c7ba HT |
367 | |
368 | if (enable) | |
e092bc50 | 369 | ctx->wake_en |= BIT(bit); |
6437c7ba | 370 | else |
e092bc50 | 371 | ctx->wake_en &= ~BIT(bit); |
6437c7ba HT |
372 | |
373 | return 0; | |
374 | } | |
cfc2b00e GU |
375 | #else |
376 | #define dwapb_irq_set_wake NULL | |
6437c7ba HT |
377 | #endif |
378 | ||
cfc2b00e GU |
379 | static const struct irq_chip dwapb_irq_chip = { |
380 | .name = DWAPB_DRIVER_NAME, | |
381 | .irq_ack = dwapb_irq_ack, | |
382 | .irq_mask = dwapb_irq_mask, | |
383 | .irq_unmask = dwapb_irq_unmask, | |
384 | .irq_set_type = dwapb_irq_set_type, | |
385 | .irq_enable = dwapb_irq_enable, | |
386 | .irq_disable = dwapb_irq_disable, | |
387 | .irq_set_wake = dwapb_irq_set_wake, | |
388 | .flags = IRQCHIP_IMMUTABLE, | |
389 | GPIOCHIP_IRQ_RESOURCE_HELPERS, | |
390 | }; | |
391 | ||
5d60d9ef WC |
392 | static int dwapb_gpio_set_debounce(struct gpio_chip *gc, |
393 | unsigned offset, unsigned debounce) | |
394 | { | |
0f4630f3 | 395 | struct dwapb_gpio_port *port = gpiochip_get_data(gc); |
5d60d9ef WC |
396 | struct dwapb_gpio *gpio = port->gpio; |
397 | unsigned long flags, val_deb; | |
d97a1b56 | 398 | unsigned long mask = BIT(offset); |
5d60d9ef | 399 | |
3c938cc5 | 400 | raw_spin_lock_irqsave(&gc->bgpio_lock, flags); |
5d60d9ef WC |
401 | |
402 | val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); | |
403 | if (debounce) | |
48ce8056 | 404 | val_deb |= mask; |
5d60d9ef | 405 | else |
48ce8056 AS |
406 | val_deb &= ~mask; |
407 | dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb); | |
5d60d9ef | 408 | |
3c938cc5 | 409 | raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
5d60d9ef WC |
410 | |
411 | return 0; | |
412 | } | |
413 | ||
2956b5d9 MW |
414 | static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset, |
415 | unsigned long config) | |
416 | { | |
417 | u32 debounce; | |
418 | ||
f34fd6ee ERB |
419 | if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) { |
420 | debounce = pinconf_to_config_argument(config); | |
421 | return dwapb_gpio_set_debounce(gc, offset, debounce); | |
422 | } | |
2956b5d9 | 423 | |
f34fd6ee | 424 | return gpiochip_generic_config(gc, offset, config); |
2956b5d9 MW |
425 | } |
426 | ||
0ea68393 SS |
427 | static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq, |
428 | struct dwapb_port_property *pp) | |
429 | { | |
430 | int i; | |
431 | ||
432 | /* Group all available IRQs into an array of parental IRQs. */ | |
433 | for (i = 0; i < pp->ngpio; ++i) { | |
434 | if (!pp->irq[i]) | |
435 | continue; | |
436 | ||
437 | pirq->irq[pirq->nr_irqs++] = pp->irq[i]; | |
438 | } | |
439 | ||
440 | return pirq->nr_irqs ? 0 : -ENOENT; | |
441 | } | |
442 | ||
7779b345 | 443 | static void dwapb_configure_irqs(struct dwapb_gpio *gpio, |
3d2613c4 WC |
444 | struct dwapb_gpio_port *port, |
445 | struct dwapb_port_property *pp) | |
7779b345 | 446 | { |
0ea68393 | 447 | struct dwapb_gpio_port_irqchip *pirq; |
0f4630f3 | 448 | struct gpio_chip *gc = &port->gc; |
0ea68393 SS |
449 | struct gpio_irq_chip *girq; |
450 | int err; | |
7779b345 | 451 | |
0ea68393 SS |
452 | pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL); |
453 | if (!pirq) | |
7779b345 | 454 | return; |
7779b345 | 455 | |
0ea68393 SS |
456 | if (dwapb_convert_irqs(pirq, pp)) { |
457 | dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx); | |
458 | goto err_kfree_pirq; | |
7779b345 JI |
459 | } |
460 | ||
0ea68393 SS |
461 | girq = &gc->irq; |
462 | girq->handler = handle_bad_irq; | |
463 | girq->default_type = IRQ_TYPE_NONE; | |
464 | ||
465 | port->pirq = pirq; | |
7779b345 | 466 | |
c1b291e9 AS |
467 | /* |
468 | * Intel ACPI-based platforms mostly have the DesignWare APB GPIO | |
469 | * IRQ lane shared between several devices. In that case the parental | |
470 | * IRQ has to be handled in the shared way so to be properly delivered | |
471 | * to all the connected devices. | |
472 | */ | |
473 | if (has_acpi_companion(gpio->dev)) { | |
0ea68393 SS |
474 | girq->num_parents = 0; |
475 | girq->parents = NULL; | |
476 | girq->parent_handler = NULL; | |
477 | ||
e6ca26ab | 478 | err = devm_request_irq(gpio->dev, pp->irq[0], |
3d2613c4 | 479 | dwapb_irq_handler_mfd, |
c58220cb | 480 | IRQF_SHARED, DWAPB_DRIVER_NAME, gpio); |
3d2613c4 WC |
481 | if (err) { |
482 | dev_err(gpio->dev, "error requesting IRQ\n"); | |
0ea68393 | 483 | goto err_kfree_pirq; |
3d2613c4 | 484 | } |
c1b291e9 AS |
485 | } else { |
486 | girq->num_parents = pirq->nr_irqs; | |
487 | girq->parents = pirq->irq; | |
488 | girq->parent_handler_data = gpio; | |
489 | girq->parent_handler = dwapb_irq_handler; | |
3d2613c4 | 490 | } |
7779b345 | 491 | |
cfc2b00e | 492 | gpio_irq_chip_set_chip(girq, &dwapb_irq_chip); |
7779b345 | 493 | |
0ea68393 | 494 | return; |
7779b345 | 495 | |
0ea68393 SS |
496 | err_kfree_pirq: |
497 | devm_kfree(gpio->dev, pirq); | |
7779b345 JI |
498 | } |
499 | ||
500 | static int dwapb_gpio_add_port(struct dwapb_gpio *gpio, | |
3d2613c4 | 501 | struct dwapb_port_property *pp, |
7779b345 JI |
502 | unsigned int offs) |
503 | { | |
504 | struct dwapb_gpio_port *port; | |
7779b345 JI |
505 | void __iomem *dat, *set, *dirout; |
506 | int err; | |
507 | ||
7779b345 JI |
508 | port = &gpio->ports[offs]; |
509 | port->gpio = gpio; | |
1e960dbb WC |
510 | port->idx = pp->idx; |
511 | ||
512 | #ifdef CONFIG_PM_SLEEP | |
513 | port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL); | |
514 | if (!port->ctx) | |
515 | return -ENOMEM; | |
516 | #endif | |
7779b345 | 517 | |
1475b629 AS |
518 | dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE; |
519 | set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE; | |
520 | dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE; | |
7779b345 | 521 | |
62c16234 | 522 | /* This registers 32 GPIO lines per port */ |
0f4630f3 | 523 | err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout, |
d97a1b56 | 524 | NULL, 0); |
7779b345 | 525 | if (err) { |
e8159181 JQ |
526 | dev_err(gpio->dev, "failed to init gpio chip for port%d\n", |
527 | port->idx); | |
7779b345 JI |
528 | return err; |
529 | } | |
530 | ||
80f60eba | 531 | port->gc.fwnode = pp->fwnode; |
0f4630f3 LW |
532 | port->gc.ngpio = pp->ngpio; |
533 | port->gc.base = pp->gpio_base; | |
f34fd6ee ERB |
534 | port->gc.request = gpiochip_generic_request; |
535 | port->gc.free = gpiochip_generic_free; | |
7779b345 | 536 | |
5d60d9ef WC |
537 | /* Only port A support debounce */ |
538 | if (pp->idx == 0) | |
2956b5d9 | 539 | port->gc.set_config = dwapb_gpio_set_config; |
f34fd6ee ERB |
540 | else |
541 | port->gc.set_config = gpiochip_generic_config; | |
5d60d9ef | 542 | |
551cb86c AS |
543 | /* Only port A can provide interrupts in all configurations of the IP */ |
544 | if (pp->idx == 0) | |
3d2613c4 | 545 | dwapb_configure_irqs(gpio, port, pp); |
7779b345 | 546 | |
feeaefd3 | 547 | err = devm_gpiochip_add_data(gpio->dev, &port->gc, port); |
494a94e3 | 548 | if (err) { |
e8159181 JQ |
549 | dev_err(gpio->dev, "failed to register gpiochip for port%d\n", |
550 | port->idx); | |
494a94e3 AS |
551 | return err; |
552 | } | |
7779b345 | 553 | |
494a94e3 | 554 | return 0; |
7779b345 JI |
555 | } |
556 | ||
4c2b54f7 AS |
557 | static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode, |
558 | struct dwapb_port_property *pp) | |
559 | { | |
bd56b051 | 560 | int irq, j; |
4c2b54f7 AS |
561 | |
562 | for (j = 0; j < pp->ngpio; j++) { | |
bd56b051 | 563 | if (has_acpi_companion(dev)) |
aa90939d | 564 | irq = platform_get_irq_optional(to_platform_device(dev), j); |
bd56b051 AS |
565 | else |
566 | irq = fwnode_irq_get(fwnode, j); | |
aa90939d AS |
567 | if (irq > 0) |
568 | pp->irq[j] = irq; | |
4c2b54f7 | 569 | } |
4c2b54f7 AS |
570 | } |
571 | ||
572 | static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev) | |
3d2613c4 | 573 | { |
4ba8cfa7 | 574 | struct fwnode_handle *fwnode; |
3d2613c4 WC |
575 | struct dwapb_platform_data *pdata; |
576 | struct dwapb_port_property *pp; | |
577 | int nports; | |
4c2b54f7 | 578 | int i; |
3d2613c4 | 579 | |
4ba8cfa7 | 580 | nports = device_get_child_node_count(dev); |
3d2613c4 WC |
581 | if (nports == 0) |
582 | return ERR_PTR(-ENODEV); | |
583 | ||
da9df93e | 584 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); |
3d2613c4 WC |
585 | if (!pdata) |
586 | return ERR_PTR(-ENOMEM); | |
587 | ||
da9df93e AL |
588 | pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL); |
589 | if (!pdata->properties) | |
3d2613c4 | 590 | return ERR_PTR(-ENOMEM); |
3d2613c4 WC |
591 | |
592 | pdata->nports = nports; | |
593 | ||
594 | i = 0; | |
4ba8cfa7 | 595 | device_for_each_child_node(dev, fwnode) { |
3d2613c4 | 596 | pp = &pdata->properties[i++]; |
4ba8cfa7 | 597 | pp->fwnode = fwnode; |
3d2613c4 | 598 | |
4ba8cfa7 | 599 | if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) || |
3d2613c4 | 600 | pp->idx >= DWAPB_MAX_PORTS) { |
e8159181 JQ |
601 | dev_err(dev, |
602 | "missing/invalid port index for port%d\n", i); | |
bfab7c8f | 603 | fwnode_handle_put(fwnode); |
3d2613c4 WC |
604 | return ERR_PTR(-EINVAL); |
605 | } | |
606 | ||
7569486d SS |
607 | if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) && |
608 | fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) { | |
e8159181 JQ |
609 | dev_info(dev, |
610 | "failed to get number of gpios for port%d\n", | |
611 | i); | |
f9f890ba | 612 | pp->ngpio = DWAPB_MAX_GPIOS; |
3d2613c4 WC |
613 | } |
614 | ||
da069d5d PE |
615 | pp->gpio_base = -1; |
616 | ||
f973be8a AS |
617 | /* For internal use only, new platforms mustn't exercise this */ |
618 | if (is_software_node(fwnode)) | |
619 | fwnode_property_read_u32(fwnode, "gpio-base", &pp->gpio_base); | |
620 | ||
3d2613c4 WC |
621 | /* |
622 | * Only port A can provide interrupts in all configurations of | |
623 | * the IP. | |
624 | */ | |
4c2b54f7 AS |
625 | if (pp->idx == 0) |
626 | dwapb_get_irq(dev, fwnode, pp); | |
3d2613c4 WC |
627 | } |
628 | ||
629 | return pdata; | |
630 | } | |
631 | ||
4731d80f SS |
632 | static void dwapb_assert_reset(void *data) |
633 | { | |
634 | struct dwapb_gpio *gpio = data; | |
635 | ||
636 | reset_control_assert(gpio->rst); | |
637 | } | |
638 | ||
639 | static int dwapb_get_reset(struct dwapb_gpio *gpio) | |
640 | { | |
641 | int err; | |
642 | ||
643 | gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL); | |
7d3615ae DLM |
644 | if (IS_ERR(gpio->rst)) |
645 | return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst), | |
646 | "Cannot get reset descriptor\n"); | |
4731d80f SS |
647 | |
648 | err = reset_control_deassert(gpio->rst); | |
649 | if (err) { | |
650 | dev_err(gpio->dev, "Cannot deassert reset lane\n"); | |
651 | return err; | |
652 | } | |
653 | ||
654 | return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio); | |
655 | } | |
656 | ||
daa3f58d SS |
657 | static void dwapb_disable_clks(void *data) |
658 | { | |
659 | struct dwapb_gpio *gpio = data; | |
660 | ||
661 | clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); | |
662 | } | |
663 | ||
664 | static int dwapb_get_clks(struct dwapb_gpio *gpio) | |
665 | { | |
666 | int err; | |
667 | ||
668 | /* Optional bus and debounce clocks */ | |
669 | gpio->clks[0].id = "bus"; | |
670 | gpio->clks[1].id = "db"; | |
671 | err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS, | |
672 | gpio->clks); | |
77006f6e SS |
673 | if (err) |
674 | return dev_err_probe(gpio->dev, err, | |
675 | "Cannot get APB/Debounce clocks\n"); | |
daa3f58d SS |
676 | |
677 | err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks); | |
678 | if (err) { | |
679 | dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n"); | |
680 | return err; | |
681 | } | |
682 | ||
683 | return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio); | |
684 | } | |
685 | ||
a72b8c4a | 686 | static const struct of_device_id dwapb_of_match[] = { |
e1610431 | 687 | { .compatible = "snps,dw-apb-gpio", .data = (void *)GPIO_REG_OFFSET_V1}, |
a72b8c4a HT |
688 | { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2}, |
689 | { /* Sentinel */ } | |
690 | }; | |
691 | MODULE_DEVICE_TABLE(of, dwapb_of_match); | |
692 | ||
693 | static const struct acpi_device_id dwapb_acpi_match[] = { | |
e1610431 AS |
694 | {"HISI0181", GPIO_REG_OFFSET_V1}, |
695 | {"APMC0D07", GPIO_REG_OFFSET_V1}, | |
a72b8c4a HT |
696 | {"APMC0D81", GPIO_REG_OFFSET_V2}, |
697 | { } | |
698 | }; | |
699 | MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match); | |
700 | ||
7779b345 JI |
701 | static int dwapb_gpio_probe(struct platform_device *pdev) |
702 | { | |
3d2613c4 | 703 | unsigned int i; |
7779b345 | 704 | struct dwapb_gpio *gpio; |
7779b345 | 705 | int err; |
5111c2b6 | 706 | struct dwapb_platform_data *pdata; |
3d2613c4 | 707 | struct device *dev = &pdev->dev; |
7779b345 | 708 | |
5111c2b6 AS |
709 | pdata = dwapb_gpio_get_pdata(dev); |
710 | if (IS_ERR(pdata)) | |
711 | return PTR_ERR(pdata); | |
7779b345 | 712 | |
3d2613c4 | 713 | gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); |
da9df93e AL |
714 | if (!gpio) |
715 | return -ENOMEM; | |
716 | ||
3d2613c4 WC |
717 | gpio->dev = &pdev->dev; |
718 | gpio->nr_ports = pdata->nports; | |
719 | ||
4731d80f SS |
720 | err = dwapb_get_reset(gpio); |
721 | if (err) | |
722 | return err; | |
07901a94 | 723 | |
3d2613c4 | 724 | gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports, |
7779b345 | 725 | sizeof(*gpio->ports), GFP_KERNEL); |
da9df93e AL |
726 | if (!gpio->ports) |
727 | return -ENOMEM; | |
7779b345 | 728 | |
2a7194e9 | 729 | gpio->regs = devm_platform_ioremap_resource(pdev, 0); |
da9df93e AL |
730 | if (IS_ERR(gpio->regs)) |
731 | return PTR_ERR(gpio->regs); | |
7779b345 | 732 | |
daa3f58d SS |
733 | err = dwapb_get_clks(gpio); |
734 | if (err) | |
3ea8094c | 735 | return err; |
e6bf3773 | 736 | |
9826bbe1 | 737 | gpio->flags = (uintptr_t)device_get_match_data(dev); |
a72b8c4a | 738 | |
3d2613c4 WC |
739 | for (i = 0; i < gpio->nr_ports; i++) { |
740 | err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i); | |
7779b345 | 741 | if (err) |
feeaefd3 | 742 | return err; |
7779b345 | 743 | } |
7779b345 | 744 | |
60593df6 LJ |
745 | platform_set_drvdata(pdev, gpio); |
746 | ||
7779b345 JI |
747 | return 0; |
748 | } | |
749 | ||
1e960dbb WC |
750 | #ifdef CONFIG_PM_SLEEP |
751 | static int dwapb_gpio_suspend(struct device *dev) | |
752 | { | |
deb19ac5 | 753 | struct dwapb_gpio *gpio = dev_get_drvdata(dev); |
0f4630f3 | 754 | struct gpio_chip *gc = &gpio->ports[0].gc; |
1e960dbb WC |
755 | unsigned long flags; |
756 | int i; | |
757 | ||
3c938cc5 | 758 | raw_spin_lock_irqsave(&gc->bgpio_lock, flags); |
1e960dbb WC |
759 | for (i = 0; i < gpio->nr_ports; i++) { |
760 | unsigned int offset; | |
761 | unsigned int idx = gpio->ports[i].idx; | |
762 | struct dwapb_context *ctx = gpio->ports[i].ctx; | |
763 | ||
89f99feb | 764 | offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; |
1e960dbb WC |
765 | ctx->dir = dwapb_read(gpio, offset); |
766 | ||
89f99feb | 767 | offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; |
1e960dbb WC |
768 | ctx->data = dwapb_read(gpio, offset); |
769 | ||
89f99feb | 770 | offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; |
1e960dbb WC |
771 | ctx->ext = dwapb_read(gpio, offset); |
772 | ||
773 | /* Only port A can provide interrupts */ | |
774 | if (idx == 0) { | |
775 | ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK); | |
776 | ctx->int_en = dwapb_read(gpio, GPIO_INTEN); | |
777 | ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY); | |
778 | ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); | |
779 | ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); | |
780 | ||
781 | /* Mask out interrupts */ | |
1afbc80c | 782 | dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en); |
1e960dbb WC |
783 | } |
784 | } | |
3c938cc5 | 785 | raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
1e960dbb | 786 | |
5c544c92 | 787 | clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); |
e6bf3773 | 788 | |
1e960dbb WC |
789 | return 0; |
790 | } | |
791 | ||
792 | static int dwapb_gpio_resume(struct device *dev) | |
793 | { | |
deb19ac5 | 794 | struct dwapb_gpio *gpio = dev_get_drvdata(dev); |
0f4630f3 | 795 | struct gpio_chip *gc = &gpio->ports[0].gc; |
1e960dbb | 796 | unsigned long flags; |
5c544c92 | 797 | int i, err; |
1e960dbb | 798 | |
5c544c92 SS |
799 | err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks); |
800 | if (err) { | |
801 | dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n"); | |
802 | return err; | |
803 | } | |
e6bf3773 | 804 | |
3c938cc5 | 805 | raw_spin_lock_irqsave(&gc->bgpio_lock, flags); |
1e960dbb WC |
806 | for (i = 0; i < gpio->nr_ports; i++) { |
807 | unsigned int offset; | |
808 | unsigned int idx = gpio->ports[i].idx; | |
809 | struct dwapb_context *ctx = gpio->ports[i].ctx; | |
810 | ||
89f99feb | 811 | offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; |
1e960dbb WC |
812 | dwapb_write(gpio, offset, ctx->data); |
813 | ||
89f99feb | 814 | offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; |
1e960dbb WC |
815 | dwapb_write(gpio, offset, ctx->dir); |
816 | ||
89f99feb | 817 | offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; |
1e960dbb WC |
818 | dwapb_write(gpio, offset, ctx->ext); |
819 | ||
820 | /* Only port A can provide interrupts */ | |
821 | if (idx == 0) { | |
822 | dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type); | |
823 | dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol); | |
824 | dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb); | |
825 | dwapb_write(gpio, GPIO_INTEN, ctx->int_en); | |
826 | dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask); | |
827 | ||
828 | /* Clear out spurious interrupts */ | |
829 | dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff); | |
830 | } | |
831 | } | |
3c938cc5 | 832 | raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
1e960dbb WC |
833 | |
834 | return 0; | |
835 | } | |
836 | #endif | |
837 | ||
838 | static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend, | |
839 | dwapb_gpio_resume); | |
840 | ||
7779b345 JI |
841 | static struct platform_driver dwapb_gpio_driver = { |
842 | .driver = { | |
c58220cb | 843 | .name = DWAPB_DRIVER_NAME, |
1e960dbb | 844 | .pm = &dwapb_gpio_pm_ops, |
c59042ed AS |
845 | .of_match_table = dwapb_of_match, |
846 | .acpi_match_table = dwapb_acpi_match, | |
7779b345 JI |
847 | }, |
848 | .probe = dwapb_gpio_probe, | |
7779b345 JI |
849 | }; |
850 | ||
851 | module_platform_driver(dwapb_gpio_driver); | |
852 | ||
853 | MODULE_LICENSE("GPL"); | |
854 | MODULE_AUTHOR("Jamie Iles"); | |
855 | MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver"); | |
c58220cb | 856 | MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME); |