Commit | Line | Data |
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7779b345 JI |
1 | /* |
2 | * Copyright (c) 2011 Jamie Iles | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * All enquiries to support@picochip.com | |
9 | */ | |
e6cb3486 | 10 | #include <linux/acpi.h> |
e6bf3773 | 11 | #include <linux/clk.h> |
7779b345 | 12 | #include <linux/err.h> |
e6bf3773 | 13 | #include <linux/gpio/driver.h> |
7779b345 JI |
14 | #include <linux/init.h> |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/ioport.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/irqdomain.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/of_address.h> | |
a72b8c4a | 23 | #include <linux/of_device.h> |
7779b345 JI |
24 | #include <linux/of_irq.h> |
25 | #include <linux/platform_device.h> | |
4ba8cfa7 | 26 | #include <linux/property.h> |
07901a94 | 27 | #include <linux/reset.h> |
7779b345 | 28 | #include <linux/spinlock.h> |
3d2613c4 WC |
29 | #include <linux/platform_data/gpio-dwapb.h> |
30 | #include <linux/slab.h> | |
7779b345 | 31 | |
e6cb3486 JQ |
32 | #include "gpiolib.h" |
33 | ||
7779b345 JI |
34 | #define GPIO_SWPORTA_DR 0x00 |
35 | #define GPIO_SWPORTA_DDR 0x04 | |
36 | #define GPIO_SWPORTB_DR 0x0c | |
37 | #define GPIO_SWPORTB_DDR 0x10 | |
38 | #define GPIO_SWPORTC_DR 0x18 | |
39 | #define GPIO_SWPORTC_DDR 0x1c | |
40 | #define GPIO_SWPORTD_DR 0x24 | |
41 | #define GPIO_SWPORTD_DDR 0x28 | |
42 | #define GPIO_INTEN 0x30 | |
43 | #define GPIO_INTMASK 0x34 | |
44 | #define GPIO_INTTYPE_LEVEL 0x38 | |
45 | #define GPIO_INT_POLARITY 0x3c | |
46 | #define GPIO_INTSTATUS 0x40 | |
5d60d9ef | 47 | #define GPIO_PORTA_DEBOUNCE 0x48 |
7779b345 JI |
48 | #define GPIO_PORTA_EOI 0x4c |
49 | #define GPIO_EXT_PORTA 0x50 | |
50 | #define GPIO_EXT_PORTB 0x54 | |
51 | #define GPIO_EXT_PORTC 0x58 | |
52 | #define GPIO_EXT_PORTD 0x5c | |
53 | ||
54 | #define DWAPB_MAX_PORTS 4 | |
89f99feb LW |
55 | #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */ |
56 | #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */ | |
57 | #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */ | |
7779b345 | 58 | |
a72b8c4a HT |
59 | #define GPIO_REG_OFFSET_V2 1 |
60 | ||
61 | #define GPIO_INTMASK_V2 0x44 | |
62 | #define GPIO_INTTYPE_LEVEL_V2 0x34 | |
63 | #define GPIO_INT_POLARITY_V2 0x38 | |
64 | #define GPIO_INTSTATUS_V2 0x3c | |
65 | #define GPIO_PORTA_EOI_V2 0x40 | |
66 | ||
7779b345 JI |
67 | struct dwapb_gpio; |
68 | ||
1e960dbb WC |
69 | #ifdef CONFIG_PM_SLEEP |
70 | /* Store GPIO context across system-wide suspend/resume transitions */ | |
71 | struct dwapb_context { | |
72 | u32 data; | |
73 | u32 dir; | |
74 | u32 ext; | |
75 | u32 int_en; | |
76 | u32 int_mask; | |
77 | u32 int_type; | |
78 | u32 int_pol; | |
79 | u32 int_deb; | |
6437c7ba | 80 | u32 wake_en; |
1e960dbb WC |
81 | }; |
82 | #endif | |
83 | ||
7779b345 | 84 | struct dwapb_gpio_port { |
0f4630f3 | 85 | struct gpio_chip gc; |
7779b345 JI |
86 | bool is_registered; |
87 | struct dwapb_gpio *gpio; | |
1e960dbb WC |
88 | #ifdef CONFIG_PM_SLEEP |
89 | struct dwapb_context *ctx; | |
90 | #endif | |
91 | unsigned int idx; | |
7779b345 JI |
92 | }; |
93 | ||
94 | struct dwapb_gpio { | |
95 | struct device *dev; | |
96 | void __iomem *regs; | |
97 | struct dwapb_gpio_port *ports; | |
98 | unsigned int nr_ports; | |
99 | struct irq_domain *domain; | |
a72b8c4a | 100 | unsigned int flags; |
07901a94 | 101 | struct reset_control *rst; |
e6bf3773 | 102 | struct clk *clk; |
7779b345 JI |
103 | }; |
104 | ||
a72b8c4a HT |
105 | static inline u32 gpio_reg_v2_convert(unsigned int offset) |
106 | { | |
107 | switch (offset) { | |
108 | case GPIO_INTMASK: | |
109 | return GPIO_INTMASK_V2; | |
110 | case GPIO_INTTYPE_LEVEL: | |
111 | return GPIO_INTTYPE_LEVEL_V2; | |
112 | case GPIO_INT_POLARITY: | |
113 | return GPIO_INT_POLARITY_V2; | |
114 | case GPIO_INTSTATUS: | |
115 | return GPIO_INTSTATUS_V2; | |
116 | case GPIO_PORTA_EOI: | |
117 | return GPIO_PORTA_EOI_V2; | |
118 | } | |
119 | ||
120 | return offset; | |
121 | } | |
122 | ||
123 | static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset) | |
124 | { | |
125 | if (gpio->flags & GPIO_REG_OFFSET_V2) | |
126 | return gpio_reg_v2_convert(offset); | |
127 | ||
128 | return offset; | |
129 | } | |
130 | ||
67809b97 WC |
131 | static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset) |
132 | { | |
0f4630f3 | 133 | struct gpio_chip *gc = &gpio->ports[0].gc; |
67809b97 WC |
134 | void __iomem *reg_base = gpio->regs; |
135 | ||
a72b8c4a | 136 | return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset)); |
67809b97 WC |
137 | } |
138 | ||
139 | static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset, | |
140 | u32 val) | |
141 | { | |
0f4630f3 | 142 | struct gpio_chip *gc = &gpio->ports[0].gc; |
67809b97 WC |
143 | void __iomem *reg_base = gpio->regs; |
144 | ||
a72b8c4a | 145 | gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val); |
67809b97 WC |
146 | } |
147 | ||
7779b345 JI |
148 | static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset) |
149 | { | |
0f4630f3 | 150 | struct dwapb_gpio_port *port = gpiochip_get_data(gc); |
7779b345 JI |
151 | struct dwapb_gpio *gpio = port->gpio; |
152 | ||
153 | return irq_find_mapping(gpio->domain, offset); | |
154 | } | |
155 | ||
62c16234 LW |
156 | static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs) |
157 | { | |
158 | struct dwapb_gpio_port *port; | |
159 | int i; | |
160 | ||
161 | for (i = 0; i < gpio->nr_ports; i++) { | |
162 | port = &gpio->ports[i]; | |
163 | if (port->idx == offs / 32) | |
164 | return port; | |
165 | } | |
166 | ||
167 | return NULL; | |
168 | } | |
169 | ||
7779b345 JI |
170 | static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs) |
171 | { | |
62c16234 LW |
172 | struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs); |
173 | struct gpio_chip *gc; | |
174 | u32 pol; | |
175 | int val; | |
176 | ||
177 | if (!port) | |
178 | return; | |
179 | gc = &port->gc; | |
7779b345 | 180 | |
62c16234 LW |
181 | pol = dwapb_read(gpio, GPIO_INT_POLARITY); |
182 | /* Just read the current value right out of the data register */ | |
183 | val = gc->get(gc, offs % 32); | |
184 | if (val) | |
185 | pol &= ~BIT(offs); | |
7779b345 | 186 | else |
62c16234 | 187 | pol |= BIT(offs); |
7779b345 | 188 | |
62c16234 | 189 | dwapb_write(gpio, GPIO_INT_POLARITY, pol); |
7779b345 JI |
190 | } |
191 | ||
3d2613c4 | 192 | static u32 dwapb_do_irq(struct dwapb_gpio *gpio) |
7779b345 | 193 | { |
5664aa1c | 194 | u32 irq_status = dwapb_read(gpio, GPIO_INTSTATUS); |
3d2613c4 | 195 | u32 ret = irq_status; |
7779b345 JI |
196 | |
197 | while (irq_status) { | |
198 | int hwirq = fls(irq_status) - 1; | |
199 | int gpio_irq = irq_find_mapping(gpio->domain, hwirq); | |
200 | ||
201 | generic_handle_irq(gpio_irq); | |
202 | irq_status &= ~BIT(hwirq); | |
203 | ||
204 | if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK) | |
205 | == IRQ_TYPE_EDGE_BOTH) | |
206 | dwapb_toggle_trigger(gpio, hwirq); | |
207 | } | |
208 | ||
3d2613c4 WC |
209 | return ret; |
210 | } | |
211 | ||
bd0b9ac4 | 212 | static void dwapb_irq_handler(struct irq_desc *desc) |
3d2613c4 | 213 | { |
476f8b4c | 214 | struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc); |
3d2613c4 WC |
215 | struct irq_chip *chip = irq_desc_get_chip(desc); |
216 | ||
217 | dwapb_do_irq(gpio); | |
218 | ||
7779b345 JI |
219 | if (chip->irq_eoi) |
220 | chip->irq_eoi(irq_desc_get_irq_data(desc)); | |
221 | } | |
222 | ||
223 | static void dwapb_irq_enable(struct irq_data *d) | |
224 | { | |
225 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
226 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 227 | struct gpio_chip *gc = &gpio->ports[0].gc; |
7779b345 JI |
228 | unsigned long flags; |
229 | u32 val; | |
230 | ||
0f4630f3 | 231 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
67809b97 | 232 | val = dwapb_read(gpio, GPIO_INTEN); |
7779b345 | 233 | val |= BIT(d->hwirq); |
67809b97 | 234 | dwapb_write(gpio, GPIO_INTEN, val); |
0f4630f3 | 235 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
7779b345 JI |
236 | } |
237 | ||
238 | static void dwapb_irq_disable(struct irq_data *d) | |
239 | { | |
240 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
241 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 242 | struct gpio_chip *gc = &gpio->ports[0].gc; |
7779b345 JI |
243 | unsigned long flags; |
244 | u32 val; | |
245 | ||
0f4630f3 | 246 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
67809b97 | 247 | val = dwapb_read(gpio, GPIO_INTEN); |
7779b345 | 248 | val &= ~BIT(d->hwirq); |
67809b97 | 249 | dwapb_write(gpio, GPIO_INTEN, val); |
0f4630f3 | 250 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
7779b345 JI |
251 | } |
252 | ||
57ef0428 | 253 | static int dwapb_irq_reqres(struct irq_data *d) |
7779b345 JI |
254 | { |
255 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
256 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 257 | struct gpio_chip *gc = &gpio->ports[0].gc; |
10ed3539 | 258 | int ret; |
7779b345 | 259 | |
10ed3539 AS |
260 | ret = gpiochip_lock_as_irq(gc, irqd_to_hwirq(d)); |
261 | if (ret) { | |
7779b345 JI |
262 | dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n", |
263 | irqd_to_hwirq(d)); | |
10ed3539 | 264 | return ret; |
57ef0428 | 265 | } |
7779b345 JI |
266 | return 0; |
267 | } | |
268 | ||
57ef0428 | 269 | static void dwapb_irq_relres(struct irq_data *d) |
7779b345 JI |
270 | { |
271 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
272 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 273 | struct gpio_chip *gc = &gpio->ports[0].gc; |
7779b345 | 274 | |
0f4630f3 | 275 | gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d)); |
7779b345 JI |
276 | } |
277 | ||
278 | static int dwapb_irq_set_type(struct irq_data *d, u32 type) | |
279 | { | |
280 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
281 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 282 | struct gpio_chip *gc = &gpio->ports[0].gc; |
7779b345 JI |
283 | int bit = d->hwirq; |
284 | unsigned long level, polarity, flags; | |
285 | ||
286 | if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | | |
287 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | |
288 | return -EINVAL; | |
289 | ||
0f4630f3 | 290 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
67809b97 WC |
291 | level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); |
292 | polarity = dwapb_read(gpio, GPIO_INT_POLARITY); | |
7779b345 JI |
293 | |
294 | switch (type) { | |
295 | case IRQ_TYPE_EDGE_BOTH: | |
296 | level |= BIT(bit); | |
297 | dwapb_toggle_trigger(gpio, bit); | |
298 | break; | |
299 | case IRQ_TYPE_EDGE_RISING: | |
300 | level |= BIT(bit); | |
301 | polarity |= BIT(bit); | |
302 | break; | |
303 | case IRQ_TYPE_EDGE_FALLING: | |
304 | level |= BIT(bit); | |
305 | polarity &= ~BIT(bit); | |
306 | break; | |
307 | case IRQ_TYPE_LEVEL_HIGH: | |
308 | level &= ~BIT(bit); | |
309 | polarity |= BIT(bit); | |
310 | break; | |
311 | case IRQ_TYPE_LEVEL_LOW: | |
312 | level &= ~BIT(bit); | |
313 | polarity &= ~BIT(bit); | |
314 | break; | |
315 | } | |
316 | ||
6a2f4b7d SAS |
317 | irq_setup_alt_chip(d, type); |
318 | ||
67809b97 | 319 | dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level); |
edadced2 XC |
320 | if (type != IRQ_TYPE_EDGE_BOTH) |
321 | dwapb_write(gpio, GPIO_INT_POLARITY, polarity); | |
0f4630f3 | 322 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
7779b345 JI |
323 | |
324 | return 0; | |
325 | } | |
326 | ||
6437c7ba HT |
327 | #ifdef CONFIG_PM_SLEEP |
328 | static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable) | |
329 | { | |
330 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
331 | struct dwapb_gpio *gpio = igc->private; | |
332 | struct dwapb_context *ctx = gpio->ports[0].ctx; | |
333 | ||
334 | if (enable) | |
335 | ctx->wake_en |= BIT(d->hwirq); | |
336 | else | |
337 | ctx->wake_en &= ~BIT(d->hwirq); | |
338 | ||
339 | return 0; | |
340 | } | |
341 | #endif | |
342 | ||
5d60d9ef WC |
343 | static int dwapb_gpio_set_debounce(struct gpio_chip *gc, |
344 | unsigned offset, unsigned debounce) | |
345 | { | |
0f4630f3 | 346 | struct dwapb_gpio_port *port = gpiochip_get_data(gc); |
5d60d9ef WC |
347 | struct dwapb_gpio *gpio = port->gpio; |
348 | unsigned long flags, val_deb; | |
d97a1b56 | 349 | unsigned long mask = BIT(offset); |
5d60d9ef | 350 | |
0f4630f3 | 351 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
5d60d9ef WC |
352 | |
353 | val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); | |
354 | if (debounce) | |
355 | dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask); | |
356 | else | |
357 | dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask); | |
358 | ||
0f4630f3 | 359 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
5d60d9ef WC |
360 | |
361 | return 0; | |
362 | } | |
363 | ||
2956b5d9 MW |
364 | static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset, |
365 | unsigned long config) | |
366 | { | |
367 | u32 debounce; | |
368 | ||
369 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
370 | return -ENOTSUPP; | |
371 | ||
372 | debounce = pinconf_to_config_argument(config); | |
373 | return dwapb_gpio_set_debounce(gc, offset, debounce); | |
374 | } | |
375 | ||
3d2613c4 WC |
376 | static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id) |
377 | { | |
378 | u32 worked; | |
379 | struct dwapb_gpio *gpio = dev_id; | |
380 | ||
381 | worked = dwapb_do_irq(gpio); | |
382 | ||
383 | return worked ? IRQ_HANDLED : IRQ_NONE; | |
384 | } | |
385 | ||
7779b345 | 386 | static void dwapb_configure_irqs(struct dwapb_gpio *gpio, |
3d2613c4 WC |
387 | struct dwapb_gpio_port *port, |
388 | struct dwapb_port_property *pp) | |
7779b345 | 389 | { |
0f4630f3 | 390 | struct gpio_chip *gc = &port->gc; |
4ba8cfa7 | 391 | struct fwnode_handle *fwnode = pp->fwnode; |
3d2613c4 | 392 | struct irq_chip_generic *irq_gc = NULL; |
7779b345 JI |
393 | unsigned int hwirq, ngpio = gc->ngpio; |
394 | struct irq_chip_type *ct; | |
3d2613c4 | 395 | int err, i; |
7779b345 | 396 | |
4ba8cfa7 JQ |
397 | gpio->domain = irq_domain_create_linear(fwnode, ngpio, |
398 | &irq_generic_chip_ops, gpio); | |
7779b345 JI |
399 | if (!gpio->domain) |
400 | return; | |
401 | ||
6a2f4b7d | 402 | err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2, |
7779b345 JI |
403 | "gpio-dwapb", handle_level_irq, |
404 | IRQ_NOREQUEST, 0, | |
405 | IRQ_GC_INIT_NESTED_LOCK); | |
406 | if (err) { | |
407 | dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n"); | |
408 | irq_domain_remove(gpio->domain); | |
409 | gpio->domain = NULL; | |
410 | return; | |
411 | } | |
412 | ||
413 | irq_gc = irq_get_domain_generic_chip(gpio->domain, 0); | |
414 | if (!irq_gc) { | |
415 | irq_domain_remove(gpio->domain); | |
416 | gpio->domain = NULL; | |
417 | return; | |
418 | } | |
419 | ||
420 | irq_gc->reg_base = gpio->regs; | |
421 | irq_gc->private = gpio; | |
422 | ||
6a2f4b7d SAS |
423 | for (i = 0; i < 2; i++) { |
424 | ct = &irq_gc->chip_types[i]; | |
425 | ct->chip.irq_ack = irq_gc_ack_set_bit; | |
426 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
427 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
428 | ct->chip.irq_set_type = dwapb_irq_set_type; | |
429 | ct->chip.irq_enable = dwapb_irq_enable; | |
430 | ct->chip.irq_disable = dwapb_irq_disable; | |
431 | ct->chip.irq_request_resources = dwapb_irq_reqres; | |
432 | ct->chip.irq_release_resources = dwapb_irq_relres; | |
6437c7ba HT |
433 | #ifdef CONFIG_PM_SLEEP |
434 | ct->chip.irq_set_wake = dwapb_irq_set_wake; | |
435 | #endif | |
a72b8c4a HT |
436 | ct->regs.ack = gpio_reg_convert(gpio, GPIO_PORTA_EOI); |
437 | ct->regs.mask = gpio_reg_convert(gpio, GPIO_INTMASK); | |
6a2f4b7d SAS |
438 | ct->type = IRQ_TYPE_LEVEL_MASK; |
439 | } | |
440 | ||
441 | irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; | |
442 | irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; | |
443 | irq_gc->chip_types[1].handler = handle_edge_irq; | |
7779b345 | 444 | |
3d2613c4 | 445 | if (!pp->irq_shared) { |
e6ca26ab PE |
446 | int i; |
447 | ||
448 | for (i = 0; i < pp->ngpio; i++) { | |
da069d5d | 449 | if (pp->irq[i] >= 0) |
e6ca26ab PE |
450 | irq_set_chained_handler_and_data(pp->irq[i], |
451 | dwapb_irq_handler, gpio); | |
452 | } | |
3d2613c4 WC |
453 | } else { |
454 | /* | |
455 | * Request a shared IRQ since where MFD would have devices | |
456 | * using the same irq pin | |
457 | */ | |
e6ca26ab | 458 | err = devm_request_irq(gpio->dev, pp->irq[0], |
3d2613c4 WC |
459 | dwapb_irq_handler_mfd, |
460 | IRQF_SHARED, "gpio-dwapb-mfd", gpio); | |
461 | if (err) { | |
462 | dev_err(gpio->dev, "error requesting IRQ\n"); | |
463 | irq_domain_remove(gpio->domain); | |
464 | gpio->domain = NULL; | |
465 | return; | |
466 | } | |
467 | } | |
7779b345 JI |
468 | |
469 | for (hwirq = 0 ; hwirq < ngpio ; hwirq++) | |
470 | irq_create_mapping(gpio->domain, hwirq); | |
471 | ||
0f4630f3 | 472 | port->gc.to_irq = dwapb_gpio_to_irq; |
7779b345 JI |
473 | } |
474 | ||
475 | static void dwapb_irq_teardown(struct dwapb_gpio *gpio) | |
476 | { | |
477 | struct dwapb_gpio_port *port = &gpio->ports[0]; | |
0f4630f3 | 478 | struct gpio_chip *gc = &port->gc; |
7779b345 JI |
479 | unsigned int ngpio = gc->ngpio; |
480 | irq_hw_number_t hwirq; | |
481 | ||
482 | if (!gpio->domain) | |
483 | return; | |
484 | ||
485 | for (hwirq = 0 ; hwirq < ngpio ; hwirq++) | |
486 | irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq)); | |
487 | ||
488 | irq_domain_remove(gpio->domain); | |
489 | gpio->domain = NULL; | |
490 | } | |
491 | ||
492 | static int dwapb_gpio_add_port(struct dwapb_gpio *gpio, | |
3d2613c4 | 493 | struct dwapb_port_property *pp, |
7779b345 JI |
494 | unsigned int offs) |
495 | { | |
496 | struct dwapb_gpio_port *port; | |
7779b345 JI |
497 | void __iomem *dat, *set, *dirout; |
498 | int err; | |
499 | ||
7779b345 JI |
500 | port = &gpio->ports[offs]; |
501 | port->gpio = gpio; | |
1e960dbb WC |
502 | port->idx = pp->idx; |
503 | ||
504 | #ifdef CONFIG_PM_SLEEP | |
505 | port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL); | |
506 | if (!port->ctx) | |
507 | return -ENOMEM; | |
508 | #endif | |
7779b345 | 509 | |
89f99feb LW |
510 | dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_STRIDE); |
511 | set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_STRIDE); | |
7779b345 | 512 | dirout = gpio->regs + GPIO_SWPORTA_DDR + |
89f99feb | 513 | (pp->idx * GPIO_SWPORT_DDR_STRIDE); |
7779b345 | 514 | |
62c16234 | 515 | /* This registers 32 GPIO lines per port */ |
0f4630f3 | 516 | err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout, |
d97a1b56 | 517 | NULL, 0); |
7779b345 | 518 | if (err) { |
e8159181 JQ |
519 | dev_err(gpio->dev, "failed to init gpio chip for port%d\n", |
520 | port->idx); | |
7779b345 JI |
521 | return err; |
522 | } | |
523 | ||
3d2613c4 | 524 | #ifdef CONFIG_OF_GPIO |
4ba8cfa7 | 525 | port->gc.of_node = to_of_node(pp->fwnode); |
3d2613c4 | 526 | #endif |
0f4630f3 LW |
527 | port->gc.ngpio = pp->ngpio; |
528 | port->gc.base = pp->gpio_base; | |
7779b345 | 529 | |
5d60d9ef WC |
530 | /* Only port A support debounce */ |
531 | if (pp->idx == 0) | |
2956b5d9 | 532 | port->gc.set_config = dwapb_gpio_set_config; |
5d60d9ef | 533 | |
e6ca26ab | 534 | if (pp->has_irq) |
3d2613c4 | 535 | dwapb_configure_irqs(gpio, port, pp); |
7779b345 | 536 | |
0f4630f3 | 537 | err = gpiochip_add_data(&port->gc, port); |
7779b345 | 538 | if (err) |
e8159181 JQ |
539 | dev_err(gpio->dev, "failed to register gpiochip for port%d\n", |
540 | port->idx); | |
7779b345 JI |
541 | else |
542 | port->is_registered = true; | |
543 | ||
e6cb3486 | 544 | /* Add GPIO-signaled ACPI event support */ |
e6ca26ab | 545 | if (pp->has_irq) |
e6cb3486 JQ |
546 | acpi_gpiochip_request_interrupts(&port->gc); |
547 | ||
7779b345 JI |
548 | return err; |
549 | } | |
550 | ||
551 | static void dwapb_gpio_unregister(struct dwapb_gpio *gpio) | |
552 | { | |
553 | unsigned int m; | |
554 | ||
555 | for (m = 0; m < gpio->nr_ports; ++m) | |
556 | if (gpio->ports[m].is_registered) | |
0f4630f3 | 557 | gpiochip_remove(&gpio->ports[m].gc); |
7779b345 JI |
558 | } |
559 | ||
3d2613c4 | 560 | static struct dwapb_platform_data * |
4ba8cfa7 | 561 | dwapb_gpio_get_pdata(struct device *dev) |
3d2613c4 | 562 | { |
4ba8cfa7 | 563 | struct fwnode_handle *fwnode; |
3d2613c4 WC |
564 | struct dwapb_platform_data *pdata; |
565 | struct dwapb_port_property *pp; | |
566 | int nports; | |
da069d5d | 567 | int i, j; |
3d2613c4 | 568 | |
4ba8cfa7 | 569 | nports = device_get_child_node_count(dev); |
3d2613c4 WC |
570 | if (nports == 0) |
571 | return ERR_PTR(-ENODEV); | |
572 | ||
da9df93e | 573 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); |
3d2613c4 WC |
574 | if (!pdata) |
575 | return ERR_PTR(-ENOMEM); | |
576 | ||
da9df93e AL |
577 | pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL); |
578 | if (!pdata->properties) | |
3d2613c4 | 579 | return ERR_PTR(-ENOMEM); |
3d2613c4 WC |
580 | |
581 | pdata->nports = nports; | |
582 | ||
583 | i = 0; | |
4ba8cfa7 | 584 | device_for_each_child_node(dev, fwnode) { |
da069d5d PE |
585 | struct device_node *np = NULL; |
586 | ||
3d2613c4 | 587 | pp = &pdata->properties[i++]; |
4ba8cfa7 | 588 | pp->fwnode = fwnode; |
3d2613c4 | 589 | |
4ba8cfa7 | 590 | if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) || |
3d2613c4 | 591 | pp->idx >= DWAPB_MAX_PORTS) { |
e8159181 JQ |
592 | dev_err(dev, |
593 | "missing/invalid port index for port%d\n", i); | |
bfab7c8f | 594 | fwnode_handle_put(fwnode); |
3d2613c4 WC |
595 | return ERR_PTR(-EINVAL); |
596 | } | |
597 | ||
4ba8cfa7 | 598 | if (fwnode_property_read_u32(fwnode, "snps,nr-gpios", |
3d2613c4 | 599 | &pp->ngpio)) { |
e8159181 JQ |
600 | dev_info(dev, |
601 | "failed to get number of gpios for port%d\n", | |
602 | i); | |
3d2613c4 WC |
603 | pp->ngpio = 32; |
604 | } | |
605 | ||
da069d5d PE |
606 | pp->irq_shared = false; |
607 | pp->gpio_base = -1; | |
608 | ||
3d2613c4 WC |
609 | /* |
610 | * Only port A can provide interrupts in all configurations of | |
611 | * the IP. | |
612 | */ | |
da069d5d PE |
613 | if (pp->idx != 0) |
614 | continue; | |
e6ca26ab | 615 | |
da069d5d PE |
616 | if (dev->of_node && fwnode_property_read_bool(fwnode, |
617 | "interrupt-controller")) { | |
618 | np = to_of_node(fwnode); | |
3d2613c4 WC |
619 | } |
620 | ||
da069d5d PE |
621 | for (j = 0; j < pp->ngpio; j++) { |
622 | pp->irq[j] = -ENXIO; | |
e6ca26ab | 623 | |
da069d5d PE |
624 | if (np) |
625 | pp->irq[j] = of_irq_get(np, j); | |
626 | else if (has_acpi_companion(dev)) | |
e6ca26ab | 627 | pp->irq[j] = platform_get_irq(to_platform_device(dev), j); |
da069d5d PE |
628 | |
629 | if (pp->irq[j] >= 0) | |
630 | pp->has_irq = true; | |
e6ca26ab | 631 | } |
e6cb3486 | 632 | |
da069d5d PE |
633 | if (!pp->has_irq) |
634 | dev_warn(dev, "no irq for port%d\n", pp->idx); | |
3d2613c4 WC |
635 | } |
636 | ||
637 | return pdata; | |
638 | } | |
639 | ||
a72b8c4a HT |
640 | static const struct of_device_id dwapb_of_match[] = { |
641 | { .compatible = "snps,dw-apb-gpio", .data = (void *)0}, | |
642 | { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2}, | |
643 | { /* Sentinel */ } | |
644 | }; | |
645 | MODULE_DEVICE_TABLE(of, dwapb_of_match); | |
646 | ||
647 | static const struct acpi_device_id dwapb_acpi_match[] = { | |
648 | {"HISI0181", 0}, | |
649 | {"APMC0D07", 0}, | |
650 | {"APMC0D81", GPIO_REG_OFFSET_V2}, | |
651 | { } | |
652 | }; | |
653 | MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match); | |
654 | ||
7779b345 JI |
655 | static int dwapb_gpio_probe(struct platform_device *pdev) |
656 | { | |
3d2613c4 | 657 | unsigned int i; |
7779b345 JI |
658 | struct resource *res; |
659 | struct dwapb_gpio *gpio; | |
7779b345 | 660 | int err; |
3d2613c4 WC |
661 | struct device *dev = &pdev->dev; |
662 | struct dwapb_platform_data *pdata = dev_get_platdata(dev); | |
3d2613c4 | 663 | |
da9df93e | 664 | if (!pdata) { |
4ba8cfa7 | 665 | pdata = dwapb_gpio_get_pdata(dev); |
3d2613c4 WC |
666 | if (IS_ERR(pdata)) |
667 | return PTR_ERR(pdata); | |
668 | } | |
7779b345 | 669 | |
da9df93e AL |
670 | if (!pdata->nports) |
671 | return -ENODEV; | |
7779b345 | 672 | |
3d2613c4 | 673 | gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); |
da9df93e AL |
674 | if (!gpio) |
675 | return -ENOMEM; | |
676 | ||
3d2613c4 WC |
677 | gpio->dev = &pdev->dev; |
678 | gpio->nr_ports = pdata->nports; | |
679 | ||
07901a94 AT |
680 | gpio->rst = devm_reset_control_get_optional_shared(dev, NULL); |
681 | if (IS_ERR(gpio->rst)) | |
682 | return PTR_ERR(gpio->rst); | |
683 | ||
684 | reset_control_deassert(gpio->rst); | |
685 | ||
3d2613c4 | 686 | gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports, |
7779b345 | 687 | sizeof(*gpio->ports), GFP_KERNEL); |
da9df93e AL |
688 | if (!gpio->ports) |
689 | return -ENOMEM; | |
7779b345 JI |
690 | |
691 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
692 | gpio->regs = devm_ioremap_resource(&pdev->dev, res); | |
da9df93e AL |
693 | if (IS_ERR(gpio->regs)) |
694 | return PTR_ERR(gpio->regs); | |
7779b345 | 695 | |
e6bf3773 PE |
696 | /* Optional bus clock */ |
697 | gpio->clk = devm_clk_get(&pdev->dev, "bus"); | |
698 | if (!IS_ERR(gpio->clk)) { | |
699 | err = clk_prepare_enable(gpio->clk); | |
700 | if (err) { | |
701 | dev_info(&pdev->dev, "Cannot enable clock\n"); | |
702 | return err; | |
703 | } | |
704 | } | |
705 | ||
a72b8c4a HT |
706 | gpio->flags = 0; |
707 | if (dev->of_node) { | |
7114b7ba | 708 | gpio->flags = (uintptr_t)of_device_get_match_data(dev); |
a72b8c4a HT |
709 | } else if (has_acpi_companion(dev)) { |
710 | const struct acpi_device_id *acpi_id; | |
711 | ||
712 | acpi_id = acpi_match_device(dwapb_acpi_match, dev); | |
713 | if (acpi_id) { | |
714 | if (acpi_id->driver_data) | |
715 | gpio->flags = acpi_id->driver_data; | |
716 | } | |
717 | } | |
718 | ||
3d2613c4 WC |
719 | for (i = 0; i < gpio->nr_ports; i++) { |
720 | err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i); | |
7779b345 JI |
721 | if (err) |
722 | goto out_unregister; | |
723 | } | |
724 | platform_set_drvdata(pdev, gpio); | |
725 | ||
da9df93e | 726 | return 0; |
7779b345 JI |
727 | |
728 | out_unregister: | |
729 | dwapb_gpio_unregister(gpio); | |
730 | dwapb_irq_teardown(gpio); | |
a618cf48 | 731 | clk_disable_unprepare(gpio->clk); |
7779b345 | 732 | |
7779b345 JI |
733 | return err; |
734 | } | |
735 | ||
736 | static int dwapb_gpio_remove(struct platform_device *pdev) | |
737 | { | |
738 | struct dwapb_gpio *gpio = platform_get_drvdata(pdev); | |
739 | ||
740 | dwapb_gpio_unregister(gpio); | |
741 | dwapb_irq_teardown(gpio); | |
07901a94 | 742 | reset_control_assert(gpio->rst); |
e6bf3773 | 743 | clk_disable_unprepare(gpio->clk); |
7779b345 JI |
744 | |
745 | return 0; | |
746 | } | |
747 | ||
1e960dbb WC |
748 | #ifdef CONFIG_PM_SLEEP |
749 | static int dwapb_gpio_suspend(struct device *dev) | |
750 | { | |
751 | struct platform_device *pdev = to_platform_device(dev); | |
752 | struct dwapb_gpio *gpio = platform_get_drvdata(pdev); | |
0f4630f3 | 753 | struct gpio_chip *gc = &gpio->ports[0].gc; |
1e960dbb WC |
754 | unsigned long flags; |
755 | int i; | |
756 | ||
0f4630f3 | 757 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
1e960dbb WC |
758 | for (i = 0; i < gpio->nr_ports; i++) { |
759 | unsigned int offset; | |
760 | unsigned int idx = gpio->ports[i].idx; | |
761 | struct dwapb_context *ctx = gpio->ports[i].ctx; | |
762 | ||
58a3b92d | 763 | BUG_ON(!ctx); |
1e960dbb | 764 | |
89f99feb | 765 | offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; |
1e960dbb WC |
766 | ctx->dir = dwapb_read(gpio, offset); |
767 | ||
89f99feb | 768 | offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; |
1e960dbb WC |
769 | ctx->data = dwapb_read(gpio, offset); |
770 | ||
89f99feb | 771 | offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; |
1e960dbb WC |
772 | ctx->ext = dwapb_read(gpio, offset); |
773 | ||
774 | /* Only port A can provide interrupts */ | |
775 | if (idx == 0) { | |
776 | ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK); | |
777 | ctx->int_en = dwapb_read(gpio, GPIO_INTEN); | |
778 | ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY); | |
779 | ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); | |
780 | ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); | |
781 | ||
782 | /* Mask out interrupts */ | |
6437c7ba HT |
783 | dwapb_write(gpio, GPIO_INTMASK, |
784 | 0xffffffff & ~ctx->wake_en); | |
1e960dbb WC |
785 | } |
786 | } | |
0f4630f3 | 787 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
1e960dbb | 788 | |
e6bf3773 PE |
789 | clk_disable_unprepare(gpio->clk); |
790 | ||
1e960dbb WC |
791 | return 0; |
792 | } | |
793 | ||
794 | static int dwapb_gpio_resume(struct device *dev) | |
795 | { | |
796 | struct platform_device *pdev = to_platform_device(dev); | |
797 | struct dwapb_gpio *gpio = platform_get_drvdata(pdev); | |
0f4630f3 | 798 | struct gpio_chip *gc = &gpio->ports[0].gc; |
1e960dbb WC |
799 | unsigned long flags; |
800 | int i; | |
801 | ||
e6bf3773 PE |
802 | if (!IS_ERR(gpio->clk)) |
803 | clk_prepare_enable(gpio->clk); | |
804 | ||
0f4630f3 | 805 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
1e960dbb WC |
806 | for (i = 0; i < gpio->nr_ports; i++) { |
807 | unsigned int offset; | |
808 | unsigned int idx = gpio->ports[i].idx; | |
809 | struct dwapb_context *ctx = gpio->ports[i].ctx; | |
810 | ||
58a3b92d | 811 | BUG_ON(!ctx); |
1e960dbb | 812 | |
89f99feb | 813 | offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; |
1e960dbb WC |
814 | dwapb_write(gpio, offset, ctx->data); |
815 | ||
89f99feb | 816 | offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; |
1e960dbb WC |
817 | dwapb_write(gpio, offset, ctx->dir); |
818 | ||
89f99feb | 819 | offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; |
1e960dbb WC |
820 | dwapb_write(gpio, offset, ctx->ext); |
821 | ||
822 | /* Only port A can provide interrupts */ | |
823 | if (idx == 0) { | |
824 | dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type); | |
825 | dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol); | |
826 | dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb); | |
827 | dwapb_write(gpio, GPIO_INTEN, ctx->int_en); | |
828 | dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask); | |
829 | ||
830 | /* Clear out spurious interrupts */ | |
831 | dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff); | |
832 | } | |
833 | } | |
0f4630f3 | 834 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
1e960dbb WC |
835 | |
836 | return 0; | |
837 | } | |
838 | #endif | |
839 | ||
840 | static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend, | |
841 | dwapb_gpio_resume); | |
842 | ||
7779b345 JI |
843 | static struct platform_driver dwapb_gpio_driver = { |
844 | .driver = { | |
845 | .name = "gpio-dwapb", | |
1e960dbb | 846 | .pm = &dwapb_gpio_pm_ops, |
7779b345 | 847 | .of_match_table = of_match_ptr(dwapb_of_match), |
e6cb3486 | 848 | .acpi_match_table = ACPI_PTR(dwapb_acpi_match), |
7779b345 JI |
849 | }, |
850 | .probe = dwapb_gpio_probe, | |
851 | .remove = dwapb_gpio_remove, | |
852 | }; | |
853 | ||
854 | module_platform_driver(dwapb_gpio_driver); | |
855 | ||
856 | MODULE_LICENSE("GPL"); | |
857 | MODULE_AUTHOR("Jamie Iles"); | |
858 | MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver"); |