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6732127f DB |
1 | /* |
2 | * Driver for the Diolan DLN-2 USB-GPIO adapter | |
3 | * | |
4 | * Copyright (c) 2014 Intel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation, version 2. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/types.h> | |
15 | #include <linux/irqdomain.h> | |
16 | #include <linux/irq.h> | |
17 | #include <linux/irqchip/chained_irq.h> | |
18 | #include <linux/gpio.h> | |
19 | #include <linux/gpio/driver.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/mfd/dln2.h> | |
22 | ||
23 | #define DLN2_GPIO_ID 0x01 | |
24 | ||
25 | #define DLN2_GPIO_GET_PIN_COUNT DLN2_CMD(0x01, DLN2_GPIO_ID) | |
26 | #define DLN2_GPIO_SET_DEBOUNCE DLN2_CMD(0x04, DLN2_GPIO_ID) | |
27 | #define DLN2_GPIO_GET_DEBOUNCE DLN2_CMD(0x05, DLN2_GPIO_ID) | |
28 | #define DLN2_GPIO_PORT_GET_VAL DLN2_CMD(0x06, DLN2_GPIO_ID) | |
29 | #define DLN2_GPIO_PIN_GET_VAL DLN2_CMD(0x0B, DLN2_GPIO_ID) | |
30 | #define DLN2_GPIO_PIN_SET_OUT_VAL DLN2_CMD(0x0C, DLN2_GPIO_ID) | |
31 | #define DLN2_GPIO_PIN_GET_OUT_VAL DLN2_CMD(0x0D, DLN2_GPIO_ID) | |
32 | #define DLN2_GPIO_CONDITION_MET_EV DLN2_CMD(0x0F, DLN2_GPIO_ID) | |
33 | #define DLN2_GPIO_PIN_ENABLE DLN2_CMD(0x10, DLN2_GPIO_ID) | |
34 | #define DLN2_GPIO_PIN_DISABLE DLN2_CMD(0x11, DLN2_GPIO_ID) | |
35 | #define DLN2_GPIO_PIN_SET_DIRECTION DLN2_CMD(0x13, DLN2_GPIO_ID) | |
36 | #define DLN2_GPIO_PIN_GET_DIRECTION DLN2_CMD(0x14, DLN2_GPIO_ID) | |
37 | #define DLN2_GPIO_PIN_SET_EVENT_CFG DLN2_CMD(0x1E, DLN2_GPIO_ID) | |
38 | #define DLN2_GPIO_PIN_GET_EVENT_CFG DLN2_CMD(0x1F, DLN2_GPIO_ID) | |
39 | ||
40 | #define DLN2_GPIO_EVENT_NONE 0 | |
41 | #define DLN2_GPIO_EVENT_CHANGE 1 | |
42 | #define DLN2_GPIO_EVENT_LVL_HIGH 2 | |
43 | #define DLN2_GPIO_EVENT_LVL_LOW 3 | |
44 | #define DLN2_GPIO_EVENT_CHANGE_RISING 0x11 | |
45 | #define DLN2_GPIO_EVENT_CHANGE_FALLING 0x21 | |
46 | #define DLN2_GPIO_EVENT_MASK 0x0F | |
47 | ||
48 | #define DLN2_GPIO_MAX_PINS 32 | |
49 | ||
6732127f DB |
50 | struct dln2_gpio { |
51 | struct platform_device *pdev; | |
52 | struct gpio_chip gpio; | |
53 | ||
54 | /* | |
55 | * Cache pin direction to save us one transfer, since the hardware has | |
56 | * separate commands to read the in and out values. | |
57 | */ | |
58 | DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS); | |
59 | ||
0acb0e71 OP |
60 | /* active IRQs - not synced to hardware */ |
61 | DECLARE_BITMAP(unmasked_irqs, DLN2_GPIO_MAX_PINS); | |
96b932b8 OP |
62 | /* active IRQS - synced to hardware */ |
63 | DECLARE_BITMAP(enabled_irqs, DLN2_GPIO_MAX_PINS); | |
64 | int irq_type[DLN2_GPIO_MAX_PINS]; | |
65 | struct mutex irq_lock; | |
6732127f DB |
66 | }; |
67 | ||
68 | struct dln2_gpio_pin { | |
69 | __le16 pin; | |
70 | }; | |
71 | ||
72 | struct dln2_gpio_pin_val { | |
73 | __le16 pin __packed; | |
74 | u8 value; | |
75 | }; | |
76 | ||
77 | static int dln2_gpio_get_pin_count(struct platform_device *pdev) | |
78 | { | |
79 | int ret; | |
80 | __le16 count; | |
81 | int len = sizeof(count); | |
82 | ||
83 | ret = dln2_transfer_rx(pdev, DLN2_GPIO_GET_PIN_COUNT, &count, &len); | |
84 | if (ret < 0) | |
85 | return ret; | |
86 | if (len < sizeof(count)) | |
87 | return -EPROTO; | |
88 | ||
89 | return le16_to_cpu(count); | |
90 | } | |
91 | ||
92 | static int dln2_gpio_pin_cmd(struct dln2_gpio *dln2, int cmd, unsigned pin) | |
93 | { | |
94 | struct dln2_gpio_pin req = { | |
95 | .pin = cpu_to_le16(pin), | |
96 | }; | |
97 | ||
98 | return dln2_transfer_tx(dln2->pdev, cmd, &req, sizeof(req)); | |
99 | } | |
100 | ||
101 | static int dln2_gpio_pin_val(struct dln2_gpio *dln2, int cmd, unsigned int pin) | |
102 | { | |
103 | int ret; | |
104 | struct dln2_gpio_pin req = { | |
105 | .pin = cpu_to_le16(pin), | |
106 | }; | |
107 | struct dln2_gpio_pin_val rsp; | |
108 | int len = sizeof(rsp); | |
109 | ||
110 | ret = dln2_transfer(dln2->pdev, cmd, &req, sizeof(req), &rsp, &len); | |
111 | if (ret < 0) | |
112 | return ret; | |
113 | if (len < sizeof(rsp) || req.pin != rsp.pin) | |
114 | return -EPROTO; | |
115 | ||
116 | return rsp.value; | |
117 | } | |
118 | ||
119 | static int dln2_gpio_pin_get_in_val(struct dln2_gpio *dln2, unsigned int pin) | |
120 | { | |
121 | int ret; | |
122 | ||
123 | ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_VAL, pin); | |
124 | if (ret < 0) | |
125 | return ret; | |
126 | return !!ret; | |
127 | } | |
128 | ||
129 | static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin) | |
130 | { | |
131 | int ret; | |
132 | ||
133 | ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_OUT_VAL, pin); | |
134 | if (ret < 0) | |
135 | return ret; | |
136 | return !!ret; | |
137 | } | |
138 | ||
5afb287a AL |
139 | static int dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2, |
140 | unsigned int pin, int value) | |
6732127f DB |
141 | { |
142 | struct dln2_gpio_pin_val req = { | |
143 | .pin = cpu_to_le16(pin), | |
144 | .value = value, | |
145 | }; | |
146 | ||
5afb287a AL |
147 | return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req, |
148 | sizeof(req)); | |
6732127f DB |
149 | } |
150 | ||
151 | #define DLN2_GPIO_DIRECTION_IN 0 | |
152 | #define DLN2_GPIO_DIRECTION_OUT 1 | |
153 | ||
154 | static int dln2_gpio_request(struct gpio_chip *chip, unsigned offset) | |
155 | { | |
1880657a | 156 | struct dln2_gpio *dln2 = gpiochip_get_data(chip); |
6732127f DB |
157 | struct dln2_gpio_pin req = { |
158 | .pin = cpu_to_le16(offset), | |
159 | }; | |
160 | struct dln2_gpio_pin_val rsp; | |
161 | int len = sizeof(rsp); | |
162 | int ret; | |
163 | ||
164 | ret = dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_ENABLE, offset); | |
165 | if (ret < 0) | |
166 | return ret; | |
167 | ||
168 | /* cache the pin direction */ | |
169 | ret = dln2_transfer(dln2->pdev, DLN2_GPIO_PIN_GET_DIRECTION, | |
170 | &req, sizeof(req), &rsp, &len); | |
171 | if (ret < 0) | |
172 | return ret; | |
173 | if (len < sizeof(rsp) || req.pin != rsp.pin) { | |
174 | ret = -EPROTO; | |
175 | goto out_disable; | |
176 | } | |
177 | ||
178 | switch (rsp.value) { | |
179 | case DLN2_GPIO_DIRECTION_IN: | |
180 | clear_bit(offset, dln2->output_enabled); | |
181 | return 0; | |
182 | case DLN2_GPIO_DIRECTION_OUT: | |
183 | set_bit(offset, dln2->output_enabled); | |
184 | return 0; | |
185 | default: | |
186 | ret = -EPROTO; | |
187 | goto out_disable; | |
188 | } | |
189 | ||
190 | out_disable: | |
191 | dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset); | |
192 | return ret; | |
193 | } | |
194 | ||
195 | static void dln2_gpio_free(struct gpio_chip *chip, unsigned offset) | |
196 | { | |
1880657a | 197 | struct dln2_gpio *dln2 = gpiochip_get_data(chip); |
6732127f DB |
198 | |
199 | dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset); | |
200 | } | |
201 | ||
202 | static int dln2_gpio_get_direction(struct gpio_chip *chip, unsigned offset) | |
203 | { | |
1880657a | 204 | struct dln2_gpio *dln2 = gpiochip_get_data(chip); |
6732127f DB |
205 | |
206 | if (test_bit(offset, dln2->output_enabled)) | |
207 | return GPIOF_DIR_OUT; | |
208 | ||
209 | return GPIOF_DIR_IN; | |
210 | } | |
211 | ||
212 | static int dln2_gpio_get(struct gpio_chip *chip, unsigned int offset) | |
213 | { | |
1880657a | 214 | struct dln2_gpio *dln2 = gpiochip_get_data(chip); |
6732127f DB |
215 | int dir; |
216 | ||
217 | dir = dln2_gpio_get_direction(chip, offset); | |
218 | if (dir < 0) | |
219 | return dir; | |
220 | ||
221 | if (dir == GPIOF_DIR_IN) | |
222 | return dln2_gpio_pin_get_in_val(dln2, offset); | |
223 | ||
224 | return dln2_gpio_pin_get_out_val(dln2, offset); | |
225 | } | |
226 | ||
227 | static void dln2_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
228 | { | |
1880657a | 229 | struct dln2_gpio *dln2 = gpiochip_get_data(chip); |
6732127f DB |
230 | |
231 | dln2_gpio_pin_set_out_val(dln2, offset, value); | |
232 | } | |
233 | ||
234 | static int dln2_gpio_set_direction(struct gpio_chip *chip, unsigned offset, | |
235 | unsigned dir) | |
236 | { | |
1880657a | 237 | struct dln2_gpio *dln2 = gpiochip_get_data(chip); |
6732127f DB |
238 | struct dln2_gpio_pin_val req = { |
239 | .pin = cpu_to_le16(offset), | |
240 | .value = dir, | |
241 | }; | |
242 | int ret; | |
243 | ||
244 | ret = dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_DIRECTION, | |
245 | &req, sizeof(req)); | |
246 | if (ret < 0) | |
247 | return ret; | |
248 | ||
249 | if (dir == DLN2_GPIO_DIRECTION_OUT) | |
250 | set_bit(offset, dln2->output_enabled); | |
251 | else | |
252 | clear_bit(offset, dln2->output_enabled); | |
253 | ||
254 | return ret; | |
255 | } | |
256 | ||
257 | static int dln2_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
258 | { | |
259 | return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_IN); | |
260 | } | |
261 | ||
262 | static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |
263 | int value) | |
264 | { | |
1880657a | 265 | struct dln2_gpio *dln2 = gpiochip_get_data(chip); |
5afb287a AL |
266 | int ret; |
267 | ||
268 | ret = dln2_gpio_pin_set_out_val(dln2, offset, value); | |
269 | if (ret < 0) | |
270 | return ret; | |
271 | ||
6732127f DB |
272 | return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT); |
273 | } | |
274 | ||
2956b5d9 MW |
275 | static int dln2_gpio_set_config(struct gpio_chip *chip, unsigned offset, |
276 | unsigned long config) | |
6732127f | 277 | { |
1880657a | 278 | struct dln2_gpio *dln2 = gpiochip_get_data(chip); |
2956b5d9 | 279 | __le32 duration; |
6732127f | 280 | |
2956b5d9 MW |
281 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) |
282 | return -ENOTSUPP; | |
283 | ||
284 | duration = cpu_to_le32(pinconf_to_config_argument(config)); | |
6732127f DB |
285 | return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_SET_DEBOUNCE, |
286 | &duration, sizeof(duration)); | |
287 | } | |
288 | ||
289 | static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin, | |
290 | unsigned type, unsigned period) | |
291 | { | |
292 | struct { | |
293 | __le16 pin; | |
294 | u8 type; | |
295 | __le16 period; | |
296 | } __packed req = { | |
297 | .pin = cpu_to_le16(pin), | |
298 | .type = type, | |
299 | .period = cpu_to_le16(period), | |
300 | }; | |
301 | ||
302 | return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_EVENT_CFG, | |
303 | &req, sizeof(req)); | |
304 | } | |
305 | ||
0acb0e71 | 306 | static void dln2_irq_unmask(struct irq_data *irqd) |
6732127f DB |
307 | { |
308 | struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); | |
1880657a | 309 | struct dln2_gpio *dln2 = gpiochip_get_data(gc); |
6732127f DB |
310 | int pin = irqd_to_hwirq(irqd); |
311 | ||
0acb0e71 | 312 | set_bit(pin, dln2->unmasked_irqs); |
6732127f DB |
313 | } |
314 | ||
315 | static void dln2_irq_mask(struct irq_data *irqd) | |
316 | { | |
317 | struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); | |
1880657a | 318 | struct dln2_gpio *dln2 = gpiochip_get_data(gc); |
6732127f DB |
319 | int pin = irqd_to_hwirq(irqd); |
320 | ||
0acb0e71 | 321 | clear_bit(pin, dln2->unmasked_irqs); |
6732127f DB |
322 | } |
323 | ||
324 | static int dln2_irq_set_type(struct irq_data *irqd, unsigned type) | |
325 | { | |
326 | struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); | |
1880657a | 327 | struct dln2_gpio *dln2 = gpiochip_get_data(gc); |
6732127f DB |
328 | int pin = irqd_to_hwirq(irqd); |
329 | ||
330 | switch (type) { | |
331 | case IRQ_TYPE_LEVEL_HIGH: | |
96b932b8 | 332 | dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_HIGH; |
6732127f DB |
333 | break; |
334 | case IRQ_TYPE_LEVEL_LOW: | |
96b932b8 | 335 | dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_LOW; |
6732127f DB |
336 | break; |
337 | case IRQ_TYPE_EDGE_BOTH: | |
96b932b8 | 338 | dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE; |
6732127f DB |
339 | break; |
340 | case IRQ_TYPE_EDGE_RISING: | |
96b932b8 | 341 | dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_RISING; |
6732127f DB |
342 | break; |
343 | case IRQ_TYPE_EDGE_FALLING: | |
96b932b8 | 344 | dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_FALLING; |
6732127f DB |
345 | break; |
346 | default: | |
347 | return -EINVAL; | |
348 | } | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
96b932b8 OP |
353 | static void dln2_irq_bus_lock(struct irq_data *irqd) |
354 | { | |
355 | struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); | |
1880657a | 356 | struct dln2_gpio *dln2 = gpiochip_get_data(gc); |
96b932b8 OP |
357 | |
358 | mutex_lock(&dln2->irq_lock); | |
359 | } | |
360 | ||
361 | static void dln2_irq_bus_unlock(struct irq_data *irqd) | |
362 | { | |
363 | struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); | |
1880657a | 364 | struct dln2_gpio *dln2 = gpiochip_get_data(gc); |
96b932b8 OP |
365 | int pin = irqd_to_hwirq(irqd); |
366 | int enabled, unmasked; | |
367 | unsigned type; | |
368 | int ret; | |
369 | ||
370 | enabled = test_bit(pin, dln2->enabled_irqs); | |
371 | unmasked = test_bit(pin, dln2->unmasked_irqs); | |
372 | ||
373 | if (enabled != unmasked) { | |
374 | if (unmasked) { | |
375 | type = dln2->irq_type[pin] & DLN2_GPIO_EVENT_MASK; | |
376 | set_bit(pin, dln2->enabled_irqs); | |
377 | } else { | |
378 | type = DLN2_GPIO_EVENT_NONE; | |
379 | clear_bit(pin, dln2->enabled_irqs); | |
380 | } | |
381 | ||
382 | ret = dln2_gpio_set_event_cfg(dln2, pin, type, 0); | |
383 | if (ret) | |
58383c78 | 384 | dev_err(dln2->gpio.parent, "failed to set event\n"); |
96b932b8 OP |
385 | } |
386 | ||
387 | mutex_unlock(&dln2->irq_lock); | |
388 | } | |
389 | ||
6732127f DB |
390 | static struct irq_chip dln2_gpio_irqchip = { |
391 | .name = "dln2-irq", | |
6732127f DB |
392 | .irq_mask = dln2_irq_mask, |
393 | .irq_unmask = dln2_irq_unmask, | |
394 | .irq_set_type = dln2_irq_set_type, | |
96b932b8 OP |
395 | .irq_bus_lock = dln2_irq_bus_lock, |
396 | .irq_bus_sync_unlock = dln2_irq_bus_unlock, | |
6732127f DB |
397 | }; |
398 | ||
399 | static void dln2_gpio_event(struct platform_device *pdev, u16 echo, | |
400 | const void *data, int len) | |
401 | { | |
402 | int pin, irq; | |
1fbb29c2 | 403 | |
6732127f DB |
404 | const struct { |
405 | __le16 count; | |
406 | __u8 type; | |
407 | __le16 pin; | |
408 | __u8 value; | |
409 | } __packed *event = data; | |
410 | struct dln2_gpio *dln2 = platform_get_drvdata(pdev); | |
411 | ||
412 | if (len < sizeof(*event)) { | |
58383c78 | 413 | dev_err(dln2->gpio.parent, "short event message\n"); |
6732127f DB |
414 | return; |
415 | } | |
416 | ||
417 | pin = le16_to_cpu(event->pin); | |
418 | if (pin >= dln2->gpio.ngpio) { | |
58383c78 | 419 | dev_err(dln2->gpio.parent, "out of bounds pin %d\n", pin); |
6732127f DB |
420 | return; |
421 | } | |
422 | ||
f0fbe7bc | 423 | irq = irq_find_mapping(dln2->gpio.irq.domain, pin); |
6732127f | 424 | if (!irq) { |
58383c78 | 425 | dev_err(dln2->gpio.parent, "pin %d not mapped to IRQ\n", pin); |
6732127f DB |
426 | return; |
427 | } | |
428 | ||
96b932b8 | 429 | switch (dln2->irq_type[pin]) { |
6732127f DB |
430 | case DLN2_GPIO_EVENT_CHANGE_RISING: |
431 | if (event->value) | |
432 | generic_handle_irq(irq); | |
433 | break; | |
434 | case DLN2_GPIO_EVENT_CHANGE_FALLING: | |
435 | if (!event->value) | |
436 | generic_handle_irq(irq); | |
437 | break; | |
438 | default: | |
439 | generic_handle_irq(irq); | |
440 | } | |
441 | } | |
442 | ||
443 | static int dln2_gpio_probe(struct platform_device *pdev) | |
444 | { | |
445 | struct dln2_gpio *dln2; | |
446 | struct device *dev = &pdev->dev; | |
447 | int pins; | |
96b932b8 | 448 | int ret; |
6732127f DB |
449 | |
450 | pins = dln2_gpio_get_pin_count(pdev); | |
451 | if (pins < 0) { | |
452 | dev_err(dev, "failed to get pin count: %d\n", pins); | |
453 | return pins; | |
454 | } | |
455 | if (pins > DLN2_GPIO_MAX_PINS) { | |
456 | pins = DLN2_GPIO_MAX_PINS; | |
457 | dev_warn(dev, "clamping pins to %d\n", DLN2_GPIO_MAX_PINS); | |
458 | } | |
459 | ||
460 | dln2 = devm_kzalloc(&pdev->dev, sizeof(*dln2), GFP_KERNEL); | |
461 | if (!dln2) | |
462 | return -ENOMEM; | |
463 | ||
96b932b8 | 464 | mutex_init(&dln2->irq_lock); |
6732127f DB |
465 | |
466 | dln2->pdev = pdev; | |
467 | ||
468 | dln2->gpio.label = "dln2"; | |
58383c78 | 469 | dln2->gpio.parent = dev; |
6732127f DB |
470 | dln2->gpio.owner = THIS_MODULE; |
471 | dln2->gpio.base = -1; | |
472 | dln2->gpio.ngpio = pins; | |
6732127f | 473 | dln2->gpio.can_sleep = true; |
6732127f DB |
474 | dln2->gpio.set = dln2_gpio_set; |
475 | dln2->gpio.get = dln2_gpio_get; | |
476 | dln2->gpio.request = dln2_gpio_request; | |
477 | dln2->gpio.free = dln2_gpio_free; | |
478 | dln2->gpio.get_direction = dln2_gpio_get_direction; | |
479 | dln2->gpio.direction_input = dln2_gpio_direction_input; | |
480 | dln2->gpio.direction_output = dln2_gpio_direction_output; | |
2956b5d9 | 481 | dln2->gpio.set_config = dln2_gpio_set_config; |
6732127f DB |
482 | |
483 | platform_set_drvdata(pdev, dln2); | |
484 | ||
1ab79a6a | 485 | ret = devm_gpiochip_add_data(dev, &dln2->gpio, dln2); |
6732127f DB |
486 | if (ret < 0) { |
487 | dev_err(dev, "failed to add gpio chip: %d\n", ret); | |
1ab79a6a | 488 | return ret; |
6732127f DB |
489 | } |
490 | ||
491 | ret = gpiochip_irqchip_add(&dln2->gpio, &dln2_gpio_irqchip, 0, | |
492 | handle_simple_irq, IRQ_TYPE_NONE); | |
493 | if (ret < 0) { | |
494 | dev_err(dev, "failed to add irq chip: %d\n", ret); | |
1ab79a6a | 495 | return ret; |
6732127f DB |
496 | } |
497 | ||
498 | ret = dln2_register_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV, | |
499 | dln2_gpio_event); | |
500 | if (ret) { | |
501 | dev_err(dev, "failed to register event cb: %d\n", ret); | |
1ab79a6a | 502 | return ret; |
6732127f DB |
503 | } |
504 | ||
505 | return 0; | |
6732127f DB |
506 | } |
507 | ||
508 | static int dln2_gpio_remove(struct platform_device *pdev) | |
509 | { | |
6732127f | 510 | dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV); |
6732127f DB |
511 | |
512 | return 0; | |
513 | } | |
514 | ||
515 | static struct platform_driver dln2_gpio_driver = { | |
516 | .driver.name = "dln2-gpio", | |
517 | .probe = dln2_gpio_probe, | |
518 | .remove = dln2_gpio_remove, | |
519 | }; | |
520 | ||
521 | module_platform_driver(dln2_gpio_driver); | |
522 | ||
523 | MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com"); | |
524 | MODULE_DESCRIPTION("Driver for the Diolan DLN2 GPIO interface"); | |
525 | MODULE_LICENSE("GPL v2"); | |
526 | MODULE_ALIAS("platform:dln2-gpio"); |