[linux-2.6-block.git] / drivers / gpio / gpio-davinci.c

/*
 * TI DaVinci GPIO Support
 *
 * Copyright (c) 2006-2007 David Brownell
 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */
#include <linux/gpio.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/platform_data/gpio-davinci.h>
#include <linux/irqchip/chained_irq.h>

struct davinci_gpio_regs {
	u32	dir;
	u32	out_data;
	u32	set_data;
	u32	clr_data;
	u32	in_data;
	u32	set_rising;
	u32	clr_rising;
	u32	set_falling;
	u32	clr_falling;
	u32	intstat;
};

typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);

#define BINTEN	0x8 /* GPIO Interrupt Per-Bank Enable Register */

#define chip2controller(chip)	\
	container_of(chip, struct davinci_gpio_controller, chip)

static void __iomem *gpio_base;

static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio)
{
	void __iomem *ptr;

	if (gpio < 32 * 1)
		ptr = gpio_base + 0x10;
	else if (gpio < 32 * 2)
		ptr = gpio_base + 0x38;
	else if (gpio < 32 * 3)
		ptr = gpio_base + 0x60;
	else if (gpio < 32 * 4)
		ptr = gpio_base + 0x88;
	else if (gpio < 32 * 5)
		ptr = gpio_base + 0xb0;
	else
		ptr = NULL;
	return ptr;
}

static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
{
	struct davinci_gpio_regs __iomem *g;

	g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);

	return g;
}

static int davinci_gpio_irq_setup(struct platform_device *pdev);

/*--------------------------------------------------------------------------*/

/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
static inline int __davinci_direction(struct gpio_chip *chip,
			unsigned offset, bool out, int value)
{
	struct davinci_gpio_controller *d = chip2controller(chip);
	struct davinci_gpio_regs __iomem *g = d->regs;
	unsigned long flags;
	u32 temp;
	u32 mask = 1 << offset;

	spin_lock_irqsave(&d->lock, flags);
	temp = readl_relaxed(&g->dir);
	if (out) {
		temp &= ~mask;
		writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
	} else {
		temp |= mask;
	}
	writel_relaxed(temp, &g->dir);
	spin_unlock_irqrestore(&d->lock, flags);

	return 0;
}

static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
{
	return __davinci_direction(chip, offset, false, 0);
}

static int
davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
{
	return __davinci_direction(chip, offset, true, value);
}

/*
 * Read the pin's value (works even if it's set up as output);
 * returns zero/nonzero.
 *
 * Note that changes are synched to the GPIO clock, so reading values back
 * right after you've set them may give old values.
 */
static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_gpio_controller *d = chip2controller(chip);
	struct davinci_gpio_regs __iomem *g = d->regs;

	return (1 << offset) & readl_relaxed(&g->in_data);
}

/*
 * Assuming the pin is muxed as a gpio output, set its output value.
 */
static void
davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct davinci_gpio_controller *d = chip2controller(chip);
	struct davinci_gpio_regs __iomem *g = d->regs;

	writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data);
}

static struct davinci_gpio_platform_data *
davinci_gpio_get_pdata(struct platform_device *pdev)
{
	struct device_node *dn = pdev->dev.of_node;
	struct davinci_gpio_platform_data *pdata;
	int ret;
	u32 val;

	if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
		return pdev->dev.platform_data;

	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return NULL;

	ret = of_property_read_u32(dn, "ti,ngpio", &val);
	if (ret)
		goto of_err;

	pdata->ngpio = val;

	ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
	if (ret)
		goto of_err;

	pdata->gpio_unbanked = val;

	return pdata;

of_err:
	dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
	return NULL;
}

static int davinci_gpio_probe(struct platform_device *pdev)
{
	int i, base;
	unsigned ngpio;
	struct davinci_gpio_controller *chips;
	struct davinci_gpio_platform_data *pdata;
	struct davinci_gpio_regs __iomem *regs;
	struct device *dev = &pdev->dev;
	struct resource *res;

	pdata = davinci_gpio_get_pdata(pdev);
	if (!pdata) {
		dev_err(dev, "No platform data found\n");
		return -EINVAL;
	}

	dev->platform_data = pdata;

	/*
	 * The gpio banks conceptually expose a segmented bitmap,
	 * and "ngpio" is one more than the largest zero-based
	 * bit index that's valid.
	 */
	ngpio = pdata->ngpio;
	if (ngpio == 0) {
		dev_err(dev, "How many GPIOs?\n");
		return -EINVAL;
	}

	if (WARN_ON(ARCH_NR_GPIOS < ngpio))
		ngpio = ARCH_NR_GPIOS;

	chips = devm_kzalloc(dev,
			     ngpio * sizeof(struct davinci_gpio_controller),
			     GFP_KERNEL);
	if (!chips) {
		dev_err(dev, "Memory allocation failed\n");
		return -ENOMEM;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(dev, "Invalid memory resource\n");
		return -EBUSY;
	}

	gpio_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(gpio_base))
		return PTR_ERR(gpio_base);

	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
		chips[i].chip.label = "DaVinci";

		chips[i].chip.direction_input = davinci_direction_in;
		chips[i].chip.get = davinci_gpio_get;
		chips[i].chip.direction_output = davinci_direction_out;
		chips[i].chip.set = davinci_gpio_set;

		chips[i].chip.base = base;
		chips[i].chip.ngpio = ngpio - base;
		if (chips[i].chip.ngpio > 32)
			chips[i].chip.ngpio = 32;

#ifdef CONFIG_OF_GPIO
		chips[i].chip.of_node = dev->of_node;
#endif
		spin_lock_init(&chips[i].lock);

		regs = gpio2regs(base);
		chips[i].regs = regs;
		chips[i].set_data = &regs->set_data;
		chips[i].clr_data = &regs->clr_data;
		chips[i].in_data = &regs->in_data;

		gpiochip_add(&chips[i].chip);
	}

	platform_set_drvdata(pdev, chips);
	davinci_gpio_irq_setup(pdev);
	return 0;
}

/*--------------------------------------------------------------------------*/
/*
 * We expect irqs will normally be set up as input pins, but they can also be
 * used as output pins ... which is convenient for testing.
 *
 * NOTE:  The first few GPIOs also have direct INTC hookups in addition
 * to their GPIOBNK0 irq, with a bit less overhead.
 *
 * All those INTC hookups (direct, plus several IRQ banks) can also
 * serve as EDMA event triggers.
 */

static void gpio_irq_disable(struct irq_data *d)
{
	struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
	u32 mask = (u32) irq_data_get_irq_handler_data(d);

	writel_relaxed(mask, &g->clr_falling);
	writel_relaxed(mask, &g->clr_rising);
}

static void gpio_irq_enable(struct irq_data *d)
{
	struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
	u32 mask = (u32) irq_data_get_irq_handler_data(d);
	unsigned status = irqd_get_trigger_type(d);

	status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
	if (!status)
		status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;

	if (status & IRQ_TYPE_EDGE_FALLING)
		writel_relaxed(mask, &g->set_falling);
	if (status & IRQ_TYPE_EDGE_RISING)
		writel_relaxed(mask, &g->set_rising);
}

static int gpio_irq_type(struct irq_data *d, unsigned trigger)
{
	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		return -EINVAL;

	return 0;
}

static struct irq_chip gpio_irqchip = {
	.name		= "GPIO",
	.irq_enable	= gpio_irq_enable,
	.irq_disable	= gpio_irq_disable,
	.irq_set_type	= gpio_irq_type,
	.flags		= IRQCHIP_SET_TYPE_MASKED,
};

static void
gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
	struct davinci_gpio_regs __iomem *g;
	u32 mask = 0xffff;
	struct davinci_gpio_controller *d;

	d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
	g = (struct davinci_gpio_regs __iomem *)d->regs;

	/* we only care about one bank */
	if (irq & 1)
		mask <<= 16;

	/* temporarily mask (level sensitive) parent IRQ */
	chained_irq_enter(irq_desc_get_chip(desc), desc);
	while (1) {
		u32		status;
		int		bit;

		/* ack any irqs */
		status = readl_relaxed(&g->intstat) & mask;
		if (!status)
			break;
		writel_relaxed(status, &g->intstat);

		/* now demux them to the right lowlevel handler */

		while (status) {
			bit = __ffs(status);
			status &= ~BIT(bit);
			generic_handle_irq(
				irq_find_mapping(d->irq_domain,
						 d->chip.base + bit));
		}
	}
	chained_irq_exit(irq_desc_get_chip(desc), desc);
	/* now it may re-trigger */
}

static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_gpio_controller *d = chip2controller(chip);

	if (d->irq_domain)
		return irq_create_mapping(d->irq_domain, d->chip.base + offset);
	else
		return -ENXIO;
}

static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_gpio_controller *d = chip2controller(chip);

	/*
	 * NOTE:  we assume for now that only irqs in the first gpio_chip
	 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
	 */
	if (offset < d->gpio_unbanked)
		return d->gpio_irq + offset;
	else
		return -ENODEV;
}

static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
{
	struct davinci_gpio_controller *d;
	struct davinci_gpio_regs __iomem *g;
	u32 mask;

	d = (struct davinci_gpio_controller *)data->handler_data;
	g = (struct davinci_gpio_regs __iomem *)d->regs;
	mask = __gpio_mask(data->irq - d->gpio_irq);

	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		return -EINVAL;

	writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
		     ? &g->set_falling : &g->clr_falling);
	writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
		     ? &g->set_rising : &g->clr_rising);

	return 0;
}

static int
davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
		     irq_hw_number_t hw)
{
	struct davinci_gpio_regs __iomem *g = gpio2regs(hw);

	irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
				"davinci_gpio");
	irq_set_irq_type(irq, IRQ_TYPE_NONE);
	irq_set_chip_data(irq, (__force void *)g);
	irq_set_handler_data(irq, (void *)__gpio_mask(hw));
	set_irq_flags(irq, IRQF_VALID);

	return 0;
}

static const struct irq_domain_ops davinci_gpio_irq_ops = {
	.map = davinci_gpio_irq_map,
	.xlate = irq_domain_xlate_onetwocell,
};

static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
{
	static struct irq_chip_type gpio_unbanked;

	gpio_unbanked = *container_of(irq_get_chip(irq),
				      struct irq_chip_type, chip);

	return &gpio_unbanked.chip;
};

static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
{
	static struct irq_chip gpio_unbanked;

	gpio_unbanked = *irq_get_chip(irq);
	return &gpio_unbanked;
};

static const struct of_device_id davinci_gpio_ids[];

/*
 * NOTE:  for suspend/resume, probably best to make a platform_device with
 * suspend_late/resume_resume calls hooking into results of the set_wake()
 * calls ... so if no gpios are wakeup events the clock can be disabled,
 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
 * (dm6446) can be set appropriately for GPIOV33 pins.
 */

static int davinci_gpio_irq_setup(struct platform_device *pdev)
{
	unsigned	gpio, bank;
	int		irq;
	struct clk	*clk;
	u32		binten = 0;
	unsigned	ngpio, bank_irq;
	struct device *dev = &pdev->dev;
	struct resource	*res;
	struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
	struct davinci_gpio_platform_data *pdata = dev->platform_data;
	struct davinci_gpio_regs __iomem *g;
	struct irq_domain	*irq_domain = NULL;
	const struct of_device_id *match;
	struct irq_chip *irq_chip;
	gpio_get_irq_chip_cb_t gpio_get_irq_chip;

	/*
	 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
	 */
	gpio_get_irq_chip = davinci_gpio_get_irq_chip;
	match = of_match_device(of_match_ptr(davinci_gpio_ids),
				dev);
	if (match)
		gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;

	ngpio = pdata->ngpio;
	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!res) {
		dev_err(dev, "Invalid IRQ resource\n");
		return -EBUSY;
	}

	bank_irq = res->start;

	if (!bank_irq) {
		dev_err(dev, "Invalid IRQ resource\n");
		return -ENODEV;
	}

	clk = devm_clk_get(dev, "gpio");
	if (IS_ERR(clk)) {
		printk(KERN_ERR "Error %ld getting gpio clock?\n",
		       PTR_ERR(clk));
		return PTR_ERR(clk);
	}
	clk_prepare_enable(clk);

	if (!pdata->gpio_unbanked) {
		irq = irq_alloc_descs(-1, 0, ngpio, 0);
		if (irq < 0) {
			dev_err(dev, "Couldn't allocate IRQ numbers\n");
			return irq;
		}

		irq_domain = irq_domain_add_legacy(NULL, ngpio, irq, 0,
							&davinci_gpio_irq_ops,
							chips);
		if (!irq_domain) {
			dev_err(dev, "Couldn't register an IRQ domain\n");
			return -ENODEV;
		}
	}

	/*
	 * Arrange gpio_to_irq() support, handling either direct IRQs or
	 * banked IRQs.  Having GPIOs in the first GPIO bank use direct
	 * IRQs, while the others use banked IRQs, would need some setup
	 * tweaks to recognize hardware which can do that.
	 */
	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
		chips[bank].chip.to_irq = gpio_to_irq_banked;
		chips[bank].irq_domain = irq_domain;
	}

	/*
	 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
	 * controller only handling trigger modes.  We currently assume no
	 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
	 */
	if (pdata->gpio_unbanked) {
		/* pass "bank 0" GPIO IRQs to AINTC */
		chips[0].chip.to_irq = gpio_to_irq_unbanked;
		chips[0].gpio_irq = bank_irq;
		chips[0].gpio_unbanked = pdata->gpio_unbanked;
		binten = BIT(0);

		/* AINTC handles mask/unmask; GPIO handles triggering */
		irq = bank_irq;
		irq_chip = gpio_get_irq_chip(irq);
		irq_chip->name = "GPIO-AINTC";
		irq_chip->irq_set_type = gpio_irq_type_unbanked;

		/* default trigger: both edges */
		g = gpio2regs(0);
		writel_relaxed(~0, &g->set_falling);
		writel_relaxed(~0, &g->set_rising);

		/* set the direct IRQs up to use that irqchip */
		for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
			irq_set_chip(irq, irq_chip);
			irq_set_handler_data(irq, &chips[gpio / 32]);
			irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
		}

		goto done;
	}

	/*
	 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
	 * then chain through our own handler.
	 */
	for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) {
		/* disabled by default, enabled only as needed */
		g = gpio2regs(gpio);
		writel_relaxed(~0, &g->clr_falling);
		writel_relaxed(~0, &g->clr_rising);

		/* set up all irqs in this bank */
		irq_set_chained_handler(bank_irq, gpio_irq_handler);

		/*
		 * Each chip handles 32 gpios, and each irq bank consists of 16
		 * gpio irqs. Pass the irq bank's corresponding controller to
		 * the chained irq handler.
		 */
		irq_set_handler_data(bank_irq, &chips[gpio / 32]);

		binten |= BIT(bank);
	}

done:
	/*
	 * BINTEN -- per-bank interrupt enable. genirq would also let these
	 * bits be set/cleared dynamically.
	 */
	writel_relaxed(binten, gpio_base + BINTEN);

	return 0;
}

#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id davinci_gpio_ids[] = {
	{ .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
	{ .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
#endif

static struct platform_driver davinci_gpio_driver = {
	.probe		= davinci_gpio_probe,
	.driver		= {
		.name		= "davinci_gpio",
		.owner		= THIS_MODULE,
		.of_match_table	= of_match_ptr(davinci_gpio_ids),
	},
};

/**
 * GPIO driver registration needs to be done before machine_init functions
 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
 */
static int __init davinci_gpio_drv_reg(void)
{
	return platform_driver_register(&davinci_gpio_driver);
}
postcore_initcall(davinci_gpio_drv_reg);
Commit	Line	Data
3d9edf09 VB	1	/*
	2	* TI DaVinci GPIO Support
	3	*
dce1115b	4	* Copyright (c) 2006-2007 David Brownell
3d9edf09 VB	5	* Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*/
2f8163ba	12	#include <linux/gpio.h>
3d9edf09 VB	13	#include <linux/errno.h>
3d9edf09 VB	14	#include <linux/kernel.h>
3d9edf09 VB	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
118150f2	18	#include <linux/irq.h>
9211ff31	19	#include <linux/irqdomain.h>
c770844c KS	20	#include <linux/module.h>
	21	#include <linux/of.h>
	22	#include <linux/of_device.h>
118150f2 KS	23	#include <linux/platform_device.h>
118150f2 KS	24	#include <linux/platform_data/gpio-davinci.h>
0d978eb7	25	#include <linux/irqchip/chained_irq.h>
3d9edf09	26
c12f415a CC	27	struct davinci_gpio_regs {
	28	u32 dir;
	29	u32 out_data;
	30	u32 set_data;
	31	u32 clr_data;
	32	u32 in_data;
	33	u32 set_rising;
	34	u32 clr_rising;
	35	u32 set_falling;
	36	u32 clr_falling;
	37	u32 intstat;
	38	};
	39
0c6feb07 GS	40	typedef struct irq_chip (gpio_get_irq_chip_cb_t)(unsigned int irq);
0c6feb07 GS	41
131a10a3 PA	42	#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
131a10a3 PA	43
ba4a984e	44	#define chip2controller(chip) \
99e9e52d	45	container_of(chip, struct davinci_gpio_controller, chip)
ba4a984e	46
b8d44293	47	static void __iomem *gpio_base;
3d9edf09	48
118150f2	49	static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio)
3d9edf09	50	{
c12f415a	51	void __iomem *ptr;
c12f415a CC	52
c12f415a CC	53	if (gpio < 32 * 1)
b8d44293	54	ptr = gpio_base + 0x10;
c12f415a	55	else if (gpio < 32 * 2)
b8d44293	56	ptr = gpio_base + 0x38;
c12f415a	57	else if (gpio < 32 * 3)
b8d44293	58	ptr = gpio_base + 0x60;
c12f415a	59	else if (gpio < 32 * 4)
b8d44293	60	ptr = gpio_base + 0x88;
c12f415a	61	else if (gpio < 32 * 5)
b8d44293	62	ptr = gpio_base + 0xb0;
c12f415a CC	63	else
	64	ptr = NULL;
	65	return ptr;
3d9edf09 VB	66	}
3d9edf09 VB	67
99e9e52d	68	static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
21ce873d	69	{
99e9e52d	70	struct davinci_gpio_regs __iomem *g;
21ce873d	71
6845664a	72	g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
21ce873d KH	73
	74	return g;
	75	}
	76
118150f2	77	static int davinci_gpio_irq_setup(struct platform_device *pdev);
dce1115b DB	78
	79	/--------------------------------------------------------------------------/
	80
5b3a05ca	81	/* board setup code MUST setup pinmux and enable the GPIO clock. */
ba4a984e CC	82	static inline int __davinci_direction(struct gpio_chip *chip,
ba4a984e CC	83	unsigned offset, bool out, int value)
3d9edf09	84	{
99e9e52d CC	85	struct davinci_gpio_controller *d = chip2controller(chip);
99e9e52d CC	86	struct davinci_gpio_regs __iomem *g = d->regs;
b27b6d03	87	unsigned long flags;
dce1115b	88	u32 temp;
ba4a984e	89	u32 mask = 1 << offset;
3d9edf09	90
b27b6d03	91	spin_lock_irqsave(&d->lock, flags);
388291c3	92	temp = readl_relaxed(&g->dir);
ba4a984e CC	93	if (out) {
ba4a984e CC	94	temp &= ~mask;
388291c3	95	writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
ba4a984e CC	96	} else {
	97	temp \|= mask;
	98	}
388291c3	99	writel_relaxed(temp, &g->dir);
b27b6d03	100	spin_unlock_irqrestore(&d->lock, flags);
3d9edf09	101
dce1115b DB	102	return 0;
dce1115b DB	103	}
3d9edf09	104
ba4a984e CC	105	static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
	106	{
	107	return __davinci_direction(chip, offset, false, 0);
	108	}
	109
	110	static int
	111	davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
	112	{
	113	return __davinci_direction(chip, offset, true, value);
	114	}
	115
3d9edf09 VB	116	/*
	117	* Read the pin's value (works even if it's set up as output);
	118	* returns zero/nonzero.
	119	*
	120	* Note that changes are synched to the GPIO clock, so reading values back
	121	* right after you've set them may give old values.
	122	*/
dce1115b	123	static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
3d9edf09	124	{
99e9e52d CC	125	struct davinci_gpio_controller *d = chip2controller(chip);
99e9e52d CC	126	struct davinci_gpio_regs __iomem *g = d->regs;
3d9edf09	127
388291c3	128	return (1 << offset) & readl_relaxed(&g->in_data);
3d9edf09	129	}
3d9edf09	130
dce1115b DB	131	/*
	132	* Assuming the pin is muxed as a gpio output, set its output value.
	133	*/
	134	static void
	135	davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3d9edf09	136	{
99e9e52d CC	137	struct davinci_gpio_controller *d = chip2controller(chip);
99e9e52d CC	138	struct davinci_gpio_regs __iomem *g = d->regs;
3d9edf09	139
388291c3	140	writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data);
dce1115b DB	141	}
dce1115b DB	142
c770844c KS	143	static struct davinci_gpio_platform_data *
	144	davinci_gpio_get_pdata(struct platform_device *pdev)
	145	{
	146	struct device_node *dn = pdev->dev.of_node;
	147	struct davinci_gpio_platform_data *pdata;
	148	int ret;
	149	u32 val;
	150
	151	if (!IS_ENABLED(CONFIG_OF) \|\| !pdev->dev.of_node)
	152	return pdev->dev.platform_data;
	153
	154	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	155	if (!pdata)
	156	return NULL;
	157
	158	ret = of_property_read_u32(dn, "ti,ngpio", &val);
	159	if (ret)
	160	goto of_err;
	161
	162	pdata->ngpio = val;
	163
	164	ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
	165	if (ret)
	166	goto of_err;
	167
	168	pdata->gpio_unbanked = val;
	169
	170	return pdata;
	171
	172	of_err:
	173	dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
	174	return NULL;
	175	}
	176
118150f2	177	static int davinci_gpio_probe(struct platform_device *pdev)
dce1115b DB	178	{
dce1115b DB	179	int i, base;
a994955c	180	unsigned ngpio;
118150f2 KS	181	struct davinci_gpio_controller *chips;
	182	struct davinci_gpio_platform_data *pdata;
	183	struct davinci_gpio_regs __iomem *regs;
	184	struct device *dev = &pdev->dev;
	185	struct resource *res;
	186
c770844c	187	pdata = davinci_gpio_get_pdata(pdev);
118150f2 KS	188	if (!pdata) {
	189	dev_err(dev, "No platform data found\n");
	190	return -EINVAL;
	191	}
686b634a	192
c770844c KS	193	dev->platform_data = pdata;
c770844c KS	194
a994955c MG	195	/*
a994955c MG	196	* The gpio banks conceptually expose a segmented bitmap,
474dad54 DB	197	* and "ngpio" is one more than the largest zero-based
	198	* bit index that's valid.
	199	*/
118150f2	200	ngpio = pdata->ngpio;
a994955c	201	if (ngpio == 0) {
118150f2	202	dev_err(dev, "How many GPIOs?\n");
474dad54 DB	203	return -EINVAL;
	204	}
	205
c21d500b GS	206	if (WARN_ON(ARCH_NR_GPIOS < ngpio))
c21d500b GS	207	ngpio = ARCH_NR_GPIOS;
474dad54	208
118150f2 KS	209	chips = devm_kzalloc(dev,
	210	ngpio * sizeof(struct davinci_gpio_controller),
	211	GFP_KERNEL);
	212	if (!chips) {
	213	dev_err(dev, "Memory allocation failed\n");
b8d44293	214	return -ENOMEM;
118150f2 KS	215	}
	216
	217	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	218	if (!res) {
	219	dev_err(dev, "Invalid memory resource\n");
	220	return -EBUSY;
	221	}
	222
	223	gpio_base = devm_ioremap_resource(dev, res);
	224	if (IS_ERR(gpio_base))
	225	return PTR_ERR(gpio_base);
b8d44293	226
474dad54	227	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
dce1115b DB	228	chips[i].chip.label = "DaVinci";
	229
	230	chips[i].chip.direction_input = davinci_direction_in;
	231	chips[i].chip.get = davinci_gpio_get;
	232	chips[i].chip.direction_output = davinci_direction_out;
	233	chips[i].chip.set = davinci_gpio_set;
	234
	235	chips[i].chip.base = base;
474dad54	236	chips[i].chip.ngpio = ngpio - base;
dce1115b DB	237	if (chips[i].chip.ngpio > 32)
	238	chips[i].chip.ngpio = 32;
	239
c770844c KS	240	#ifdef CONFIG_OF_GPIO
	241	chips[i].chip.of_node = dev->of_node;
	242	#endif
b27b6d03 CC	243	spin_lock_init(&chips[i].lock);
b27b6d03 CC	244
c12f415a CC	245	regs = gpio2regs(base);
	246	chips[i].regs = regs;
	247	chips[i].set_data = &regs->set_data;
	248	chips[i].clr_data = &regs->clr_data;
	249	chips[i].in_data = &regs->in_data;
dce1115b DB	250
	251	gpiochip_add(&chips[i].chip);
	252	}
3d9edf09	253
118150f2 KS	254	platform_set_drvdata(pdev, chips);
118150f2 KS	255	davinci_gpio_irq_setup(pdev);
3d9edf09 VB	256	return 0;
3d9edf09 VB	257	}
3d9edf09	258
dce1115b	259	/--------------------------------------------------------------------------/
3d9edf09 VB	260	/*
	261	* We expect irqs will normally be set up as input pins, but they can also be
	262	* used as output pins ... which is convenient for testing.
	263	*
474dad54	264	* NOTE: The first few GPIOs also have direct INTC hookups in addition
7a36071e	265	* to their GPIOBNK0 irq, with a bit less overhead.
3d9edf09	266	*
474dad54	267	* All those INTC hookups (direct, plus several IRQ banks) can also
3d9edf09 VB	268	* serve as EDMA event triggers.
	269	*/
	270
23265442	271	static void gpio_irq_disable(struct irq_data *d)
3d9edf09	272	{
23265442	273	struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
6845664a	274	u32 mask = (u32) irq_data_get_irq_handler_data(d);
3d9edf09	275
388291c3 LP	276	writel_relaxed(mask, &g->clr_falling);
388291c3 LP	277	writel_relaxed(mask, &g->clr_rising);
3d9edf09 VB	278	}
3d9edf09 VB	279
23265442	280	static void gpio_irq_enable(struct irq_data *d)
3d9edf09	281	{
23265442	282	struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
6845664a	283	u32 mask = (u32) irq_data_get_irq_handler_data(d);
5093aec8	284	unsigned status = irqd_get_trigger_type(d);
3d9edf09	285
df4aab46 DB	286	status &= IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING;
	287	if (!status)
	288	status = IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING;
	289
	290	if (status & IRQ_TYPE_EDGE_FALLING)
388291c3	291	writel_relaxed(mask, &g->set_falling);
df4aab46	292	if (status & IRQ_TYPE_EDGE_RISING)
388291c3	293	writel_relaxed(mask, &g->set_rising);
3d9edf09 VB	294	}
3d9edf09 VB	295
23265442	296	static int gpio_irq_type(struct irq_data *d, unsigned trigger)
3d9edf09	297	{
3d9edf09 VB	298	if (trigger & ~(IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
	299	return -EINVAL;
	300
3d9edf09 VB	301	return 0;
	302	}
	303
	304	static struct irq_chip gpio_irqchip = {
	305	.name = "GPIO",
23265442 LB	306	.irq_enable = gpio_irq_enable,
	307	.irq_disable = gpio_irq_disable,
	308	.irq_set_type = gpio_irq_type,
5093aec8	309	.flags = IRQCHIP_SET_TYPE_MASKED,
3d9edf09 VB	310	};
	311
	312	static void
	313	gpio_irq_handler(unsigned irq, struct irq_desc *desc)
	314	{
74164016	315	struct davinci_gpio_regs __iomem *g;
3d9edf09	316	u32 mask = 0xffff;
f299bb95	317	struct davinci_gpio_controller *d;
3d9edf09	318
f299bb95 IY	319	d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
f299bb95 IY	320	g = (struct davinci_gpio_regs __iomem *)d->regs;
74164016	321
3d9edf09 VB	322	/* we only care about one bank */
	323	if (irq & 1)
	324	mask <<= 16;
	325
	326	/* temporarily mask (level sensitive) parent IRQ */
0d978eb7	327	chained_irq_enter(irq_desc_get_chip(desc), desc);
3d9edf09 VB	328	while (1) {
3d9edf09 VB	329	u32 status;
9211ff31	330	int bit;
3d9edf09 VB	331
3d9edf09 VB	332	/* ack any irqs */
388291c3	333	status = readl_relaxed(&g->intstat) & mask;
3d9edf09 VB	334	if (!status)
3d9edf09 VB	335	break;
388291c3	336	writel_relaxed(status, &g->intstat);
3d9edf09 VB	337
3d9edf09 VB	338	/* now demux them to the right lowlevel handler */
f299bb95	339
3d9edf09	340	while (status) {
9211ff31 LP	341	bit = __ffs(status);
	342	status &= ~BIT(bit);
	343	generic_handle_irq(
	344	irq_find_mapping(d->irq_domain,
	345	d->chip.base + bit));
3d9edf09 VB	346	}
3d9edf09 VB	347	}
0d978eb7	348	chained_irq_exit(irq_desc_get_chip(desc), desc);
3d9edf09 VB	349	/* now it may re-trigger */
	350	}
	351
7a36071e DB	352	static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
7a36071e DB	353	{
99e9e52d	354	struct davinci_gpio_controller *d = chip2controller(chip);
7a36071e	355
6075a8b2 GS	356	if (d->irq_domain)
	357	return irq_create_mapping(d->irq_domain, d->chip.base + offset);
	358	else
	359	return -ENXIO;
7a36071e DB	360	}
	361
	362	static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
	363	{
118150f2	364	struct davinci_gpio_controller *d = chip2controller(chip);
7a36071e	365
131a10a3 PA	366	/*
131a10a3 PA	367	* NOTE: we assume for now that only irqs in the first gpio_chip
7a36071e DB	368	* can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
7a36071e DB	369	*/
34af1ab4	370	if (offset < d->gpio_unbanked)
118150f2	371	return d->gpio_irq + offset;
7a36071e DB	372	else
	373	return -ENODEV;
	374	}
	375
ab2dde99	376	static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
7a36071e	377	{
ab2dde99 SN	378	struct davinci_gpio_controller *d;
ab2dde99 SN	379	struct davinci_gpio_regs __iomem *g;
ab2dde99 SN	380	u32 mask;
	381
	382	d = (struct davinci_gpio_controller *)data->handler_data;
	383	g = (struct davinci_gpio_regs __iomem *)d->regs;
118150f2	384	mask = __gpio_mask(data->irq - d->gpio_irq);
7a36071e DB	385
	386	if (trigger & ~(IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
	387	return -EINVAL;
	388
388291c3	389	writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
7a36071e	390	? &g->set_falling : &g->clr_falling);
388291c3	391	writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
7a36071e DB	392	? &g->set_rising : &g->clr_rising);
	393
	394	return 0;
	395	}
	396
9211ff31 LP	397	static int
	398	davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
	399	irq_hw_number_t hw)
	400	{
	401	struct davinci_gpio_regs __iomem *g = gpio2regs(hw);
	402
	403	irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
	404	"davinci_gpio");
	405	irq_set_irq_type(irq, IRQ_TYPE_NONE);
	406	irq_set_chip_data(irq, (__force void *)g);
	407	irq_set_handler_data(irq, (void *)__gpio_mask(hw));
	408	set_irq_flags(irq, IRQF_VALID);
	409
	410	return 0;
	411	}
	412
	413	static const struct irq_domain_ops davinci_gpio_irq_ops = {
	414	.map = davinci_gpio_irq_map,
	415	.xlate = irq_domain_xlate_onetwocell,
	416	};
	417
0c6feb07 GS	418	static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
	419	{
	420	static struct irq_chip_type gpio_unbanked;
	421
	422	gpio_unbanked = *container_of(irq_get_chip(irq),
	423	struct irq_chip_type, chip);
	424
	425	return &gpio_unbanked.chip;
	426	};
	427
	428	static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
	429	{
	430	static struct irq_chip gpio_unbanked;
	431
	432	gpio_unbanked = *irq_get_chip(irq);
	433	return &gpio_unbanked;
	434	};
	435
	436	static const struct of_device_id davinci_gpio_ids[];
	437
3d9edf09	438	/*
474dad54 DB	439	* NOTE: for suspend/resume, probably best to make a platform_device with
474dad54 DB	440	* suspend_late/resume_resume calls hooking into results of the set_wake()
3d9edf09 VB	441	* calls ... so if no gpios are wakeup events the clock can be disabled,
3d9edf09 VB	442	* with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
474dad54	443	* (dm6446) can be set appropriately for GPIOV33 pins.
3d9edf09 VB	444	*/
3d9edf09 VB	445
118150f2	446	static int davinci_gpio_irq_setup(struct platform_device *pdev)
3d9edf09	447	{
58c0f5aa AS	448	unsigned gpio, bank;
58c0f5aa AS	449	int irq;
3d9edf09	450	struct clk *clk;
474dad54	451	u32 binten = 0;
a994955c	452	unsigned ngpio, bank_irq;
118150f2 KS	453	struct device *dev = &pdev->dev;
	454	struct resource *res;
	455	struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
	456	struct davinci_gpio_platform_data *pdata = dev->platform_data;
	457	struct davinci_gpio_regs __iomem *g;
6075a8b2	458	struct irq_domain *irq_domain = NULL;
0c6feb07 GS	459	const struct of_device_id *match;
	460	struct irq_chip *irq_chip;
	461	gpio_get_irq_chip_cb_t gpio_get_irq_chip;
	462
	463	/*
	464	* Use davinci_gpio_get_irq_chip by default to handle non DT cases
	465	*/
	466	gpio_get_irq_chip = davinci_gpio_get_irq_chip;
	467	match = of_match_device(of_match_ptr(davinci_gpio_ids),
	468	dev);
	469	if (match)
	470	gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
a994955c	471
118150f2 KS	472	ngpio = pdata->ngpio;
	473	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	474	if (!res) {
	475	dev_err(dev, "Invalid IRQ resource\n");
	476	return -EBUSY;
	477	}
474dad54	478
118150f2 KS	479	bank_irq = res->start;
	480
	481	if (!bank_irq) {
	482	dev_err(dev, "Invalid IRQ resource\n");
	483	return -ENODEV;
474dad54	484	}
3d9edf09	485
118150f2	486	clk = devm_clk_get(dev, "gpio");
3d9edf09 VB	487	if (IS_ERR(clk)) {
	488	printk(KERN_ERR "Error %ld getting gpio clock?\n",
	489	PTR_ERR(clk));
474dad54	490	return PTR_ERR(clk);
3d9edf09	491	}
ce6b658d	492	clk_prepare_enable(clk);
3d9edf09	493
6075a8b2 GS	494	if (!pdata->gpio_unbanked) {
	495	irq = irq_alloc_descs(-1, 0, ngpio, 0);
	496	if (irq < 0) {
	497	dev_err(dev, "Couldn't allocate IRQ numbers\n");
	498	return irq;
	499	}
9211ff31	500
6075a8b2 GS	501	irq_domain = irq_domain_add_legacy(NULL, ngpio, irq, 0,
	502	&davinci_gpio_irq_ops,
	503	chips);
	504	if (!irq_domain) {
	505	dev_err(dev, "Couldn't register an IRQ domain\n");
	506	return -ENODEV;
	507	}
9211ff31 LP	508	}
9211ff31 LP	509
131a10a3 PA	510	/*
131a10a3 PA	511	* Arrange gpio_to_irq() support, handling either direct IRQs or
7a36071e DB	512	* banked IRQs. Having GPIOs in the first GPIO bank use direct
	513	* IRQs, while the others use banked IRQs, would need some setup
	514	* tweaks to recognize hardware which can do that.
	515	*/
	516	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
	517	chips[bank].chip.to_irq = gpio_to_irq_banked;
6075a8b2	518	chips[bank].irq_domain = irq_domain;
7a36071e DB	519	}
	520
	521	/*
	522	* AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
	523	* controller only handling trigger modes. We currently assume no
	524	* IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
	525	*/
118150f2	526	if (pdata->gpio_unbanked) {
7a36071e DB	527	/* pass "bank 0" GPIO IRQs to AINTC */
7a36071e DB	528	chips[0].chip.to_irq = gpio_to_irq_unbanked;
34af1ab4 LP	529	chips[0].gpio_irq = bank_irq;
34af1ab4 LP	530	chips[0].gpio_unbanked = pdata->gpio_unbanked;
7a36071e DB	531	binten = BIT(0);
	532
	533	/* AINTC handles mask/unmask; GPIO handles triggering */
	534	irq = bank_irq;
0c6feb07 GS	535	irq_chip = gpio_get_irq_chip(irq);
	536	irq_chip->name = "GPIO-AINTC";
	537	irq_chip->irq_set_type = gpio_irq_type_unbanked;
7a36071e DB	538
7a36071e DB	539	/* default trigger: both edges */
99e9e52d	540	g = gpio2regs(0);
388291c3 LP	541	writel_relaxed(~0, &g->set_falling);
388291c3 LP	542	writel_relaxed(~0, &g->set_rising);
7a36071e DB	543
7a36071e DB	544	/* set the direct IRQs up to use that irqchip */
118150f2	545	for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
0c6feb07	546	irq_set_chip(irq, irq_chip);
ab2dde99	547	irq_set_handler_data(irq, &chips[gpio / 32]);
5093aec8	548	irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
7a36071e DB	549	}
	550
	551	goto done;
	552	}
	553
	554	/*
	555	* Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
	556	* then chain through our own handler.
	557	*/
9211ff31	558	for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) {
7a36071e	559	/* disabled by default, enabled only as needed */
99e9e52d	560	g = gpio2regs(gpio);
388291c3 LP	561	writel_relaxed(~0, &g->clr_falling);
388291c3 LP	562	writel_relaxed(~0, &g->clr_rising);
3d9edf09 VB	563
3d9edf09 VB	564	/* set up all irqs in this bank */
6845664a	565	irq_set_chained_handler(bank_irq, gpio_irq_handler);
f299bb95 IY	566
	567	/*
	568	* Each chip handles 32 gpios, and each irq bank consists of 16
	569	* gpio irqs. Pass the irq bank's corresponding controller to
	570	* the chained irq handler.
	571	*/
	572	irq_set_handler_data(bank_irq, &chips[gpio / 32]);
3d9edf09	573
474dad54	574	binten \|= BIT(bank);
3d9edf09 VB	575	}
3d9edf09 VB	576
7a36071e	577	done:
131a10a3 PA	578	/*
131a10a3 PA	579	* BINTEN -- per-bank interrupt enable. genirq would also let these
3d9edf09 VB	580	* bits be set/cleared dynamically.
3d9edf09 VB	581	*/
388291c3	582	writel_relaxed(binten, gpio_base + BINTEN);
3d9edf09	583
3d9edf09 VB	584	return 0;
3d9edf09 VB	585	}
118150f2	586
c770844c KS	587	#if IS_ENABLED(CONFIG_OF)
c770844c KS	588	static const struct of_device_id davinci_gpio_ids[] = {
0c6feb07 GS	589	{ .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
0c6feb07 GS	590	{ .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
c770844c KS	591	{ /* sentinel */ },
	592	};
	593	MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
	594	#endif
	595
118150f2 KS	596	static struct platform_driver davinci_gpio_driver = {
	597	.probe = davinci_gpio_probe,
	598	.driver = {
c770844c KS	599	.name = "davinci_gpio",
	600	.owner = THIS_MODULE,
	601	.of_match_table = of_match_ptr(davinci_gpio_ids),
118150f2 KS	602	},
	603	};
	604
	605	/**
	606	* GPIO driver registration needs to be done before machine_init functions
	607	* access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
	608	*/
	609	static int __init davinci_gpio_drv_reg(void)
	610	{
	611	return platform_driver_register(&davinci_gpio_driver);
	612	}
	613	postcore_initcall(davinci_gpio_drv_reg);