Commit | Line | Data |
---|---|---|
3d9edf09 VB |
1 | /* |
2 | * TI DaVinci GPIO Support | |
3 | * | |
dce1115b | 4 | * Copyright (c) 2006-2007 David Brownell |
3d9edf09 VB |
5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
2f8163ba | 12 | #include <linux/gpio.h> |
3d9edf09 VB |
13 | #include <linux/errno.h> |
14 | #include <linux/kernel.h> | |
3d9edf09 VB |
15 | #include <linux/clk.h> |
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
118150f2 | 18 | #include <linux/irq.h> |
9211ff31 | 19 | #include <linux/irqdomain.h> |
c770844c KS |
20 | #include <linux/module.h> |
21 | #include <linux/of.h> | |
22 | #include <linux/of_device.h> | |
118150f2 KS |
23 | #include <linux/platform_device.h> |
24 | #include <linux/platform_data/gpio-davinci.h> | |
0d978eb7 | 25 | #include <linux/irqchip/chained_irq.h> |
3d9edf09 | 26 | |
c12f415a CC |
27 | struct davinci_gpio_regs { |
28 | u32 dir; | |
29 | u32 out_data; | |
30 | u32 set_data; | |
31 | u32 clr_data; | |
32 | u32 in_data; | |
33 | u32 set_rising; | |
34 | u32 clr_rising; | |
35 | u32 set_falling; | |
36 | u32 clr_falling; | |
37 | u32 intstat; | |
38 | }; | |
39 | ||
131a10a3 PA |
40 | #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ |
41 | ||
ba4a984e | 42 | #define chip2controller(chip) \ |
99e9e52d | 43 | container_of(chip, struct davinci_gpio_controller, chip) |
ba4a984e | 44 | |
b8d44293 | 45 | static void __iomem *gpio_base; |
3d9edf09 | 46 | |
118150f2 | 47 | static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio) |
3d9edf09 | 48 | { |
c12f415a | 49 | void __iomem *ptr; |
c12f415a CC |
50 | |
51 | if (gpio < 32 * 1) | |
b8d44293 | 52 | ptr = gpio_base + 0x10; |
c12f415a | 53 | else if (gpio < 32 * 2) |
b8d44293 | 54 | ptr = gpio_base + 0x38; |
c12f415a | 55 | else if (gpio < 32 * 3) |
b8d44293 | 56 | ptr = gpio_base + 0x60; |
c12f415a | 57 | else if (gpio < 32 * 4) |
b8d44293 | 58 | ptr = gpio_base + 0x88; |
c12f415a | 59 | else if (gpio < 32 * 5) |
b8d44293 | 60 | ptr = gpio_base + 0xb0; |
c12f415a CC |
61 | else |
62 | ptr = NULL; | |
63 | return ptr; | |
3d9edf09 VB |
64 | } |
65 | ||
99e9e52d | 66 | static inline struct davinci_gpio_regs __iomem *irq2regs(int irq) |
21ce873d | 67 | { |
99e9e52d | 68 | struct davinci_gpio_regs __iomem *g; |
21ce873d | 69 | |
6845664a | 70 | g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq); |
21ce873d KH |
71 | |
72 | return g; | |
73 | } | |
74 | ||
118150f2 | 75 | static int davinci_gpio_irq_setup(struct platform_device *pdev); |
dce1115b DB |
76 | |
77 | /*--------------------------------------------------------------------------*/ | |
78 | ||
5b3a05ca | 79 | /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ |
ba4a984e CC |
80 | static inline int __davinci_direction(struct gpio_chip *chip, |
81 | unsigned offset, bool out, int value) | |
3d9edf09 | 82 | { |
99e9e52d CC |
83 | struct davinci_gpio_controller *d = chip2controller(chip); |
84 | struct davinci_gpio_regs __iomem *g = d->regs; | |
b27b6d03 | 85 | unsigned long flags; |
dce1115b | 86 | u32 temp; |
ba4a984e | 87 | u32 mask = 1 << offset; |
3d9edf09 | 88 | |
b27b6d03 | 89 | spin_lock_irqsave(&d->lock, flags); |
388291c3 | 90 | temp = readl_relaxed(&g->dir); |
ba4a984e CC |
91 | if (out) { |
92 | temp &= ~mask; | |
388291c3 | 93 | writel_relaxed(mask, value ? &g->set_data : &g->clr_data); |
ba4a984e CC |
94 | } else { |
95 | temp |= mask; | |
96 | } | |
388291c3 | 97 | writel_relaxed(temp, &g->dir); |
b27b6d03 | 98 | spin_unlock_irqrestore(&d->lock, flags); |
3d9edf09 | 99 | |
dce1115b DB |
100 | return 0; |
101 | } | |
3d9edf09 | 102 | |
ba4a984e CC |
103 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) |
104 | { | |
105 | return __davinci_direction(chip, offset, false, 0); | |
106 | } | |
107 | ||
108 | static int | |
109 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) | |
110 | { | |
111 | return __davinci_direction(chip, offset, true, value); | |
112 | } | |
113 | ||
3d9edf09 VB |
114 | /* |
115 | * Read the pin's value (works even if it's set up as output); | |
116 | * returns zero/nonzero. | |
117 | * | |
118 | * Note that changes are synched to the GPIO clock, so reading values back | |
119 | * right after you've set them may give old values. | |
120 | */ | |
dce1115b | 121 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
3d9edf09 | 122 | { |
99e9e52d CC |
123 | struct davinci_gpio_controller *d = chip2controller(chip); |
124 | struct davinci_gpio_regs __iomem *g = d->regs; | |
3d9edf09 | 125 | |
388291c3 | 126 | return (1 << offset) & readl_relaxed(&g->in_data); |
3d9edf09 | 127 | } |
3d9edf09 | 128 | |
dce1115b DB |
129 | /* |
130 | * Assuming the pin is muxed as a gpio output, set its output value. | |
131 | */ | |
132 | static void | |
133 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
3d9edf09 | 134 | { |
99e9e52d CC |
135 | struct davinci_gpio_controller *d = chip2controller(chip); |
136 | struct davinci_gpio_regs __iomem *g = d->regs; | |
3d9edf09 | 137 | |
388291c3 | 138 | writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data); |
dce1115b DB |
139 | } |
140 | ||
c770844c KS |
141 | static struct davinci_gpio_platform_data * |
142 | davinci_gpio_get_pdata(struct platform_device *pdev) | |
143 | { | |
144 | struct device_node *dn = pdev->dev.of_node; | |
145 | struct davinci_gpio_platform_data *pdata; | |
146 | int ret; | |
147 | u32 val; | |
148 | ||
149 | if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) | |
150 | return pdev->dev.platform_data; | |
151 | ||
152 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
153 | if (!pdata) | |
154 | return NULL; | |
155 | ||
156 | ret = of_property_read_u32(dn, "ti,ngpio", &val); | |
157 | if (ret) | |
158 | goto of_err; | |
159 | ||
160 | pdata->ngpio = val; | |
161 | ||
162 | ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val); | |
163 | if (ret) | |
164 | goto of_err; | |
165 | ||
166 | pdata->gpio_unbanked = val; | |
167 | ||
168 | return pdata; | |
169 | ||
170 | of_err: | |
171 | dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret); | |
172 | return NULL; | |
173 | } | |
174 | ||
118150f2 | 175 | static int davinci_gpio_probe(struct platform_device *pdev) |
dce1115b DB |
176 | { |
177 | int i, base; | |
a994955c | 178 | unsigned ngpio; |
118150f2 KS |
179 | struct davinci_gpio_controller *chips; |
180 | struct davinci_gpio_platform_data *pdata; | |
181 | struct davinci_gpio_regs __iomem *regs; | |
182 | struct device *dev = &pdev->dev; | |
183 | struct resource *res; | |
184 | ||
c770844c | 185 | pdata = davinci_gpio_get_pdata(pdev); |
118150f2 KS |
186 | if (!pdata) { |
187 | dev_err(dev, "No platform data found\n"); | |
188 | return -EINVAL; | |
189 | } | |
686b634a | 190 | |
c770844c KS |
191 | dev->platform_data = pdata; |
192 | ||
a994955c MG |
193 | /* |
194 | * The gpio banks conceptually expose a segmented bitmap, | |
474dad54 DB |
195 | * and "ngpio" is one more than the largest zero-based |
196 | * bit index that's valid. | |
197 | */ | |
118150f2 | 198 | ngpio = pdata->ngpio; |
a994955c | 199 | if (ngpio == 0) { |
118150f2 | 200 | dev_err(dev, "How many GPIOs?\n"); |
474dad54 DB |
201 | return -EINVAL; |
202 | } | |
203 | ||
c21d500b GS |
204 | if (WARN_ON(ARCH_NR_GPIOS < ngpio)) |
205 | ngpio = ARCH_NR_GPIOS; | |
474dad54 | 206 | |
118150f2 KS |
207 | chips = devm_kzalloc(dev, |
208 | ngpio * sizeof(struct davinci_gpio_controller), | |
209 | GFP_KERNEL); | |
210 | if (!chips) { | |
211 | dev_err(dev, "Memory allocation failed\n"); | |
b8d44293 | 212 | return -ENOMEM; |
118150f2 KS |
213 | } |
214 | ||
215 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
216 | if (!res) { | |
217 | dev_err(dev, "Invalid memory resource\n"); | |
218 | return -EBUSY; | |
219 | } | |
220 | ||
221 | gpio_base = devm_ioremap_resource(dev, res); | |
222 | if (IS_ERR(gpio_base)) | |
223 | return PTR_ERR(gpio_base); | |
b8d44293 | 224 | |
474dad54 | 225 | for (i = 0, base = 0; base < ngpio; i++, base += 32) { |
dce1115b DB |
226 | chips[i].chip.label = "DaVinci"; |
227 | ||
228 | chips[i].chip.direction_input = davinci_direction_in; | |
229 | chips[i].chip.get = davinci_gpio_get; | |
230 | chips[i].chip.direction_output = davinci_direction_out; | |
231 | chips[i].chip.set = davinci_gpio_set; | |
232 | ||
233 | chips[i].chip.base = base; | |
474dad54 | 234 | chips[i].chip.ngpio = ngpio - base; |
dce1115b DB |
235 | if (chips[i].chip.ngpio > 32) |
236 | chips[i].chip.ngpio = 32; | |
237 | ||
c770844c KS |
238 | #ifdef CONFIG_OF_GPIO |
239 | chips[i].chip.of_node = dev->of_node; | |
240 | #endif | |
b27b6d03 CC |
241 | spin_lock_init(&chips[i].lock); |
242 | ||
c12f415a CC |
243 | regs = gpio2regs(base); |
244 | chips[i].regs = regs; | |
245 | chips[i].set_data = ®s->set_data; | |
246 | chips[i].clr_data = ®s->clr_data; | |
247 | chips[i].in_data = ®s->in_data; | |
dce1115b DB |
248 | |
249 | gpiochip_add(&chips[i].chip); | |
250 | } | |
3d9edf09 | 251 | |
118150f2 KS |
252 | platform_set_drvdata(pdev, chips); |
253 | davinci_gpio_irq_setup(pdev); | |
3d9edf09 VB |
254 | return 0; |
255 | } | |
3d9edf09 | 256 | |
dce1115b | 257 | /*--------------------------------------------------------------------------*/ |
3d9edf09 VB |
258 | /* |
259 | * We expect irqs will normally be set up as input pins, but they can also be | |
260 | * used as output pins ... which is convenient for testing. | |
261 | * | |
474dad54 | 262 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
7a36071e | 263 | * to their GPIOBNK0 irq, with a bit less overhead. |
3d9edf09 | 264 | * |
474dad54 | 265 | * All those INTC hookups (direct, plus several IRQ banks) can also |
3d9edf09 VB |
266 | * serve as EDMA event triggers. |
267 | */ | |
268 | ||
23265442 | 269 | static void gpio_irq_disable(struct irq_data *d) |
3d9edf09 | 270 | { |
23265442 | 271 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
6845664a | 272 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
3d9edf09 | 273 | |
388291c3 LP |
274 | writel_relaxed(mask, &g->clr_falling); |
275 | writel_relaxed(mask, &g->clr_rising); | |
3d9edf09 VB |
276 | } |
277 | ||
23265442 | 278 | static void gpio_irq_enable(struct irq_data *d) |
3d9edf09 | 279 | { |
23265442 | 280 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
6845664a | 281 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
5093aec8 | 282 | unsigned status = irqd_get_trigger_type(d); |
3d9edf09 | 283 | |
df4aab46 DB |
284 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
285 | if (!status) | |
286 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | |
287 | ||
288 | if (status & IRQ_TYPE_EDGE_FALLING) | |
388291c3 | 289 | writel_relaxed(mask, &g->set_falling); |
df4aab46 | 290 | if (status & IRQ_TYPE_EDGE_RISING) |
388291c3 | 291 | writel_relaxed(mask, &g->set_rising); |
3d9edf09 VB |
292 | } |
293 | ||
23265442 | 294 | static int gpio_irq_type(struct irq_data *d, unsigned trigger) |
3d9edf09 | 295 | { |
3d9edf09 VB |
296 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
297 | return -EINVAL; | |
298 | ||
3d9edf09 VB |
299 | return 0; |
300 | } | |
301 | ||
302 | static struct irq_chip gpio_irqchip = { | |
303 | .name = "GPIO", | |
23265442 LB |
304 | .irq_enable = gpio_irq_enable, |
305 | .irq_disable = gpio_irq_disable, | |
306 | .irq_set_type = gpio_irq_type, | |
5093aec8 | 307 | .flags = IRQCHIP_SET_TYPE_MASKED, |
3d9edf09 VB |
308 | }; |
309 | ||
310 | static void | |
311 | gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |
312 | { | |
74164016 | 313 | struct davinci_gpio_regs __iomem *g; |
3d9edf09 | 314 | u32 mask = 0xffff; |
f299bb95 | 315 | struct davinci_gpio_controller *d; |
3d9edf09 | 316 | |
f299bb95 IY |
317 | d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc); |
318 | g = (struct davinci_gpio_regs __iomem *)d->regs; | |
74164016 | 319 | |
3d9edf09 VB |
320 | /* we only care about one bank */ |
321 | if (irq & 1) | |
322 | mask <<= 16; | |
323 | ||
324 | /* temporarily mask (level sensitive) parent IRQ */ | |
0d978eb7 | 325 | chained_irq_enter(irq_desc_get_chip(desc), desc); |
3d9edf09 VB |
326 | while (1) { |
327 | u32 status; | |
9211ff31 | 328 | int bit; |
3d9edf09 VB |
329 | |
330 | /* ack any irqs */ | |
388291c3 | 331 | status = readl_relaxed(&g->intstat) & mask; |
3d9edf09 VB |
332 | if (!status) |
333 | break; | |
388291c3 | 334 | writel_relaxed(status, &g->intstat); |
3d9edf09 VB |
335 | |
336 | /* now demux them to the right lowlevel handler */ | |
f299bb95 | 337 | |
3d9edf09 | 338 | while (status) { |
9211ff31 LP |
339 | bit = __ffs(status); |
340 | status &= ~BIT(bit); | |
341 | generic_handle_irq( | |
342 | irq_find_mapping(d->irq_domain, | |
343 | d->chip.base + bit)); | |
3d9edf09 VB |
344 | } |
345 | } | |
0d978eb7 | 346 | chained_irq_exit(irq_desc_get_chip(desc), desc); |
3d9edf09 VB |
347 | /* now it may re-trigger */ |
348 | } | |
349 | ||
7a36071e DB |
350 | static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) |
351 | { | |
99e9e52d | 352 | struct davinci_gpio_controller *d = chip2controller(chip); |
7a36071e | 353 | |
6075a8b2 GS |
354 | if (d->irq_domain) |
355 | return irq_create_mapping(d->irq_domain, d->chip.base + offset); | |
356 | else | |
357 | return -ENXIO; | |
7a36071e DB |
358 | } |
359 | ||
360 | static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) | |
361 | { | |
118150f2 | 362 | struct davinci_gpio_controller *d = chip2controller(chip); |
7a36071e | 363 | |
131a10a3 PA |
364 | /* |
365 | * NOTE: we assume for now that only irqs in the first gpio_chip | |
7a36071e DB |
366 | * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). |
367 | */ | |
34af1ab4 | 368 | if (offset < d->gpio_unbanked) |
118150f2 | 369 | return d->gpio_irq + offset; |
7a36071e DB |
370 | else |
371 | return -ENODEV; | |
372 | } | |
373 | ||
ab2dde99 | 374 | static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) |
7a36071e | 375 | { |
ab2dde99 SN |
376 | struct davinci_gpio_controller *d; |
377 | struct davinci_gpio_regs __iomem *g; | |
ab2dde99 SN |
378 | u32 mask; |
379 | ||
380 | d = (struct davinci_gpio_controller *)data->handler_data; | |
381 | g = (struct davinci_gpio_regs __iomem *)d->regs; | |
118150f2 | 382 | mask = __gpio_mask(data->irq - d->gpio_irq); |
7a36071e DB |
383 | |
384 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
385 | return -EINVAL; | |
386 | ||
388291c3 | 387 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) |
7a36071e | 388 | ? &g->set_falling : &g->clr_falling); |
388291c3 | 389 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) |
7a36071e DB |
390 | ? &g->set_rising : &g->clr_rising); |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
9211ff31 LP |
395 | static int |
396 | davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, | |
397 | irq_hw_number_t hw) | |
398 | { | |
399 | struct davinci_gpio_regs __iomem *g = gpio2regs(hw); | |
400 | ||
401 | irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, | |
402 | "davinci_gpio"); | |
403 | irq_set_irq_type(irq, IRQ_TYPE_NONE); | |
404 | irq_set_chip_data(irq, (__force void *)g); | |
405 | irq_set_handler_data(irq, (void *)__gpio_mask(hw)); | |
406 | set_irq_flags(irq, IRQF_VALID); | |
407 | ||
408 | return 0; | |
409 | } | |
410 | ||
411 | static const struct irq_domain_ops davinci_gpio_irq_ops = { | |
412 | .map = davinci_gpio_irq_map, | |
413 | .xlate = irq_domain_xlate_onetwocell, | |
414 | }; | |
415 | ||
3d9edf09 | 416 | /* |
474dad54 DB |
417 | * NOTE: for suspend/resume, probably best to make a platform_device with |
418 | * suspend_late/resume_resume calls hooking into results of the set_wake() | |
3d9edf09 VB |
419 | * calls ... so if no gpios are wakeup events the clock can be disabled, |
420 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 | |
474dad54 | 421 | * (dm6446) can be set appropriately for GPIOV33 pins. |
3d9edf09 VB |
422 | */ |
423 | ||
118150f2 | 424 | static int davinci_gpio_irq_setup(struct platform_device *pdev) |
3d9edf09 VB |
425 | { |
426 | unsigned gpio, irq, bank; | |
427 | struct clk *clk; | |
474dad54 | 428 | u32 binten = 0; |
a994955c | 429 | unsigned ngpio, bank_irq; |
118150f2 KS |
430 | struct device *dev = &pdev->dev; |
431 | struct resource *res; | |
432 | struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); | |
433 | struct davinci_gpio_platform_data *pdata = dev->platform_data; | |
434 | struct davinci_gpio_regs __iomem *g; | |
6075a8b2 | 435 | struct irq_domain *irq_domain = NULL; |
a994955c | 436 | |
118150f2 KS |
437 | ngpio = pdata->ngpio; |
438 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
439 | if (!res) { | |
440 | dev_err(dev, "Invalid IRQ resource\n"); | |
441 | return -EBUSY; | |
442 | } | |
474dad54 | 443 | |
118150f2 KS |
444 | bank_irq = res->start; |
445 | ||
446 | if (!bank_irq) { | |
447 | dev_err(dev, "Invalid IRQ resource\n"); | |
448 | return -ENODEV; | |
474dad54 | 449 | } |
3d9edf09 | 450 | |
118150f2 | 451 | clk = devm_clk_get(dev, "gpio"); |
3d9edf09 VB |
452 | if (IS_ERR(clk)) { |
453 | printk(KERN_ERR "Error %ld getting gpio clock?\n", | |
454 | PTR_ERR(clk)); | |
474dad54 | 455 | return PTR_ERR(clk); |
3d9edf09 | 456 | } |
ce6b658d | 457 | clk_prepare_enable(clk); |
3d9edf09 | 458 | |
6075a8b2 GS |
459 | if (!pdata->gpio_unbanked) { |
460 | irq = irq_alloc_descs(-1, 0, ngpio, 0); | |
461 | if (irq < 0) { | |
462 | dev_err(dev, "Couldn't allocate IRQ numbers\n"); | |
463 | return irq; | |
464 | } | |
9211ff31 | 465 | |
6075a8b2 GS |
466 | irq_domain = irq_domain_add_legacy(NULL, ngpio, irq, 0, |
467 | &davinci_gpio_irq_ops, | |
468 | chips); | |
469 | if (!irq_domain) { | |
470 | dev_err(dev, "Couldn't register an IRQ domain\n"); | |
471 | return -ENODEV; | |
472 | } | |
9211ff31 LP |
473 | } |
474 | ||
131a10a3 PA |
475 | /* |
476 | * Arrange gpio_to_irq() support, handling either direct IRQs or | |
7a36071e DB |
477 | * banked IRQs. Having GPIOs in the first GPIO bank use direct |
478 | * IRQs, while the others use banked IRQs, would need some setup | |
479 | * tweaks to recognize hardware which can do that. | |
480 | */ | |
481 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { | |
482 | chips[bank].chip.to_irq = gpio_to_irq_banked; | |
6075a8b2 | 483 | chips[bank].irq_domain = irq_domain; |
7a36071e DB |
484 | } |
485 | ||
486 | /* | |
487 | * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO | |
488 | * controller only handling trigger modes. We currently assume no | |
489 | * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. | |
490 | */ | |
118150f2 | 491 | if (pdata->gpio_unbanked) { |
81b279d8 | 492 | static struct irq_chip_type gpio_unbanked; |
7a36071e DB |
493 | |
494 | /* pass "bank 0" GPIO IRQs to AINTC */ | |
495 | chips[0].chip.to_irq = gpio_to_irq_unbanked; | |
34af1ab4 LP |
496 | chips[0].gpio_irq = bank_irq; |
497 | chips[0].gpio_unbanked = pdata->gpio_unbanked; | |
7a36071e DB |
498 | binten = BIT(0); |
499 | ||
500 | /* AINTC handles mask/unmask; GPIO handles triggering */ | |
501 | irq = bank_irq; | |
81b279d8 SN |
502 | gpio_unbanked = *container_of(irq_get_chip(irq), |
503 | struct irq_chip_type, chip); | |
504 | gpio_unbanked.chip.name = "GPIO-AINTC"; | |
505 | gpio_unbanked.chip.irq_set_type = gpio_irq_type_unbanked; | |
7a36071e DB |
506 | |
507 | /* default trigger: both edges */ | |
99e9e52d | 508 | g = gpio2regs(0); |
388291c3 LP |
509 | writel_relaxed(~0, &g->set_falling); |
510 | writel_relaxed(~0, &g->set_rising); | |
7a36071e DB |
511 | |
512 | /* set the direct IRQs up to use that irqchip */ | |
118150f2 | 513 | for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) { |
81b279d8 | 514 | irq_set_chip(irq, &gpio_unbanked.chip); |
ab2dde99 | 515 | irq_set_handler_data(irq, &chips[gpio / 32]); |
5093aec8 | 516 | irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); |
7a36071e DB |
517 | } |
518 | ||
519 | goto done; | |
520 | } | |
521 | ||
522 | /* | |
523 | * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we | |
524 | * then chain through our own handler. | |
525 | */ | |
9211ff31 | 526 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) { |
7a36071e | 527 | /* disabled by default, enabled only as needed */ |
99e9e52d | 528 | g = gpio2regs(gpio); |
388291c3 LP |
529 | writel_relaxed(~0, &g->clr_falling); |
530 | writel_relaxed(~0, &g->clr_rising); | |
3d9edf09 VB |
531 | |
532 | /* set up all irqs in this bank */ | |
6845664a | 533 | irq_set_chained_handler(bank_irq, gpio_irq_handler); |
f299bb95 IY |
534 | |
535 | /* | |
536 | * Each chip handles 32 gpios, and each irq bank consists of 16 | |
537 | * gpio irqs. Pass the irq bank's corresponding controller to | |
538 | * the chained irq handler. | |
539 | */ | |
540 | irq_set_handler_data(bank_irq, &chips[gpio / 32]); | |
3d9edf09 | 541 | |
474dad54 | 542 | binten |= BIT(bank); |
3d9edf09 VB |
543 | } |
544 | ||
7a36071e | 545 | done: |
131a10a3 PA |
546 | /* |
547 | * BINTEN -- per-bank interrupt enable. genirq would also let these | |
3d9edf09 VB |
548 | * bits be set/cleared dynamically. |
549 | */ | |
388291c3 | 550 | writel_relaxed(binten, gpio_base + BINTEN); |
3d9edf09 | 551 | |
3d9edf09 VB |
552 | return 0; |
553 | } | |
118150f2 | 554 | |
c770844c KS |
555 | #if IS_ENABLED(CONFIG_OF) |
556 | static const struct of_device_id davinci_gpio_ids[] = { | |
557 | { .compatible = "ti,dm6441-gpio", }, | |
558 | { /* sentinel */ }, | |
559 | }; | |
560 | MODULE_DEVICE_TABLE(of, davinci_gpio_ids); | |
561 | #endif | |
562 | ||
118150f2 KS |
563 | static struct platform_driver davinci_gpio_driver = { |
564 | .probe = davinci_gpio_probe, | |
565 | .driver = { | |
c770844c KS |
566 | .name = "davinci_gpio", |
567 | .owner = THIS_MODULE, | |
568 | .of_match_table = of_match_ptr(davinci_gpio_ids), | |
118150f2 KS |
569 | }, |
570 | }; | |
571 | ||
572 | /** | |
573 | * GPIO driver registration needs to be done before machine_init functions | |
574 | * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall. | |
575 | */ | |
576 | static int __init davinci_gpio_drv_reg(void) | |
577 | { | |
578 | return platform_driver_register(&davinci_gpio_driver); | |
579 | } | |
580 | postcore_initcall(davinci_gpio_drv_reg); |