Commit | Line | Data |
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3d9edf09 VB |
1 | /* |
2 | * TI DaVinci GPIO Support | |
3 | * | |
dce1115b | 4 | * Copyright (c) 2006-2007 David Brownell |
3d9edf09 VB |
5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
79b73ff9 | 12 | |
7220c43a | 13 | #include <linux/gpio/driver.h> |
3d9edf09 VB |
14 | #include <linux/errno.h> |
15 | #include <linux/kernel.h> | |
3d9edf09 VB |
16 | #include <linux/clk.h> |
17 | #include <linux/err.h> | |
18 | #include <linux/io.h> | |
118150f2 | 19 | #include <linux/irq.h> |
9211ff31 | 20 | #include <linux/irqdomain.h> |
c770844c KS |
21 | #include <linux/module.h> |
22 | #include <linux/of.h> | |
23 | #include <linux/of_device.h> | |
3c87d7c8 | 24 | #include <linux/pinctrl/consumer.h> |
118150f2 KS |
25 | #include <linux/platform_device.h> |
26 | #include <linux/platform_data/gpio-davinci.h> | |
0d978eb7 | 27 | #include <linux/irqchip/chained_irq.h> |
79b73ff9 AD |
28 | #include <linux/spinlock.h> |
29 | ||
30 | #include <asm-generic/gpio.h> | |
31 | ||
32 | #define MAX_REGS_BANKS 5 | |
33 | #define MAX_INT_PER_BANK 32 | |
3d9edf09 | 34 | |
c12f415a CC |
35 | struct davinci_gpio_regs { |
36 | u32 dir; | |
37 | u32 out_data; | |
38 | u32 set_data; | |
39 | u32 clr_data; | |
40 | u32 in_data; | |
41 | u32 set_rising; | |
42 | u32 clr_rising; | |
43 | u32 set_falling; | |
44 | u32 clr_falling; | |
45 | u32 intstat; | |
46 | }; | |
47 | ||
0c6feb07 GS |
48 | typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq); |
49 | ||
131a10a3 PA |
50 | #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ |
51 | ||
b8d44293 | 52 | static void __iomem *gpio_base; |
8f7cf8c6 | 53 | static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0}; |
3d9edf09 | 54 | |
79b73ff9 AD |
55 | struct davinci_gpio_irq_data { |
56 | void __iomem *regs; | |
57 | struct davinci_gpio_controller *chip; | |
58 | int bank_num; | |
59 | }; | |
60 | ||
61 | struct davinci_gpio_controller { | |
62 | struct gpio_chip chip; | |
63 | struct irq_domain *irq_domain; | |
64 | /* Serialize access to GPIO registers */ | |
65 | spinlock_t lock; | |
66 | void __iomem *regs[MAX_REGS_BANKS]; | |
67 | int gpio_unbanked; | |
68 | int irqs[MAX_INT_PER_BANK]; | |
69 | }; | |
70 | ||
71 | static inline u32 __gpio_mask(unsigned gpio) | |
72 | { | |
73 | return 1 << (gpio % 32); | |
74 | } | |
75 | ||
1765d671 | 76 | static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d) |
21ce873d | 77 | { |
99e9e52d | 78 | struct davinci_gpio_regs __iomem *g; |
21ce873d | 79 | |
1765d671 | 80 | g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d); |
21ce873d KH |
81 | |
82 | return g; | |
83 | } | |
84 | ||
eb3744a2 | 85 | static int davinci_gpio_irq_setup(struct platform_device *pdev); |
dce1115b DB |
86 | |
87 | /*--------------------------------------------------------------------------*/ | |
88 | ||
5b3a05ca | 89 | /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ |
ba4a984e CC |
90 | static inline int __davinci_direction(struct gpio_chip *chip, |
91 | unsigned offset, bool out, int value) | |
3d9edf09 | 92 | { |
72a1ca2c | 93 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
b5cf3fd8 | 94 | struct davinci_gpio_regs __iomem *g; |
b27b6d03 | 95 | unsigned long flags; |
dce1115b | 96 | u32 temp; |
b5cf3fd8 K |
97 | int bank = offset / 32; |
98 | u32 mask = __gpio_mask(offset); | |
3d9edf09 | 99 | |
b5cf3fd8 | 100 | g = d->regs[bank]; |
b27b6d03 | 101 | spin_lock_irqsave(&d->lock, flags); |
388291c3 | 102 | temp = readl_relaxed(&g->dir); |
ba4a984e CC |
103 | if (out) { |
104 | temp &= ~mask; | |
388291c3 | 105 | writel_relaxed(mask, value ? &g->set_data : &g->clr_data); |
ba4a984e CC |
106 | } else { |
107 | temp |= mask; | |
108 | } | |
388291c3 | 109 | writel_relaxed(temp, &g->dir); |
b27b6d03 | 110 | spin_unlock_irqrestore(&d->lock, flags); |
3d9edf09 | 111 | |
dce1115b DB |
112 | return 0; |
113 | } | |
3d9edf09 | 114 | |
ba4a984e CC |
115 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) |
116 | { | |
117 | return __davinci_direction(chip, offset, false, 0); | |
118 | } | |
119 | ||
120 | static int | |
121 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) | |
122 | { | |
123 | return __davinci_direction(chip, offset, true, value); | |
124 | } | |
125 | ||
3d9edf09 VB |
126 | /* |
127 | * Read the pin's value (works even if it's set up as output); | |
128 | * returns zero/nonzero. | |
129 | * | |
130 | * Note that changes are synched to the GPIO clock, so reading values back | |
131 | * right after you've set them may give old values. | |
132 | */ | |
dce1115b | 133 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
3d9edf09 | 134 | { |
72a1ca2c | 135 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
b5cf3fd8 K |
136 | struct davinci_gpio_regs __iomem *g; |
137 | int bank = offset / 32; | |
3d9edf09 | 138 | |
b5cf3fd8 K |
139 | g = d->regs[bank]; |
140 | ||
141 | return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data)); | |
3d9edf09 | 142 | } |
3d9edf09 | 143 | |
dce1115b DB |
144 | /* |
145 | * Assuming the pin is muxed as a gpio output, set its output value. | |
146 | */ | |
147 | static void | |
148 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
3d9edf09 | 149 | { |
72a1ca2c | 150 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
b5cf3fd8 K |
151 | struct davinci_gpio_regs __iomem *g; |
152 | int bank = offset / 32; | |
3d9edf09 | 153 | |
b5cf3fd8 K |
154 | g = d->regs[bank]; |
155 | ||
156 | writel_relaxed(__gpio_mask(offset), | |
157 | value ? &g->set_data : &g->clr_data); | |
dce1115b DB |
158 | } |
159 | ||
c770844c KS |
160 | static struct davinci_gpio_platform_data * |
161 | davinci_gpio_get_pdata(struct platform_device *pdev) | |
162 | { | |
163 | struct device_node *dn = pdev->dev.of_node; | |
164 | struct davinci_gpio_platform_data *pdata; | |
165 | int ret; | |
166 | u32 val; | |
167 | ||
168 | if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) | |
ab128afc | 169 | return dev_get_platdata(&pdev->dev); |
c770844c KS |
170 | |
171 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
172 | if (!pdata) | |
173 | return NULL; | |
174 | ||
175 | ret = of_property_read_u32(dn, "ti,ngpio", &val); | |
176 | if (ret) | |
177 | goto of_err; | |
178 | ||
179 | pdata->ngpio = val; | |
180 | ||
181 | ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val); | |
182 | if (ret) | |
183 | goto of_err; | |
184 | ||
185 | pdata->gpio_unbanked = val; | |
186 | ||
187 | return pdata; | |
188 | ||
189 | of_err: | |
190 | dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret); | |
191 | return NULL; | |
192 | } | |
193 | ||
118150f2 | 194 | static int davinci_gpio_probe(struct platform_device *pdev) |
dce1115b | 195 | { |
c809e37a | 196 | int bank, i, ret = 0; |
eb3744a2 | 197 | unsigned int ngpio, nbank, nirq; |
118150f2 KS |
198 | struct davinci_gpio_controller *chips; |
199 | struct davinci_gpio_platform_data *pdata; | |
118150f2 | 200 | struct device *dev = &pdev->dev; |
118150f2 | 201 | |
c770844c | 202 | pdata = davinci_gpio_get_pdata(pdev); |
118150f2 KS |
203 | if (!pdata) { |
204 | dev_err(dev, "No platform data found\n"); | |
205 | return -EINVAL; | |
206 | } | |
686b634a | 207 | |
c770844c KS |
208 | dev->platform_data = pdata; |
209 | ||
a994955c MG |
210 | /* |
211 | * The gpio banks conceptually expose a segmented bitmap, | |
474dad54 DB |
212 | * and "ngpio" is one more than the largest zero-based |
213 | * bit index that's valid. | |
214 | */ | |
118150f2 | 215 | ngpio = pdata->ngpio; |
a994955c | 216 | if (ngpio == 0) { |
118150f2 | 217 | dev_err(dev, "How many GPIOs?\n"); |
474dad54 DB |
218 | return -EINVAL; |
219 | } | |
220 | ||
c21d500b GS |
221 | if (WARN_ON(ARCH_NR_GPIOS < ngpio)) |
222 | ngpio = ARCH_NR_GPIOS; | |
474dad54 | 223 | |
eb3744a2 K |
224 | /* |
225 | * If there are unbanked interrupts then the number of | |
226 | * interrupts is equal to number of gpios else all are banked so | |
227 | * number of interrupts is equal to number of banks(each with 16 gpios) | |
228 | */ | |
229 | if (pdata->gpio_unbanked) | |
230 | nirq = pdata->gpio_unbanked; | |
231 | else | |
232 | nirq = DIV_ROUND_UP(ngpio, 16); | |
233 | ||
c809e37a | 234 | chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL); |
9ea9363c | 235 | if (!chips) |
b8d44293 | 236 | return -ENOMEM; |
118150f2 | 237 | |
fa7569c8 | 238 | gpio_base = devm_platform_ioremap_resource(pdev, 0); |
118150f2 KS |
239 | if (IS_ERR(gpio_base)) |
240 | return PTR_ERR(gpio_base); | |
b8d44293 | 241 | |
eb3744a2 K |
242 | for (i = 0; i < nirq; i++) { |
243 | chips->irqs[i] = platform_get_irq(pdev, i); | |
244 | if (chips->irqs[i] < 0) { | |
245 | dev_info(dev, "IRQ not populated, err = %d\n", | |
246 | chips->irqs[i]); | |
247 | return chips->irqs[i]; | |
248 | } | |
c1d013a7 K |
249 | } |
250 | ||
587f7a69 | 251 | chips->chip.label = dev_name(dev); |
dce1115b | 252 | |
b5cf3fd8 K |
253 | chips->chip.direction_input = davinci_direction_in; |
254 | chips->chip.get = davinci_gpio_get; | |
255 | chips->chip.direction_output = davinci_direction_out; | |
256 | chips->chip.set = davinci_gpio_set; | |
dce1115b | 257 | |
b5cf3fd8 | 258 | chips->chip.ngpio = ngpio; |
786a9ab1 | 259 | chips->chip.base = pdata->no_auto_base ? pdata->base : -1; |
dce1115b | 260 | |
c770844c | 261 | #ifdef CONFIG_OF_GPIO |
b5cf3fd8 | 262 | chips->chip.of_gpio_n_cells = 2; |
b5cf3fd8 K |
263 | chips->chip.parent = dev; |
264 | chips->chip.of_node = dev->of_node; | |
3c87d7c8 DL |
265 | |
266 | if (of_property_read_bool(dev->of_node, "gpio-ranges")) { | |
267 | chips->chip.request = gpiochip_generic_request; | |
268 | chips->chip.free = gpiochip_generic_free; | |
269 | } | |
c770844c | 270 | #endif |
b5cf3fd8 | 271 | spin_lock_init(&chips->lock); |
dce1115b | 272 | |
c809e37a AD |
273 | nbank = DIV_ROUND_UP(ngpio, 32); |
274 | for (bank = 0; bank < nbank; bank++) | |
b5cf3fd8 | 275 | chips->regs[bank] = gpio_base + offset_array[bank]; |
3d9edf09 | 276 | |
8327e1ba K |
277 | ret = devm_gpiochip_add_data(dev, &chips->chip, chips); |
278 | if (ret) | |
587f7a69 | 279 | return ret; |
8327e1ba | 280 | |
118150f2 | 281 | platform_set_drvdata(pdev, chips); |
eb3744a2 | 282 | ret = davinci_gpio_irq_setup(pdev); |
5e7a0ce7 | 283 | if (ret) |
587f7a69 | 284 | return ret; |
5e7a0ce7 | 285 | |
3d9edf09 VB |
286 | return 0; |
287 | } | |
3d9edf09 | 288 | |
dce1115b | 289 | /*--------------------------------------------------------------------------*/ |
3d9edf09 VB |
290 | /* |
291 | * We expect irqs will normally be set up as input pins, but they can also be | |
292 | * used as output pins ... which is convenient for testing. | |
293 | * | |
474dad54 | 294 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
7a36071e | 295 | * to their GPIOBNK0 irq, with a bit less overhead. |
3d9edf09 | 296 | * |
474dad54 | 297 | * All those INTC hookups (direct, plus several IRQ banks) can also |
3d9edf09 VB |
298 | * serve as EDMA event triggers. |
299 | */ | |
300 | ||
23265442 | 301 | static void gpio_irq_disable(struct irq_data *d) |
3d9edf09 | 302 | { |
1765d671 | 303 | struct davinci_gpio_regs __iomem *g = irq2regs(d); |
36c05519 | 304 | uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d); |
3d9edf09 | 305 | |
388291c3 LP |
306 | writel_relaxed(mask, &g->clr_falling); |
307 | writel_relaxed(mask, &g->clr_rising); | |
3d9edf09 VB |
308 | } |
309 | ||
23265442 | 310 | static void gpio_irq_enable(struct irq_data *d) |
3d9edf09 | 311 | { |
1765d671 | 312 | struct davinci_gpio_regs __iomem *g = irq2regs(d); |
36c05519 | 313 | uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d); |
5093aec8 | 314 | unsigned status = irqd_get_trigger_type(d); |
3d9edf09 | 315 | |
df4aab46 DB |
316 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
317 | if (!status) | |
318 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | |
319 | ||
320 | if (status & IRQ_TYPE_EDGE_FALLING) | |
388291c3 | 321 | writel_relaxed(mask, &g->set_falling); |
df4aab46 | 322 | if (status & IRQ_TYPE_EDGE_RISING) |
388291c3 | 323 | writel_relaxed(mask, &g->set_rising); |
3d9edf09 VB |
324 | } |
325 | ||
23265442 | 326 | static int gpio_irq_type(struct irq_data *d, unsigned trigger) |
3d9edf09 | 327 | { |
3d9edf09 VB |
328 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
329 | return -EINVAL; | |
330 | ||
3d9edf09 VB |
331 | return 0; |
332 | } | |
333 | ||
334 | static struct irq_chip gpio_irqchip = { | |
335 | .name = "GPIO", | |
23265442 LB |
336 | .irq_enable = gpio_irq_enable, |
337 | .irq_disable = gpio_irq_disable, | |
338 | .irq_set_type = gpio_irq_type, | |
5093aec8 | 339 | .flags = IRQCHIP_SET_TYPE_MASKED, |
3d9edf09 VB |
340 | }; |
341 | ||
bd0b9ac4 | 342 | static void gpio_irq_handler(struct irq_desc *desc) |
3d9edf09 | 343 | { |
74164016 | 344 | struct davinci_gpio_regs __iomem *g; |
3d9edf09 | 345 | u32 mask = 0xffff; |
b5cf3fd8 | 346 | int bank_num; |
f299bb95 | 347 | struct davinci_gpio_controller *d; |
b5cf3fd8 | 348 | struct davinci_gpio_irq_data *irqdata; |
3d9edf09 | 349 | |
b5cf3fd8 K |
350 | irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc); |
351 | bank_num = irqdata->bank_num; | |
352 | g = irqdata->regs; | |
353 | d = irqdata->chip; | |
74164016 | 354 | |
3d9edf09 | 355 | /* we only care about one bank */ |
b5cf3fd8 | 356 | if ((bank_num % 2) == 1) |
3d9edf09 VB |
357 | mask <<= 16; |
358 | ||
359 | /* temporarily mask (level sensitive) parent IRQ */ | |
0d978eb7 | 360 | chained_irq_enter(irq_desc_get_chip(desc), desc); |
3d9edf09 VB |
361 | while (1) { |
362 | u32 status; | |
9211ff31 | 363 | int bit; |
b5cf3fd8 | 364 | irq_hw_number_t hw_irq; |
3d9edf09 VB |
365 | |
366 | /* ack any irqs */ | |
388291c3 | 367 | status = readl_relaxed(&g->intstat) & mask; |
3d9edf09 VB |
368 | if (!status) |
369 | break; | |
388291c3 | 370 | writel_relaxed(status, &g->intstat); |
3d9edf09 VB |
371 | |
372 | /* now demux them to the right lowlevel handler */ | |
f299bb95 | 373 | |
3d9edf09 | 374 | while (status) { |
9211ff31 LP |
375 | bit = __ffs(status); |
376 | status &= ~BIT(bit); | |
b5cf3fd8 K |
377 | /* Max number of gpios per controller is 144 so |
378 | * hw_irq will be in [0..143] | |
379 | */ | |
380 | hw_irq = (bank_num / 2) * 32 + bit; | |
381 | ||
9211ff31 | 382 | generic_handle_irq( |
b5cf3fd8 | 383 | irq_find_mapping(d->irq_domain, hw_irq)); |
3d9edf09 VB |
384 | } |
385 | } | |
0d978eb7 | 386 | chained_irq_exit(irq_desc_get_chip(desc), desc); |
3d9edf09 VB |
387 | /* now it may re-trigger */ |
388 | } | |
389 | ||
7a36071e DB |
390 | static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) |
391 | { | |
72a1ca2c | 392 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
7a36071e | 393 | |
6075a8b2 | 394 | if (d->irq_domain) |
b5cf3fd8 | 395 | return irq_create_mapping(d->irq_domain, offset); |
6075a8b2 GS |
396 | else |
397 | return -ENXIO; | |
7a36071e DB |
398 | } |
399 | ||
400 | static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) | |
401 | { | |
72a1ca2c | 402 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
7a36071e | 403 | |
131a10a3 PA |
404 | /* |
405 | * NOTE: we assume for now that only irqs in the first gpio_chip | |
7a36071e DB |
406 | * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). |
407 | */ | |
34af1ab4 | 408 | if (offset < d->gpio_unbanked) |
eb3744a2 | 409 | return d->irqs[offset]; |
7a36071e DB |
410 | else |
411 | return -ENODEV; | |
412 | } | |
413 | ||
ab2dde99 | 414 | static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) |
7a36071e | 415 | { |
ab2dde99 SN |
416 | struct davinci_gpio_controller *d; |
417 | struct davinci_gpio_regs __iomem *g; | |
eb3744a2 | 418 | u32 mask, i; |
ab2dde99 | 419 | |
c16edb8b | 420 | d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data); |
7f8e2a85 | 421 | g = (struct davinci_gpio_regs __iomem *)d->regs[0]; |
eb3744a2 K |
422 | for (i = 0; i < MAX_INT_PER_BANK; i++) |
423 | if (data->irq == d->irqs[i]) | |
424 | break; | |
425 | ||
426 | if (i == MAX_INT_PER_BANK) | |
427 | return -EINVAL; | |
428 | ||
429 | mask = __gpio_mask(i); | |
7a36071e DB |
430 | |
431 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
432 | return -EINVAL; | |
433 | ||
388291c3 | 434 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) |
7a36071e | 435 | ? &g->set_falling : &g->clr_falling); |
388291c3 | 436 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) |
7a36071e DB |
437 | ? &g->set_rising : &g->clr_rising); |
438 | ||
439 | return 0; | |
440 | } | |
441 | ||
9211ff31 LP |
442 | static int |
443 | davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, | |
444 | irq_hw_number_t hw) | |
445 | { | |
8f7cf8c6 K |
446 | struct davinci_gpio_controller *chips = |
447 | (struct davinci_gpio_controller *)d->host_data; | |
b5cf3fd8 | 448 | struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32]; |
9211ff31 LP |
449 | |
450 | irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, | |
451 | "davinci_gpio"); | |
452 | irq_set_irq_type(irq, IRQ_TYPE_NONE); | |
453 | irq_set_chip_data(irq, (__force void *)g); | |
36c05519 | 454 | irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw)); |
9211ff31 LP |
455 | |
456 | return 0; | |
457 | } | |
458 | ||
459 | static const struct irq_domain_ops davinci_gpio_irq_ops = { | |
460 | .map = davinci_gpio_irq_map, | |
461 | .xlate = irq_domain_xlate_onetwocell, | |
462 | }; | |
463 | ||
0c6feb07 GS |
464 | static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq) |
465 | { | |
466 | static struct irq_chip_type gpio_unbanked; | |
467 | ||
ccdbddfe | 468 | gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq)); |
0c6feb07 GS |
469 | |
470 | return &gpio_unbanked.chip; | |
471 | }; | |
472 | ||
473 | static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq) | |
474 | { | |
475 | static struct irq_chip gpio_unbanked; | |
476 | ||
477 | gpio_unbanked = *irq_get_chip(irq); | |
478 | return &gpio_unbanked; | |
479 | }; | |
480 | ||
481 | static const struct of_device_id davinci_gpio_ids[]; | |
482 | ||
3d9edf09 | 483 | /* |
474dad54 DB |
484 | * NOTE: for suspend/resume, probably best to make a platform_device with |
485 | * suspend_late/resume_resume calls hooking into results of the set_wake() | |
3d9edf09 VB |
486 | * calls ... so if no gpios are wakeup events the clock can be disabled, |
487 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 | |
474dad54 | 488 | * (dm6446) can be set appropriately for GPIOV33 pins. |
3d9edf09 VB |
489 | */ |
490 | ||
eb3744a2 | 491 | static int davinci_gpio_irq_setup(struct platform_device *pdev) |
3d9edf09 | 492 | { |
58c0f5aa AS |
493 | unsigned gpio, bank; |
494 | int irq; | |
6dc0048c | 495 | int ret; |
3d9edf09 | 496 | struct clk *clk; |
474dad54 | 497 | u32 binten = 0; |
c1d013a7 | 498 | unsigned ngpio; |
118150f2 | 499 | struct device *dev = &pdev->dev; |
118150f2 KS |
500 | struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); |
501 | struct davinci_gpio_platform_data *pdata = dev->platform_data; | |
502 | struct davinci_gpio_regs __iomem *g; | |
6075a8b2 | 503 | struct irq_domain *irq_domain = NULL; |
0c6feb07 GS |
504 | const struct of_device_id *match; |
505 | struct irq_chip *irq_chip; | |
b5cf3fd8 | 506 | struct davinci_gpio_irq_data *irqdata; |
0c6feb07 GS |
507 | gpio_get_irq_chip_cb_t gpio_get_irq_chip; |
508 | ||
509 | /* | |
510 | * Use davinci_gpio_get_irq_chip by default to handle non DT cases | |
511 | */ | |
512 | gpio_get_irq_chip = davinci_gpio_get_irq_chip; | |
513 | match = of_match_device(of_match_ptr(davinci_gpio_ids), | |
514 | dev); | |
515 | if (match) | |
516 | gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data; | |
a994955c | 517 | |
118150f2 | 518 | ngpio = pdata->ngpio; |
3d9edf09 | 519 | |
118150f2 | 520 | clk = devm_clk_get(dev, "gpio"); |
3d9edf09 | 521 | if (IS_ERR(clk)) { |
1a9ef909 | 522 | dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk)); |
474dad54 | 523 | return PTR_ERR(clk); |
3d9edf09 | 524 | } |
eb3744a2 | 525 | |
6dc0048c AY |
526 | ret = clk_prepare_enable(clk); |
527 | if (ret) | |
528 | return ret; | |
3d9edf09 | 529 | |
6075a8b2 | 530 | if (!pdata->gpio_unbanked) { |
a1a3c2d5 | 531 | irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0); |
6075a8b2 GS |
532 | if (irq < 0) { |
533 | dev_err(dev, "Couldn't allocate IRQ numbers\n"); | |
6dc0048c | 534 | clk_disable_unprepare(clk); |
6075a8b2 GS |
535 | return irq; |
536 | } | |
9211ff31 | 537 | |
310a7e60 | 538 | irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0, |
6075a8b2 GS |
539 | &davinci_gpio_irq_ops, |
540 | chips); | |
541 | if (!irq_domain) { | |
542 | dev_err(dev, "Couldn't register an IRQ domain\n"); | |
6dc0048c | 543 | clk_disable_unprepare(clk); |
6075a8b2 GS |
544 | return -ENODEV; |
545 | } | |
9211ff31 LP |
546 | } |
547 | ||
131a10a3 PA |
548 | /* |
549 | * Arrange gpio_to_irq() support, handling either direct IRQs or | |
7a36071e DB |
550 | * banked IRQs. Having GPIOs in the first GPIO bank use direct |
551 | * IRQs, while the others use banked IRQs, would need some setup | |
552 | * tweaks to recognize hardware which can do that. | |
553 | */ | |
b5cf3fd8 K |
554 | chips->chip.to_irq = gpio_to_irq_banked; |
555 | chips->irq_domain = irq_domain; | |
7a36071e DB |
556 | |
557 | /* | |
558 | * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO | |
559 | * controller only handling trigger modes. We currently assume no | |
560 | * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. | |
561 | */ | |
118150f2 | 562 | if (pdata->gpio_unbanked) { |
7a36071e | 563 | /* pass "bank 0" GPIO IRQs to AINTC */ |
b5cf3fd8 | 564 | chips->chip.to_irq = gpio_to_irq_unbanked; |
b5cf3fd8 | 565 | chips->gpio_unbanked = pdata->gpio_unbanked; |
3685bbce | 566 | binten = GENMASK(pdata->gpio_unbanked / 16, 0); |
7a36071e DB |
567 | |
568 | /* AINTC handles mask/unmask; GPIO handles triggering */ | |
eb3744a2 | 569 | irq = chips->irqs[0]; |
0c6feb07 GS |
570 | irq_chip = gpio_get_irq_chip(irq); |
571 | irq_chip->name = "GPIO-AINTC"; | |
572 | irq_chip->irq_set_type = gpio_irq_type_unbanked; | |
7a36071e DB |
573 | |
574 | /* default trigger: both edges */ | |
b5cf3fd8 | 575 | g = chips->regs[0]; |
388291c3 LP |
576 | writel_relaxed(~0, &g->set_falling); |
577 | writel_relaxed(~0, &g->set_rising); | |
7a36071e DB |
578 | |
579 | /* set the direct IRQs up to use that irqchip */ | |
eb3744a2 K |
580 | for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) { |
581 | irq_set_chip(chips->irqs[gpio], irq_chip); | |
582 | irq_set_handler_data(chips->irqs[gpio], chips); | |
583 | irq_set_status_flags(chips->irqs[gpio], | |
584 | IRQ_TYPE_EDGE_BOTH); | |
7a36071e DB |
585 | } |
586 | ||
587 | goto done; | |
588 | } | |
589 | ||
590 | /* | |
591 | * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we | |
592 | * then chain through our own handler. | |
593 | */ | |
eb3744a2 | 594 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) { |
8f7cf8c6 K |
595 | /* disabled by default, enabled only as needed |
596 | * There are register sets for 32 GPIOs. 2 banks of 16 | |
597 | * GPIOs are covered by each set of registers hence divide by 2 | |
598 | */ | |
b5cf3fd8 | 599 | g = chips->regs[bank / 2]; |
388291c3 LP |
600 | writel_relaxed(~0, &g->clr_falling); |
601 | writel_relaxed(~0, &g->clr_rising); | |
3d9edf09 | 602 | |
f299bb95 IY |
603 | /* |
604 | * Each chip handles 32 gpios, and each irq bank consists of 16 | |
605 | * gpio irqs. Pass the irq bank's corresponding controller to | |
606 | * the chained irq handler. | |
607 | */ | |
b5cf3fd8 K |
608 | irqdata = devm_kzalloc(&pdev->dev, |
609 | sizeof(struct | |
610 | davinci_gpio_irq_data), | |
611 | GFP_KERNEL); | |
6dc0048c AY |
612 | if (!irqdata) { |
613 | clk_disable_unprepare(clk); | |
b5cf3fd8 | 614 | return -ENOMEM; |
6dc0048c | 615 | } |
b5cf3fd8 K |
616 | |
617 | irqdata->regs = g; | |
618 | irqdata->bank_num = bank; | |
619 | irqdata->chip = chips; | |
620 | ||
eb3744a2 K |
621 | irq_set_chained_handler_and_data(chips->irqs[bank], |
622 | gpio_irq_handler, irqdata); | |
3d9edf09 | 623 | |
474dad54 | 624 | binten |= BIT(bank); |
3d9edf09 VB |
625 | } |
626 | ||
7a36071e | 627 | done: |
131a10a3 PA |
628 | /* |
629 | * BINTEN -- per-bank interrupt enable. genirq would also let these | |
3d9edf09 VB |
630 | * bits be set/cleared dynamically. |
631 | */ | |
388291c3 | 632 | writel_relaxed(binten, gpio_base + BINTEN); |
3d9edf09 | 633 | |
3d9edf09 VB |
634 | return 0; |
635 | } | |
118150f2 | 636 | |
c770844c | 637 | static const struct of_device_id davinci_gpio_ids[] = { |
0c6feb07 GS |
638 | { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip}, |
639 | { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip}, | |
c770844c KS |
640 | { /* sentinel */ }, |
641 | }; | |
642 | MODULE_DEVICE_TABLE(of, davinci_gpio_ids); | |
c770844c | 643 | |
118150f2 KS |
644 | static struct platform_driver davinci_gpio_driver = { |
645 | .probe = davinci_gpio_probe, | |
646 | .driver = { | |
c770844c | 647 | .name = "davinci_gpio", |
c770844c | 648 | .of_match_table = of_match_ptr(davinci_gpio_ids), |
118150f2 KS |
649 | }, |
650 | }; | |
651 | ||
652 | /** | |
653 | * GPIO driver registration needs to be done before machine_init functions | |
654 | * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall. | |
655 | */ | |
656 | static int __init davinci_gpio_drv_reg(void) | |
657 | { | |
658 | return platform_driver_register(&davinci_gpio_driver); | |
659 | } | |
660 | postcore_initcall(davinci_gpio_drv_reg); |