Commit | Line | Data |
---|---|---|
3d9edf09 VB |
1 | /* |
2 | * TI DaVinci GPIO Support | |
3 | * | |
dce1115b | 4 | * Copyright (c) 2006-2007 David Brownell |
3d9edf09 VB |
5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
2f8163ba | 12 | #include <linux/gpio.h> |
3d9edf09 VB |
13 | #include <linux/errno.h> |
14 | #include <linux/kernel.h> | |
3d9edf09 VB |
15 | #include <linux/clk.h> |
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
118150f2 KS |
18 | #include <linux/irq.h> |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/platform_data/gpio-davinci.h> | |
3d9edf09 | 21 | |
c12f415a CC |
22 | struct davinci_gpio_regs { |
23 | u32 dir; | |
24 | u32 out_data; | |
25 | u32 set_data; | |
26 | u32 clr_data; | |
27 | u32 in_data; | |
28 | u32 set_rising; | |
29 | u32 clr_rising; | |
30 | u32 set_falling; | |
31 | u32 clr_falling; | |
32 | u32 intstat; | |
33 | }; | |
34 | ||
131a10a3 PA |
35 | #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ |
36 | ||
ba4a984e | 37 | #define chip2controller(chip) \ |
99e9e52d | 38 | container_of(chip, struct davinci_gpio_controller, chip) |
ba4a984e | 39 | |
b8d44293 | 40 | static void __iomem *gpio_base; |
3d9edf09 | 41 | |
118150f2 | 42 | static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio) |
3d9edf09 | 43 | { |
c12f415a | 44 | void __iomem *ptr; |
c12f415a CC |
45 | |
46 | if (gpio < 32 * 1) | |
b8d44293 | 47 | ptr = gpio_base + 0x10; |
c12f415a | 48 | else if (gpio < 32 * 2) |
b8d44293 | 49 | ptr = gpio_base + 0x38; |
c12f415a | 50 | else if (gpio < 32 * 3) |
b8d44293 | 51 | ptr = gpio_base + 0x60; |
c12f415a | 52 | else if (gpio < 32 * 4) |
b8d44293 | 53 | ptr = gpio_base + 0x88; |
c12f415a | 54 | else if (gpio < 32 * 5) |
b8d44293 | 55 | ptr = gpio_base + 0xb0; |
c12f415a CC |
56 | else |
57 | ptr = NULL; | |
58 | return ptr; | |
3d9edf09 VB |
59 | } |
60 | ||
99e9e52d | 61 | static inline struct davinci_gpio_regs __iomem *irq2regs(int irq) |
21ce873d | 62 | { |
99e9e52d | 63 | struct davinci_gpio_regs __iomem *g; |
21ce873d | 64 | |
6845664a | 65 | g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq); |
21ce873d KH |
66 | |
67 | return g; | |
68 | } | |
69 | ||
118150f2 | 70 | static int davinci_gpio_irq_setup(struct platform_device *pdev); |
dce1115b DB |
71 | |
72 | /*--------------------------------------------------------------------------*/ | |
73 | ||
5b3a05ca | 74 | /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ |
ba4a984e CC |
75 | static inline int __davinci_direction(struct gpio_chip *chip, |
76 | unsigned offset, bool out, int value) | |
3d9edf09 | 77 | { |
99e9e52d CC |
78 | struct davinci_gpio_controller *d = chip2controller(chip); |
79 | struct davinci_gpio_regs __iomem *g = d->regs; | |
b27b6d03 | 80 | unsigned long flags; |
dce1115b | 81 | u32 temp; |
ba4a984e | 82 | u32 mask = 1 << offset; |
3d9edf09 | 83 | |
b27b6d03 | 84 | spin_lock_irqsave(&d->lock, flags); |
dce1115b | 85 | temp = __raw_readl(&g->dir); |
ba4a984e CC |
86 | if (out) { |
87 | temp &= ~mask; | |
88 | __raw_writel(mask, value ? &g->set_data : &g->clr_data); | |
89 | } else { | |
90 | temp |= mask; | |
91 | } | |
dce1115b | 92 | __raw_writel(temp, &g->dir); |
b27b6d03 | 93 | spin_unlock_irqrestore(&d->lock, flags); |
3d9edf09 | 94 | |
dce1115b DB |
95 | return 0; |
96 | } | |
3d9edf09 | 97 | |
ba4a984e CC |
98 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) |
99 | { | |
100 | return __davinci_direction(chip, offset, false, 0); | |
101 | } | |
102 | ||
103 | static int | |
104 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) | |
105 | { | |
106 | return __davinci_direction(chip, offset, true, value); | |
107 | } | |
108 | ||
3d9edf09 VB |
109 | /* |
110 | * Read the pin's value (works even if it's set up as output); | |
111 | * returns zero/nonzero. | |
112 | * | |
113 | * Note that changes are synched to the GPIO clock, so reading values back | |
114 | * right after you've set them may give old values. | |
115 | */ | |
dce1115b | 116 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
3d9edf09 | 117 | { |
99e9e52d CC |
118 | struct davinci_gpio_controller *d = chip2controller(chip); |
119 | struct davinci_gpio_regs __iomem *g = d->regs; | |
3d9edf09 | 120 | |
dce1115b | 121 | return (1 << offset) & __raw_readl(&g->in_data); |
3d9edf09 | 122 | } |
3d9edf09 | 123 | |
dce1115b DB |
124 | /* |
125 | * Assuming the pin is muxed as a gpio output, set its output value. | |
126 | */ | |
127 | static void | |
128 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
3d9edf09 | 129 | { |
99e9e52d CC |
130 | struct davinci_gpio_controller *d = chip2controller(chip); |
131 | struct davinci_gpio_regs __iomem *g = d->regs; | |
3d9edf09 | 132 | |
dce1115b DB |
133 | __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); |
134 | } | |
135 | ||
118150f2 | 136 | static int davinci_gpio_probe(struct platform_device *pdev) |
dce1115b DB |
137 | { |
138 | int i, base; | |
a994955c | 139 | unsigned ngpio; |
118150f2 KS |
140 | struct davinci_gpio_controller *chips; |
141 | struct davinci_gpio_platform_data *pdata; | |
142 | struct davinci_gpio_regs __iomem *regs; | |
143 | struct device *dev = &pdev->dev; | |
144 | struct resource *res; | |
145 | ||
146 | pdata = dev->platform_data; | |
147 | if (!pdata) { | |
148 | dev_err(dev, "No platform data found\n"); | |
149 | return -EINVAL; | |
150 | } | |
686b634a | 151 | |
a994955c MG |
152 | /* |
153 | * The gpio banks conceptually expose a segmented bitmap, | |
474dad54 DB |
154 | * and "ngpio" is one more than the largest zero-based |
155 | * bit index that's valid. | |
156 | */ | |
118150f2 | 157 | ngpio = pdata->ngpio; |
a994955c | 158 | if (ngpio == 0) { |
118150f2 | 159 | dev_err(dev, "How many GPIOs?\n"); |
474dad54 DB |
160 | return -EINVAL; |
161 | } | |
162 | ||
163 | if (WARN_ON(DAVINCI_N_GPIO < ngpio)) | |
164 | ngpio = DAVINCI_N_GPIO; | |
165 | ||
118150f2 KS |
166 | chips = devm_kzalloc(dev, |
167 | ngpio * sizeof(struct davinci_gpio_controller), | |
168 | GFP_KERNEL); | |
169 | if (!chips) { | |
170 | dev_err(dev, "Memory allocation failed\n"); | |
b8d44293 | 171 | return -ENOMEM; |
118150f2 KS |
172 | } |
173 | ||
174 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
175 | if (!res) { | |
176 | dev_err(dev, "Invalid memory resource\n"); | |
177 | return -EBUSY; | |
178 | } | |
179 | ||
180 | gpio_base = devm_ioremap_resource(dev, res); | |
181 | if (IS_ERR(gpio_base)) | |
182 | return PTR_ERR(gpio_base); | |
b8d44293 | 183 | |
474dad54 | 184 | for (i = 0, base = 0; base < ngpio; i++, base += 32) { |
dce1115b DB |
185 | chips[i].chip.label = "DaVinci"; |
186 | ||
187 | chips[i].chip.direction_input = davinci_direction_in; | |
188 | chips[i].chip.get = davinci_gpio_get; | |
189 | chips[i].chip.direction_output = davinci_direction_out; | |
190 | chips[i].chip.set = davinci_gpio_set; | |
191 | ||
192 | chips[i].chip.base = base; | |
474dad54 | 193 | chips[i].chip.ngpio = ngpio - base; |
dce1115b DB |
194 | if (chips[i].chip.ngpio > 32) |
195 | chips[i].chip.ngpio = 32; | |
196 | ||
b27b6d03 CC |
197 | spin_lock_init(&chips[i].lock); |
198 | ||
c12f415a CC |
199 | regs = gpio2regs(base); |
200 | chips[i].regs = regs; | |
201 | chips[i].set_data = ®s->set_data; | |
202 | chips[i].clr_data = ®s->clr_data; | |
203 | chips[i].in_data = ®s->in_data; | |
dce1115b DB |
204 | |
205 | gpiochip_add(&chips[i].chip); | |
206 | } | |
3d9edf09 | 207 | |
118150f2 KS |
208 | platform_set_drvdata(pdev, chips); |
209 | davinci_gpio_irq_setup(pdev); | |
3d9edf09 VB |
210 | return 0; |
211 | } | |
3d9edf09 | 212 | |
dce1115b | 213 | /*--------------------------------------------------------------------------*/ |
3d9edf09 VB |
214 | /* |
215 | * We expect irqs will normally be set up as input pins, but they can also be | |
216 | * used as output pins ... which is convenient for testing. | |
217 | * | |
474dad54 | 218 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
7a36071e | 219 | * to their GPIOBNK0 irq, with a bit less overhead. |
3d9edf09 | 220 | * |
474dad54 | 221 | * All those INTC hookups (direct, plus several IRQ banks) can also |
3d9edf09 VB |
222 | * serve as EDMA event triggers. |
223 | */ | |
224 | ||
23265442 | 225 | static void gpio_irq_disable(struct irq_data *d) |
3d9edf09 | 226 | { |
23265442 | 227 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
6845664a | 228 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
3d9edf09 VB |
229 | |
230 | __raw_writel(mask, &g->clr_falling); | |
231 | __raw_writel(mask, &g->clr_rising); | |
232 | } | |
233 | ||
23265442 | 234 | static void gpio_irq_enable(struct irq_data *d) |
3d9edf09 | 235 | { |
23265442 | 236 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
6845664a | 237 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
5093aec8 | 238 | unsigned status = irqd_get_trigger_type(d); |
3d9edf09 | 239 | |
df4aab46 DB |
240 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
241 | if (!status) | |
242 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | |
243 | ||
244 | if (status & IRQ_TYPE_EDGE_FALLING) | |
3d9edf09 | 245 | __raw_writel(mask, &g->set_falling); |
df4aab46 | 246 | if (status & IRQ_TYPE_EDGE_RISING) |
3d9edf09 VB |
247 | __raw_writel(mask, &g->set_rising); |
248 | } | |
249 | ||
23265442 | 250 | static int gpio_irq_type(struct irq_data *d, unsigned trigger) |
3d9edf09 | 251 | { |
3d9edf09 VB |
252 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
253 | return -EINVAL; | |
254 | ||
3d9edf09 VB |
255 | return 0; |
256 | } | |
257 | ||
258 | static struct irq_chip gpio_irqchip = { | |
259 | .name = "GPIO", | |
23265442 LB |
260 | .irq_enable = gpio_irq_enable, |
261 | .irq_disable = gpio_irq_disable, | |
262 | .irq_set_type = gpio_irq_type, | |
5093aec8 | 263 | .flags = IRQCHIP_SET_TYPE_MASKED, |
3d9edf09 VB |
264 | }; |
265 | ||
266 | static void | |
267 | gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |
268 | { | |
74164016 | 269 | struct davinci_gpio_regs __iomem *g; |
3d9edf09 | 270 | u32 mask = 0xffff; |
f299bb95 | 271 | struct davinci_gpio_controller *d; |
3d9edf09 | 272 | |
f299bb95 IY |
273 | d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc); |
274 | g = (struct davinci_gpio_regs __iomem *)d->regs; | |
74164016 | 275 | |
3d9edf09 VB |
276 | /* we only care about one bank */ |
277 | if (irq & 1) | |
278 | mask <<= 16; | |
279 | ||
280 | /* temporarily mask (level sensitive) parent IRQ */ | |
23265442 LB |
281 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
282 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
3d9edf09 VB |
283 | while (1) { |
284 | u32 status; | |
3d9edf09 VB |
285 | int n; |
286 | int res; | |
287 | ||
288 | /* ack any irqs */ | |
289 | status = __raw_readl(&g->intstat) & mask; | |
290 | if (!status) | |
291 | break; | |
292 | __raw_writel(status, &g->intstat); | |
3d9edf09 VB |
293 | |
294 | /* now demux them to the right lowlevel handler */ | |
f299bb95 IY |
295 | n = d->irq_base; |
296 | if (irq & 1) { | |
297 | n += 16; | |
298 | status >>= 16; | |
299 | } | |
300 | ||
3d9edf09 VB |
301 | while (status) { |
302 | res = ffs(status); | |
303 | n += res; | |
d8aa0251 | 304 | generic_handle_irq(n - 1); |
3d9edf09 VB |
305 | status >>= res; |
306 | } | |
307 | } | |
23265442 | 308 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
3d9edf09 VB |
309 | /* now it may re-trigger */ |
310 | } | |
311 | ||
7a36071e DB |
312 | static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) |
313 | { | |
99e9e52d | 314 | struct davinci_gpio_controller *d = chip2controller(chip); |
7a36071e DB |
315 | |
316 | if (d->irq_base >= 0) | |
317 | return d->irq_base + offset; | |
318 | else | |
319 | return -ENODEV; | |
320 | } | |
321 | ||
322 | static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) | |
323 | { | |
118150f2 | 324 | struct davinci_gpio_controller *d = chip2controller(chip); |
7a36071e | 325 | |
131a10a3 PA |
326 | /* |
327 | * NOTE: we assume for now that only irqs in the first gpio_chip | |
7a36071e DB |
328 | * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). |
329 | */ | |
118150f2 KS |
330 | if (offset < d->irq_base) |
331 | return d->gpio_irq + offset; | |
7a36071e DB |
332 | else |
333 | return -ENODEV; | |
334 | } | |
335 | ||
ab2dde99 | 336 | static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) |
7a36071e | 337 | { |
ab2dde99 SN |
338 | struct davinci_gpio_controller *d; |
339 | struct davinci_gpio_regs __iomem *g; | |
ab2dde99 SN |
340 | u32 mask; |
341 | ||
342 | d = (struct davinci_gpio_controller *)data->handler_data; | |
343 | g = (struct davinci_gpio_regs __iomem *)d->regs; | |
118150f2 | 344 | mask = __gpio_mask(data->irq - d->gpio_irq); |
7a36071e DB |
345 | |
346 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
347 | return -EINVAL; | |
348 | ||
349 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) | |
350 | ? &g->set_falling : &g->clr_falling); | |
351 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) | |
352 | ? &g->set_rising : &g->clr_rising); | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
3d9edf09 | 357 | /* |
474dad54 DB |
358 | * NOTE: for suspend/resume, probably best to make a platform_device with |
359 | * suspend_late/resume_resume calls hooking into results of the set_wake() | |
3d9edf09 VB |
360 | * calls ... so if no gpios are wakeup events the clock can be disabled, |
361 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 | |
474dad54 | 362 | * (dm6446) can be set appropriately for GPIOV33 pins. |
3d9edf09 VB |
363 | */ |
364 | ||
118150f2 | 365 | static int davinci_gpio_irq_setup(struct platform_device *pdev) |
3d9edf09 VB |
366 | { |
367 | unsigned gpio, irq, bank; | |
368 | struct clk *clk; | |
474dad54 | 369 | u32 binten = 0; |
a994955c | 370 | unsigned ngpio, bank_irq; |
118150f2 KS |
371 | struct device *dev = &pdev->dev; |
372 | struct resource *res; | |
373 | struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); | |
374 | struct davinci_gpio_platform_data *pdata = dev->platform_data; | |
375 | struct davinci_gpio_regs __iomem *g; | |
a994955c | 376 | |
118150f2 KS |
377 | ngpio = pdata->ngpio; |
378 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
379 | if (!res) { | |
380 | dev_err(dev, "Invalid IRQ resource\n"); | |
381 | return -EBUSY; | |
382 | } | |
474dad54 | 383 | |
118150f2 KS |
384 | bank_irq = res->start; |
385 | ||
386 | if (!bank_irq) { | |
387 | dev_err(dev, "Invalid IRQ resource\n"); | |
388 | return -ENODEV; | |
474dad54 | 389 | } |
3d9edf09 | 390 | |
118150f2 | 391 | clk = devm_clk_get(dev, "gpio"); |
3d9edf09 VB |
392 | if (IS_ERR(clk)) { |
393 | printk(KERN_ERR "Error %ld getting gpio clock?\n", | |
394 | PTR_ERR(clk)); | |
474dad54 | 395 | return PTR_ERR(clk); |
3d9edf09 | 396 | } |
ce6b658d | 397 | clk_prepare_enable(clk); |
3d9edf09 | 398 | |
131a10a3 PA |
399 | /* |
400 | * Arrange gpio_to_irq() support, handling either direct IRQs or | |
7a36071e DB |
401 | * banked IRQs. Having GPIOs in the first GPIO bank use direct |
402 | * IRQs, while the others use banked IRQs, would need some setup | |
403 | * tweaks to recognize hardware which can do that. | |
404 | */ | |
405 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { | |
406 | chips[bank].chip.to_irq = gpio_to_irq_banked; | |
118150f2 | 407 | chips[bank].irq_base = pdata->gpio_unbanked |
7a36071e | 408 | ? -EINVAL |
118150f2 | 409 | : (pdata->intc_irq_num + gpio); |
7a36071e DB |
410 | } |
411 | ||
412 | /* | |
413 | * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO | |
414 | * controller only handling trigger modes. We currently assume no | |
415 | * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. | |
416 | */ | |
118150f2 | 417 | if (pdata->gpio_unbanked) { |
81b279d8 | 418 | static struct irq_chip_type gpio_unbanked; |
7a36071e DB |
419 | |
420 | /* pass "bank 0" GPIO IRQs to AINTC */ | |
421 | chips[0].chip.to_irq = gpio_to_irq_unbanked; | |
422 | binten = BIT(0); | |
423 | ||
424 | /* AINTC handles mask/unmask; GPIO handles triggering */ | |
425 | irq = bank_irq; | |
81b279d8 SN |
426 | gpio_unbanked = *container_of(irq_get_chip(irq), |
427 | struct irq_chip_type, chip); | |
428 | gpio_unbanked.chip.name = "GPIO-AINTC"; | |
429 | gpio_unbanked.chip.irq_set_type = gpio_irq_type_unbanked; | |
7a36071e DB |
430 | |
431 | /* default trigger: both edges */ | |
99e9e52d | 432 | g = gpio2regs(0); |
7a36071e DB |
433 | __raw_writel(~0, &g->set_falling); |
434 | __raw_writel(~0, &g->set_rising); | |
435 | ||
436 | /* set the direct IRQs up to use that irqchip */ | |
118150f2 | 437 | for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) { |
81b279d8 | 438 | irq_set_chip(irq, &gpio_unbanked.chip); |
ab2dde99 | 439 | irq_set_handler_data(irq, &chips[gpio / 32]); |
5093aec8 | 440 | irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); |
7a36071e DB |
441 | } |
442 | ||
443 | goto done; | |
444 | } | |
445 | ||
446 | /* | |
447 | * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we | |
448 | * then chain through our own handler. | |
449 | */ | |
474dad54 DB |
450 | for (gpio = 0, irq = gpio_to_irq(0), bank = 0; |
451 | gpio < ngpio; | |
452 | bank++, bank_irq++) { | |
3d9edf09 VB |
453 | unsigned i; |
454 | ||
7a36071e | 455 | /* disabled by default, enabled only as needed */ |
99e9e52d | 456 | g = gpio2regs(gpio); |
3d9edf09 VB |
457 | __raw_writel(~0, &g->clr_falling); |
458 | __raw_writel(~0, &g->clr_rising); | |
459 | ||
460 | /* set up all irqs in this bank */ | |
6845664a | 461 | irq_set_chained_handler(bank_irq, gpio_irq_handler); |
f299bb95 IY |
462 | |
463 | /* | |
464 | * Each chip handles 32 gpios, and each irq bank consists of 16 | |
465 | * gpio irqs. Pass the irq bank's corresponding controller to | |
466 | * the chained irq handler. | |
467 | */ | |
468 | irq_set_handler_data(bank_irq, &chips[gpio / 32]); | |
3d9edf09 | 469 | |
474dad54 | 470 | for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { |
6845664a TG |
471 | irq_set_chip(irq, &gpio_irqchip); |
472 | irq_set_chip_data(irq, (__force void *)g); | |
473 | irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); | |
474 | irq_set_handler(irq, handle_simple_irq); | |
3d9edf09 VB |
475 | set_irq_flags(irq, IRQF_VALID); |
476 | } | |
474dad54 DB |
477 | |
478 | binten |= BIT(bank); | |
3d9edf09 VB |
479 | } |
480 | ||
7a36071e | 481 | done: |
131a10a3 PA |
482 | /* |
483 | * BINTEN -- per-bank interrupt enable. genirq would also let these | |
3d9edf09 VB |
484 | * bits be set/cleared dynamically. |
485 | */ | |
131a10a3 | 486 | __raw_writel(binten, gpio_base + BINTEN); |
3d9edf09 VB |
487 | |
488 | printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); | |
489 | ||
490 | return 0; | |
491 | } | |
118150f2 KS |
492 | |
493 | static struct platform_driver davinci_gpio_driver = { | |
494 | .probe = davinci_gpio_probe, | |
495 | .driver = { | |
496 | .name = "davinci_gpio", | |
497 | .owner = THIS_MODULE, | |
498 | }, | |
499 | }; | |
500 | ||
501 | /** | |
502 | * GPIO driver registration needs to be done before machine_init functions | |
503 | * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall. | |
504 | */ | |
505 | static int __init davinci_gpio_drv_reg(void) | |
506 | { | |
507 | return platform_driver_register(&davinci_gpio_driver); | |
508 | } | |
509 | postcore_initcall(davinci_gpio_drv_reg); |