Commit | Line | Data |
---|---|---|
2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
3d9edf09 VB |
2 | /* |
3 | * TI DaVinci GPIO Support | |
4 | * | |
dce1115b | 5 | * Copyright (c) 2006-2007 David Brownell |
3d9edf09 | 6 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> |
3d9edf09 | 7 | */ |
79b73ff9 | 8 | |
7220c43a | 9 | #include <linux/gpio/driver.h> |
3d9edf09 VB |
10 | #include <linux/errno.h> |
11 | #include <linux/kernel.h> | |
3d9edf09 VB |
12 | #include <linux/clk.h> |
13 | #include <linux/err.h> | |
14 | #include <linux/io.h> | |
118150f2 | 15 | #include <linux/irq.h> |
9211ff31 | 16 | #include <linux/irqdomain.h> |
c770844c KS |
17 | #include <linux/module.h> |
18 | #include <linux/of.h> | |
19 | #include <linux/of_device.h> | |
3c87d7c8 | 20 | #include <linux/pinctrl/consumer.h> |
118150f2 KS |
21 | #include <linux/platform_device.h> |
22 | #include <linux/platform_data/gpio-davinci.h> | |
0d978eb7 | 23 | #include <linux/irqchip/chained_irq.h> |
79b73ff9 AD |
24 | #include <linux/spinlock.h> |
25 | ||
26 | #include <asm-generic/gpio.h> | |
27 | ||
28 | #define MAX_REGS_BANKS 5 | |
29 | #define MAX_INT_PER_BANK 32 | |
3d9edf09 | 30 | |
c12f415a CC |
31 | struct davinci_gpio_regs { |
32 | u32 dir; | |
33 | u32 out_data; | |
34 | u32 set_data; | |
35 | u32 clr_data; | |
36 | u32 in_data; | |
37 | u32 set_rising; | |
38 | u32 clr_rising; | |
39 | u32 set_falling; | |
40 | u32 clr_falling; | |
41 | u32 intstat; | |
42 | }; | |
43 | ||
0c6feb07 GS |
44 | typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq); |
45 | ||
131a10a3 PA |
46 | #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ |
47 | ||
b8d44293 | 48 | static void __iomem *gpio_base; |
8f7cf8c6 | 49 | static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0}; |
3d9edf09 | 50 | |
79b73ff9 AD |
51 | struct davinci_gpio_irq_data { |
52 | void __iomem *regs; | |
53 | struct davinci_gpio_controller *chip; | |
54 | int bank_num; | |
55 | }; | |
56 | ||
57 | struct davinci_gpio_controller { | |
58 | struct gpio_chip chip; | |
59 | struct irq_domain *irq_domain; | |
60 | /* Serialize access to GPIO registers */ | |
61 | spinlock_t lock; | |
62 | void __iomem *regs[MAX_REGS_BANKS]; | |
63 | int gpio_unbanked; | |
64 | int irqs[MAX_INT_PER_BANK]; | |
65 | }; | |
66 | ||
67 | static inline u32 __gpio_mask(unsigned gpio) | |
68 | { | |
69 | return 1 << (gpio % 32); | |
70 | } | |
71 | ||
1765d671 | 72 | static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d) |
21ce873d | 73 | { |
99e9e52d | 74 | struct davinci_gpio_regs __iomem *g; |
21ce873d | 75 | |
1765d671 | 76 | g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d); |
21ce873d KH |
77 | |
78 | return g; | |
79 | } | |
80 | ||
eb3744a2 | 81 | static int davinci_gpio_irq_setup(struct platform_device *pdev); |
dce1115b DB |
82 | |
83 | /*--------------------------------------------------------------------------*/ | |
84 | ||
5b3a05ca | 85 | /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ |
ba4a984e CC |
86 | static inline int __davinci_direction(struct gpio_chip *chip, |
87 | unsigned offset, bool out, int value) | |
3d9edf09 | 88 | { |
72a1ca2c | 89 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
b5cf3fd8 | 90 | struct davinci_gpio_regs __iomem *g; |
b27b6d03 | 91 | unsigned long flags; |
dce1115b | 92 | u32 temp; |
b5cf3fd8 K |
93 | int bank = offset / 32; |
94 | u32 mask = __gpio_mask(offset); | |
3d9edf09 | 95 | |
b5cf3fd8 | 96 | g = d->regs[bank]; |
b27b6d03 | 97 | spin_lock_irqsave(&d->lock, flags); |
388291c3 | 98 | temp = readl_relaxed(&g->dir); |
ba4a984e CC |
99 | if (out) { |
100 | temp &= ~mask; | |
388291c3 | 101 | writel_relaxed(mask, value ? &g->set_data : &g->clr_data); |
ba4a984e CC |
102 | } else { |
103 | temp |= mask; | |
104 | } | |
388291c3 | 105 | writel_relaxed(temp, &g->dir); |
b27b6d03 | 106 | spin_unlock_irqrestore(&d->lock, flags); |
3d9edf09 | 107 | |
dce1115b DB |
108 | return 0; |
109 | } | |
3d9edf09 | 110 | |
ba4a984e CC |
111 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) |
112 | { | |
113 | return __davinci_direction(chip, offset, false, 0); | |
114 | } | |
115 | ||
116 | static int | |
117 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) | |
118 | { | |
119 | return __davinci_direction(chip, offset, true, value); | |
120 | } | |
121 | ||
3d9edf09 VB |
122 | /* |
123 | * Read the pin's value (works even if it's set up as output); | |
124 | * returns zero/nonzero. | |
125 | * | |
126 | * Note that changes are synched to the GPIO clock, so reading values back | |
127 | * right after you've set them may give old values. | |
128 | */ | |
dce1115b | 129 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
3d9edf09 | 130 | { |
72a1ca2c | 131 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
b5cf3fd8 K |
132 | struct davinci_gpio_regs __iomem *g; |
133 | int bank = offset / 32; | |
3d9edf09 | 134 | |
b5cf3fd8 K |
135 | g = d->regs[bank]; |
136 | ||
137 | return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data)); | |
3d9edf09 | 138 | } |
3d9edf09 | 139 | |
dce1115b DB |
140 | /* |
141 | * Assuming the pin is muxed as a gpio output, set its output value. | |
142 | */ | |
143 | static void | |
144 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
3d9edf09 | 145 | { |
72a1ca2c | 146 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
b5cf3fd8 K |
147 | struct davinci_gpio_regs __iomem *g; |
148 | int bank = offset / 32; | |
3d9edf09 | 149 | |
b5cf3fd8 K |
150 | g = d->regs[bank]; |
151 | ||
152 | writel_relaxed(__gpio_mask(offset), | |
153 | value ? &g->set_data : &g->clr_data); | |
dce1115b DB |
154 | } |
155 | ||
c770844c KS |
156 | static struct davinci_gpio_platform_data * |
157 | davinci_gpio_get_pdata(struct platform_device *pdev) | |
158 | { | |
159 | struct device_node *dn = pdev->dev.of_node; | |
160 | struct davinci_gpio_platform_data *pdata; | |
161 | int ret; | |
162 | u32 val; | |
163 | ||
164 | if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) | |
ab128afc | 165 | return dev_get_platdata(&pdev->dev); |
c770844c KS |
166 | |
167 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
168 | if (!pdata) | |
169 | return NULL; | |
170 | ||
171 | ret = of_property_read_u32(dn, "ti,ngpio", &val); | |
172 | if (ret) | |
173 | goto of_err; | |
174 | ||
175 | pdata->ngpio = val; | |
176 | ||
177 | ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val); | |
178 | if (ret) | |
179 | goto of_err; | |
180 | ||
181 | pdata->gpio_unbanked = val; | |
182 | ||
183 | return pdata; | |
184 | ||
185 | of_err: | |
186 | dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret); | |
187 | return NULL; | |
188 | } | |
189 | ||
118150f2 | 190 | static int davinci_gpio_probe(struct platform_device *pdev) |
dce1115b | 191 | { |
c809e37a | 192 | int bank, i, ret = 0; |
eb3744a2 | 193 | unsigned int ngpio, nbank, nirq; |
118150f2 KS |
194 | struct davinci_gpio_controller *chips; |
195 | struct davinci_gpio_platform_data *pdata; | |
118150f2 | 196 | struct device *dev = &pdev->dev; |
118150f2 | 197 | |
c770844c | 198 | pdata = davinci_gpio_get_pdata(pdev); |
118150f2 KS |
199 | if (!pdata) { |
200 | dev_err(dev, "No platform data found\n"); | |
201 | return -EINVAL; | |
202 | } | |
686b634a | 203 | |
c770844c KS |
204 | dev->platform_data = pdata; |
205 | ||
a994955c MG |
206 | /* |
207 | * The gpio banks conceptually expose a segmented bitmap, | |
474dad54 DB |
208 | * and "ngpio" is one more than the largest zero-based |
209 | * bit index that's valid. | |
210 | */ | |
118150f2 | 211 | ngpio = pdata->ngpio; |
a994955c | 212 | if (ngpio == 0) { |
118150f2 | 213 | dev_err(dev, "How many GPIOs?\n"); |
474dad54 DB |
214 | return -EINVAL; |
215 | } | |
216 | ||
c21d500b GS |
217 | if (WARN_ON(ARCH_NR_GPIOS < ngpio)) |
218 | ngpio = ARCH_NR_GPIOS; | |
474dad54 | 219 | |
eb3744a2 K |
220 | /* |
221 | * If there are unbanked interrupts then the number of | |
222 | * interrupts is equal to number of gpios else all are banked so | |
223 | * number of interrupts is equal to number of banks(each with 16 gpios) | |
224 | */ | |
225 | if (pdata->gpio_unbanked) | |
226 | nirq = pdata->gpio_unbanked; | |
227 | else | |
228 | nirq = DIV_ROUND_UP(ngpio, 16); | |
229 | ||
c809e37a | 230 | chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL); |
9ea9363c | 231 | if (!chips) |
b8d44293 | 232 | return -ENOMEM; |
118150f2 | 233 | |
fa7569c8 | 234 | gpio_base = devm_platform_ioremap_resource(pdev, 0); |
118150f2 KS |
235 | if (IS_ERR(gpio_base)) |
236 | return PTR_ERR(gpio_base); | |
b8d44293 | 237 | |
eb3744a2 K |
238 | for (i = 0; i < nirq; i++) { |
239 | chips->irqs[i] = platform_get_irq(pdev, i); | |
240 | if (chips->irqs[i] < 0) { | |
541e4095 K |
241 | if (chips->irqs[i] != -EPROBE_DEFER) |
242 | dev_info(dev, "IRQ not populated, err = %d\n", | |
243 | chips->irqs[i]); | |
eb3744a2 K |
244 | return chips->irqs[i]; |
245 | } | |
c1d013a7 K |
246 | } |
247 | ||
587f7a69 | 248 | chips->chip.label = dev_name(dev); |
dce1115b | 249 | |
b5cf3fd8 K |
250 | chips->chip.direction_input = davinci_direction_in; |
251 | chips->chip.get = davinci_gpio_get; | |
252 | chips->chip.direction_output = davinci_direction_out; | |
253 | chips->chip.set = davinci_gpio_set; | |
dce1115b | 254 | |
b5cf3fd8 | 255 | chips->chip.ngpio = ngpio; |
786a9ab1 | 256 | chips->chip.base = pdata->no_auto_base ? pdata->base : -1; |
dce1115b | 257 | |
c770844c | 258 | #ifdef CONFIG_OF_GPIO |
b5cf3fd8 | 259 | chips->chip.of_gpio_n_cells = 2; |
b5cf3fd8 K |
260 | chips->chip.parent = dev; |
261 | chips->chip.of_node = dev->of_node; | |
3c87d7c8 DL |
262 | |
263 | if (of_property_read_bool(dev->of_node, "gpio-ranges")) { | |
264 | chips->chip.request = gpiochip_generic_request; | |
265 | chips->chip.free = gpiochip_generic_free; | |
266 | } | |
c770844c | 267 | #endif |
b5cf3fd8 | 268 | spin_lock_init(&chips->lock); |
dce1115b | 269 | |
c809e37a AD |
270 | nbank = DIV_ROUND_UP(ngpio, 32); |
271 | for (bank = 0; bank < nbank; bank++) | |
b5cf3fd8 | 272 | chips->regs[bank] = gpio_base + offset_array[bank]; |
3d9edf09 | 273 | |
8327e1ba K |
274 | ret = devm_gpiochip_add_data(dev, &chips->chip, chips); |
275 | if (ret) | |
587f7a69 | 276 | return ret; |
8327e1ba | 277 | |
118150f2 | 278 | platform_set_drvdata(pdev, chips); |
eb3744a2 | 279 | ret = davinci_gpio_irq_setup(pdev); |
5e7a0ce7 | 280 | if (ret) |
587f7a69 | 281 | return ret; |
5e7a0ce7 | 282 | |
3d9edf09 VB |
283 | return 0; |
284 | } | |
3d9edf09 | 285 | |
dce1115b | 286 | /*--------------------------------------------------------------------------*/ |
3d9edf09 VB |
287 | /* |
288 | * We expect irqs will normally be set up as input pins, but they can also be | |
289 | * used as output pins ... which is convenient for testing. | |
290 | * | |
474dad54 | 291 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
7a36071e | 292 | * to their GPIOBNK0 irq, with a bit less overhead. |
3d9edf09 | 293 | * |
474dad54 | 294 | * All those INTC hookups (direct, plus several IRQ banks) can also |
3d9edf09 VB |
295 | * serve as EDMA event triggers. |
296 | */ | |
297 | ||
23265442 | 298 | static void gpio_irq_disable(struct irq_data *d) |
3d9edf09 | 299 | { |
1765d671 | 300 | struct davinci_gpio_regs __iomem *g = irq2regs(d); |
36c05519 | 301 | uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d); |
3d9edf09 | 302 | |
388291c3 LP |
303 | writel_relaxed(mask, &g->clr_falling); |
304 | writel_relaxed(mask, &g->clr_rising); | |
3d9edf09 VB |
305 | } |
306 | ||
23265442 | 307 | static void gpio_irq_enable(struct irq_data *d) |
3d9edf09 | 308 | { |
1765d671 | 309 | struct davinci_gpio_regs __iomem *g = irq2regs(d); |
36c05519 | 310 | uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d); |
5093aec8 | 311 | unsigned status = irqd_get_trigger_type(d); |
3d9edf09 | 312 | |
df4aab46 DB |
313 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
314 | if (!status) | |
315 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | |
316 | ||
317 | if (status & IRQ_TYPE_EDGE_FALLING) | |
388291c3 | 318 | writel_relaxed(mask, &g->set_falling); |
df4aab46 | 319 | if (status & IRQ_TYPE_EDGE_RISING) |
388291c3 | 320 | writel_relaxed(mask, &g->set_rising); |
3d9edf09 VB |
321 | } |
322 | ||
23265442 | 323 | static int gpio_irq_type(struct irq_data *d, unsigned trigger) |
3d9edf09 | 324 | { |
3d9edf09 VB |
325 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
326 | return -EINVAL; | |
327 | ||
3d9edf09 VB |
328 | return 0; |
329 | } | |
330 | ||
331 | static struct irq_chip gpio_irqchip = { | |
332 | .name = "GPIO", | |
23265442 LB |
333 | .irq_enable = gpio_irq_enable, |
334 | .irq_disable = gpio_irq_disable, | |
335 | .irq_set_type = gpio_irq_type, | |
5093aec8 | 336 | .flags = IRQCHIP_SET_TYPE_MASKED, |
3d9edf09 VB |
337 | }; |
338 | ||
bd0b9ac4 | 339 | static void gpio_irq_handler(struct irq_desc *desc) |
3d9edf09 | 340 | { |
74164016 | 341 | struct davinci_gpio_regs __iomem *g; |
3d9edf09 | 342 | u32 mask = 0xffff; |
b5cf3fd8 | 343 | int bank_num; |
f299bb95 | 344 | struct davinci_gpio_controller *d; |
b5cf3fd8 | 345 | struct davinci_gpio_irq_data *irqdata; |
3d9edf09 | 346 | |
b5cf3fd8 K |
347 | irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc); |
348 | bank_num = irqdata->bank_num; | |
349 | g = irqdata->regs; | |
350 | d = irqdata->chip; | |
74164016 | 351 | |
3d9edf09 | 352 | /* we only care about one bank */ |
b5cf3fd8 | 353 | if ((bank_num % 2) == 1) |
3d9edf09 VB |
354 | mask <<= 16; |
355 | ||
356 | /* temporarily mask (level sensitive) parent IRQ */ | |
0d978eb7 | 357 | chained_irq_enter(irq_desc_get_chip(desc), desc); |
3d9edf09 VB |
358 | while (1) { |
359 | u32 status; | |
9211ff31 | 360 | int bit; |
b5cf3fd8 | 361 | irq_hw_number_t hw_irq; |
3d9edf09 VB |
362 | |
363 | /* ack any irqs */ | |
388291c3 | 364 | status = readl_relaxed(&g->intstat) & mask; |
3d9edf09 VB |
365 | if (!status) |
366 | break; | |
388291c3 | 367 | writel_relaxed(status, &g->intstat); |
3d9edf09 VB |
368 | |
369 | /* now demux them to the right lowlevel handler */ | |
f299bb95 | 370 | |
3d9edf09 | 371 | while (status) { |
9211ff31 LP |
372 | bit = __ffs(status); |
373 | status &= ~BIT(bit); | |
b5cf3fd8 K |
374 | /* Max number of gpios per controller is 144 so |
375 | * hw_irq will be in [0..143] | |
376 | */ | |
377 | hw_irq = (bank_num / 2) * 32 + bit; | |
378 | ||
9211ff31 | 379 | generic_handle_irq( |
b5cf3fd8 | 380 | irq_find_mapping(d->irq_domain, hw_irq)); |
3d9edf09 VB |
381 | } |
382 | } | |
0d978eb7 | 383 | chained_irq_exit(irq_desc_get_chip(desc), desc); |
3d9edf09 VB |
384 | /* now it may re-trigger */ |
385 | } | |
386 | ||
7a36071e DB |
387 | static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) |
388 | { | |
72a1ca2c | 389 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
7a36071e | 390 | |
6075a8b2 | 391 | if (d->irq_domain) |
b5cf3fd8 | 392 | return irq_create_mapping(d->irq_domain, offset); |
6075a8b2 GS |
393 | else |
394 | return -ENXIO; | |
7a36071e DB |
395 | } |
396 | ||
397 | static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) | |
398 | { | |
72a1ca2c | 399 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
7a36071e | 400 | |
131a10a3 PA |
401 | /* |
402 | * NOTE: we assume for now that only irqs in the first gpio_chip | |
7a36071e DB |
403 | * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). |
404 | */ | |
34af1ab4 | 405 | if (offset < d->gpio_unbanked) |
eb3744a2 | 406 | return d->irqs[offset]; |
7a36071e DB |
407 | else |
408 | return -ENODEV; | |
409 | } | |
410 | ||
ab2dde99 | 411 | static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) |
7a36071e | 412 | { |
ab2dde99 SN |
413 | struct davinci_gpio_controller *d; |
414 | struct davinci_gpio_regs __iomem *g; | |
eb3744a2 | 415 | u32 mask, i; |
ab2dde99 | 416 | |
c16edb8b | 417 | d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data); |
7f8e2a85 | 418 | g = (struct davinci_gpio_regs __iomem *)d->regs[0]; |
eb3744a2 K |
419 | for (i = 0; i < MAX_INT_PER_BANK; i++) |
420 | if (data->irq == d->irqs[i]) | |
421 | break; | |
422 | ||
423 | if (i == MAX_INT_PER_BANK) | |
424 | return -EINVAL; | |
425 | ||
426 | mask = __gpio_mask(i); | |
7a36071e DB |
427 | |
428 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
429 | return -EINVAL; | |
430 | ||
388291c3 | 431 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) |
7a36071e | 432 | ? &g->set_falling : &g->clr_falling); |
388291c3 | 433 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) |
7a36071e DB |
434 | ? &g->set_rising : &g->clr_rising); |
435 | ||
436 | return 0; | |
437 | } | |
438 | ||
9211ff31 LP |
439 | static int |
440 | davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, | |
441 | irq_hw_number_t hw) | |
442 | { | |
8f7cf8c6 K |
443 | struct davinci_gpio_controller *chips = |
444 | (struct davinci_gpio_controller *)d->host_data; | |
b5cf3fd8 | 445 | struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32]; |
9211ff31 LP |
446 | |
447 | irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, | |
448 | "davinci_gpio"); | |
449 | irq_set_irq_type(irq, IRQ_TYPE_NONE); | |
450 | irq_set_chip_data(irq, (__force void *)g); | |
36c05519 | 451 | irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw)); |
9211ff31 LP |
452 | |
453 | return 0; | |
454 | } | |
455 | ||
456 | static const struct irq_domain_ops davinci_gpio_irq_ops = { | |
457 | .map = davinci_gpio_irq_map, | |
458 | .xlate = irq_domain_xlate_onetwocell, | |
459 | }; | |
460 | ||
0c6feb07 GS |
461 | static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq) |
462 | { | |
463 | static struct irq_chip_type gpio_unbanked; | |
464 | ||
ccdbddfe | 465 | gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq)); |
0c6feb07 GS |
466 | |
467 | return &gpio_unbanked.chip; | |
468 | }; | |
469 | ||
470 | static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq) | |
471 | { | |
472 | static struct irq_chip gpio_unbanked; | |
473 | ||
474 | gpio_unbanked = *irq_get_chip(irq); | |
475 | return &gpio_unbanked; | |
476 | }; | |
477 | ||
478 | static const struct of_device_id davinci_gpio_ids[]; | |
479 | ||
3d9edf09 | 480 | /* |
474dad54 DB |
481 | * NOTE: for suspend/resume, probably best to make a platform_device with |
482 | * suspend_late/resume_resume calls hooking into results of the set_wake() | |
3d9edf09 VB |
483 | * calls ... so if no gpios are wakeup events the clock can be disabled, |
484 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 | |
474dad54 | 485 | * (dm6446) can be set appropriately for GPIOV33 pins. |
3d9edf09 VB |
486 | */ |
487 | ||
eb3744a2 | 488 | static int davinci_gpio_irq_setup(struct platform_device *pdev) |
3d9edf09 | 489 | { |
58c0f5aa AS |
490 | unsigned gpio, bank; |
491 | int irq; | |
6dc0048c | 492 | int ret; |
3d9edf09 | 493 | struct clk *clk; |
474dad54 | 494 | u32 binten = 0; |
c1d013a7 | 495 | unsigned ngpio; |
118150f2 | 496 | struct device *dev = &pdev->dev; |
118150f2 KS |
497 | struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); |
498 | struct davinci_gpio_platform_data *pdata = dev->platform_data; | |
499 | struct davinci_gpio_regs __iomem *g; | |
6075a8b2 | 500 | struct irq_domain *irq_domain = NULL; |
0c6feb07 GS |
501 | const struct of_device_id *match; |
502 | struct irq_chip *irq_chip; | |
b5cf3fd8 | 503 | struct davinci_gpio_irq_data *irqdata; |
0c6feb07 GS |
504 | gpio_get_irq_chip_cb_t gpio_get_irq_chip; |
505 | ||
506 | /* | |
507 | * Use davinci_gpio_get_irq_chip by default to handle non DT cases | |
508 | */ | |
509 | gpio_get_irq_chip = davinci_gpio_get_irq_chip; | |
510 | match = of_match_device(of_match_ptr(davinci_gpio_ids), | |
511 | dev); | |
512 | if (match) | |
513 | gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data; | |
a994955c | 514 | |
118150f2 | 515 | ngpio = pdata->ngpio; |
3d9edf09 | 516 | |
118150f2 | 517 | clk = devm_clk_get(dev, "gpio"); |
3d9edf09 | 518 | if (IS_ERR(clk)) { |
1a9ef909 | 519 | dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk)); |
474dad54 | 520 | return PTR_ERR(clk); |
3d9edf09 | 521 | } |
eb3744a2 | 522 | |
6dc0048c AY |
523 | ret = clk_prepare_enable(clk); |
524 | if (ret) | |
525 | return ret; | |
3d9edf09 | 526 | |
6075a8b2 | 527 | if (!pdata->gpio_unbanked) { |
a1a3c2d5 | 528 | irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0); |
6075a8b2 GS |
529 | if (irq < 0) { |
530 | dev_err(dev, "Couldn't allocate IRQ numbers\n"); | |
6dc0048c | 531 | clk_disable_unprepare(clk); |
6075a8b2 GS |
532 | return irq; |
533 | } | |
9211ff31 | 534 | |
310a7e60 | 535 | irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0, |
6075a8b2 GS |
536 | &davinci_gpio_irq_ops, |
537 | chips); | |
538 | if (!irq_domain) { | |
539 | dev_err(dev, "Couldn't register an IRQ domain\n"); | |
6dc0048c | 540 | clk_disable_unprepare(clk); |
6075a8b2 GS |
541 | return -ENODEV; |
542 | } | |
9211ff31 LP |
543 | } |
544 | ||
131a10a3 PA |
545 | /* |
546 | * Arrange gpio_to_irq() support, handling either direct IRQs or | |
7a36071e DB |
547 | * banked IRQs. Having GPIOs in the first GPIO bank use direct |
548 | * IRQs, while the others use banked IRQs, would need some setup | |
549 | * tweaks to recognize hardware which can do that. | |
550 | */ | |
b5cf3fd8 K |
551 | chips->chip.to_irq = gpio_to_irq_banked; |
552 | chips->irq_domain = irq_domain; | |
7a36071e DB |
553 | |
554 | /* | |
555 | * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO | |
556 | * controller only handling trigger modes. We currently assume no | |
557 | * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. | |
558 | */ | |
118150f2 | 559 | if (pdata->gpio_unbanked) { |
7a36071e | 560 | /* pass "bank 0" GPIO IRQs to AINTC */ |
b5cf3fd8 | 561 | chips->chip.to_irq = gpio_to_irq_unbanked; |
b5cf3fd8 | 562 | chips->gpio_unbanked = pdata->gpio_unbanked; |
3685bbce | 563 | binten = GENMASK(pdata->gpio_unbanked / 16, 0); |
7a36071e DB |
564 | |
565 | /* AINTC handles mask/unmask; GPIO handles triggering */ | |
eb3744a2 | 566 | irq = chips->irqs[0]; |
0c6feb07 GS |
567 | irq_chip = gpio_get_irq_chip(irq); |
568 | irq_chip->name = "GPIO-AINTC"; | |
569 | irq_chip->irq_set_type = gpio_irq_type_unbanked; | |
7a36071e DB |
570 | |
571 | /* default trigger: both edges */ | |
b5cf3fd8 | 572 | g = chips->regs[0]; |
388291c3 LP |
573 | writel_relaxed(~0, &g->set_falling); |
574 | writel_relaxed(~0, &g->set_rising); | |
7a36071e DB |
575 | |
576 | /* set the direct IRQs up to use that irqchip */ | |
eb3744a2 K |
577 | for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) { |
578 | irq_set_chip(chips->irqs[gpio], irq_chip); | |
579 | irq_set_handler_data(chips->irqs[gpio], chips); | |
580 | irq_set_status_flags(chips->irqs[gpio], | |
581 | IRQ_TYPE_EDGE_BOTH); | |
7a36071e DB |
582 | } |
583 | ||
584 | goto done; | |
585 | } | |
586 | ||
587 | /* | |
588 | * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we | |
589 | * then chain through our own handler. | |
590 | */ | |
eb3744a2 | 591 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) { |
8f7cf8c6 K |
592 | /* disabled by default, enabled only as needed |
593 | * There are register sets for 32 GPIOs. 2 banks of 16 | |
594 | * GPIOs are covered by each set of registers hence divide by 2 | |
595 | */ | |
b5cf3fd8 | 596 | g = chips->regs[bank / 2]; |
388291c3 LP |
597 | writel_relaxed(~0, &g->clr_falling); |
598 | writel_relaxed(~0, &g->clr_rising); | |
3d9edf09 | 599 | |
f299bb95 IY |
600 | /* |
601 | * Each chip handles 32 gpios, and each irq bank consists of 16 | |
602 | * gpio irqs. Pass the irq bank's corresponding controller to | |
603 | * the chained irq handler. | |
604 | */ | |
b5cf3fd8 K |
605 | irqdata = devm_kzalloc(&pdev->dev, |
606 | sizeof(struct | |
607 | davinci_gpio_irq_data), | |
608 | GFP_KERNEL); | |
6dc0048c AY |
609 | if (!irqdata) { |
610 | clk_disable_unprepare(clk); | |
b5cf3fd8 | 611 | return -ENOMEM; |
6dc0048c | 612 | } |
b5cf3fd8 K |
613 | |
614 | irqdata->regs = g; | |
615 | irqdata->bank_num = bank; | |
616 | irqdata->chip = chips; | |
617 | ||
eb3744a2 K |
618 | irq_set_chained_handler_and_data(chips->irqs[bank], |
619 | gpio_irq_handler, irqdata); | |
3d9edf09 | 620 | |
474dad54 | 621 | binten |= BIT(bank); |
3d9edf09 VB |
622 | } |
623 | ||
7a36071e | 624 | done: |
131a10a3 PA |
625 | /* |
626 | * BINTEN -- per-bank interrupt enable. genirq would also let these | |
3d9edf09 VB |
627 | * bits be set/cleared dynamically. |
628 | */ | |
388291c3 | 629 | writel_relaxed(binten, gpio_base + BINTEN); |
3d9edf09 | 630 | |
3d9edf09 VB |
631 | return 0; |
632 | } | |
118150f2 | 633 | |
c770844c | 634 | static const struct of_device_id davinci_gpio_ids[] = { |
0c6feb07 | 635 | { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip}, |
6a4d8b6b | 636 | { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip}, |
0c6feb07 | 637 | { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip}, |
c770844c KS |
638 | { /* sentinel */ }, |
639 | }; | |
640 | MODULE_DEVICE_TABLE(of, davinci_gpio_ids); | |
c770844c | 641 | |
118150f2 KS |
642 | static struct platform_driver davinci_gpio_driver = { |
643 | .probe = davinci_gpio_probe, | |
644 | .driver = { | |
c770844c | 645 | .name = "davinci_gpio", |
c770844c | 646 | .of_match_table = of_match_ptr(davinci_gpio_ids), |
118150f2 KS |
647 | }, |
648 | }; | |
649 | ||
650 | /** | |
651 | * GPIO driver registration needs to be done before machine_init functions | |
652 | * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall. | |
653 | */ | |
654 | static int __init davinci_gpio_drv_reg(void) | |
655 | { | |
656 | return platform_driver_register(&davinci_gpio_driver); | |
657 | } | |
658 | postcore_initcall(davinci_gpio_drv_reg); |