Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
3d9edf09 VB |
2 | /* |
3 | * TI DaVinci GPIO Support | |
4 | * | |
dce1115b | 5 | * Copyright (c) 2006-2007 David Brownell |
3d9edf09 | 6 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> |
3d9edf09 | 7 | */ |
79b73ff9 | 8 | |
7220c43a | 9 | #include <linux/gpio/driver.h> |
3d9edf09 VB |
10 | #include <linux/errno.h> |
11 | #include <linux/kernel.h> | |
3d9edf09 VB |
12 | #include <linux/clk.h> |
13 | #include <linux/err.h> | |
14 | #include <linux/io.h> | |
118150f2 | 15 | #include <linux/irq.h> |
9211ff31 | 16 | #include <linux/irqdomain.h> |
c770844c KS |
17 | #include <linux/module.h> |
18 | #include <linux/of.h> | |
19 | #include <linux/of_device.h> | |
3c87d7c8 | 20 | #include <linux/pinctrl/consumer.h> |
118150f2 KS |
21 | #include <linux/platform_device.h> |
22 | #include <linux/platform_data/gpio-davinci.h> | |
0d978eb7 | 23 | #include <linux/irqchip/chained_irq.h> |
79b73ff9 | 24 | #include <linux/spinlock.h> |
0651a730 | 25 | #include <linux/pm_runtime.h> |
79b73ff9 | 26 | |
79b73ff9 AD |
27 | #define MAX_REGS_BANKS 5 |
28 | #define MAX_INT_PER_BANK 32 | |
3d9edf09 | 29 | |
c12f415a CC |
30 | struct davinci_gpio_regs { |
31 | u32 dir; | |
32 | u32 out_data; | |
33 | u32 set_data; | |
34 | u32 clr_data; | |
35 | u32 in_data; | |
36 | u32 set_rising; | |
37 | u32 clr_rising; | |
38 | u32 set_falling; | |
39 | u32 clr_falling; | |
40 | u32 intstat; | |
41 | }; | |
42 | ||
0c6feb07 GS |
43 | typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq); |
44 | ||
131a10a3 PA |
45 | #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ |
46 | ||
b8d44293 | 47 | static void __iomem *gpio_base; |
8f7cf8c6 | 48 | static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0}; |
3d9edf09 | 49 | |
79b73ff9 AD |
50 | struct davinci_gpio_irq_data { |
51 | void __iomem *regs; | |
52 | struct davinci_gpio_controller *chip; | |
53 | int bank_num; | |
54 | }; | |
55 | ||
56 | struct davinci_gpio_controller { | |
57 | struct gpio_chip chip; | |
58 | struct irq_domain *irq_domain; | |
59 | /* Serialize access to GPIO registers */ | |
60 | spinlock_t lock; | |
61 | void __iomem *regs[MAX_REGS_BANKS]; | |
62 | int gpio_unbanked; | |
63 | int irqs[MAX_INT_PER_BANK]; | |
0651a730 DT |
64 | struct davinci_gpio_regs context[MAX_REGS_BANKS]; |
65 | u32 binten_context; | |
79b73ff9 AD |
66 | }; |
67 | ||
68 | static inline u32 __gpio_mask(unsigned gpio) | |
69 | { | |
70 | return 1 << (gpio % 32); | |
71 | } | |
72 | ||
1765d671 | 73 | static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d) |
21ce873d | 74 | { |
99e9e52d | 75 | struct davinci_gpio_regs __iomem *g; |
21ce873d | 76 | |
1765d671 | 77 | g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d); |
21ce873d KH |
78 | |
79 | return g; | |
80 | } | |
81 | ||
eb3744a2 | 82 | static int davinci_gpio_irq_setup(struct platform_device *pdev); |
dce1115b DB |
83 | |
84 | /*--------------------------------------------------------------------------*/ | |
85 | ||
5b3a05ca | 86 | /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ |
ba4a984e CC |
87 | static inline int __davinci_direction(struct gpio_chip *chip, |
88 | unsigned offset, bool out, int value) | |
3d9edf09 | 89 | { |
72a1ca2c | 90 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
b5cf3fd8 | 91 | struct davinci_gpio_regs __iomem *g; |
b27b6d03 | 92 | unsigned long flags; |
dce1115b | 93 | u32 temp; |
b5cf3fd8 K |
94 | int bank = offset / 32; |
95 | u32 mask = __gpio_mask(offset); | |
3d9edf09 | 96 | |
b5cf3fd8 | 97 | g = d->regs[bank]; |
b27b6d03 | 98 | spin_lock_irqsave(&d->lock, flags); |
388291c3 | 99 | temp = readl_relaxed(&g->dir); |
ba4a984e CC |
100 | if (out) { |
101 | temp &= ~mask; | |
388291c3 | 102 | writel_relaxed(mask, value ? &g->set_data : &g->clr_data); |
ba4a984e CC |
103 | } else { |
104 | temp |= mask; | |
105 | } | |
388291c3 | 106 | writel_relaxed(temp, &g->dir); |
b27b6d03 | 107 | spin_unlock_irqrestore(&d->lock, flags); |
3d9edf09 | 108 | |
dce1115b DB |
109 | return 0; |
110 | } | |
3d9edf09 | 111 | |
ba4a984e CC |
112 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) |
113 | { | |
114 | return __davinci_direction(chip, offset, false, 0); | |
115 | } | |
116 | ||
117 | static int | |
118 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) | |
119 | { | |
120 | return __davinci_direction(chip, offset, true, value); | |
121 | } | |
122 | ||
3d9edf09 VB |
123 | /* |
124 | * Read the pin's value (works even if it's set up as output); | |
125 | * returns zero/nonzero. | |
126 | * | |
127 | * Note that changes are synched to the GPIO clock, so reading values back | |
128 | * right after you've set them may give old values. | |
129 | */ | |
dce1115b | 130 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
3d9edf09 | 131 | { |
72a1ca2c | 132 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
b5cf3fd8 K |
133 | struct davinci_gpio_regs __iomem *g; |
134 | int bank = offset / 32; | |
3d9edf09 | 135 | |
b5cf3fd8 K |
136 | g = d->regs[bank]; |
137 | ||
138 | return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data)); | |
3d9edf09 | 139 | } |
3d9edf09 | 140 | |
dce1115b DB |
141 | /* |
142 | * Assuming the pin is muxed as a gpio output, set its output value. | |
143 | */ | |
144 | static void | |
145 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
3d9edf09 | 146 | { |
72a1ca2c | 147 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
b5cf3fd8 K |
148 | struct davinci_gpio_regs __iomem *g; |
149 | int bank = offset / 32; | |
3d9edf09 | 150 | |
b5cf3fd8 K |
151 | g = d->regs[bank]; |
152 | ||
153 | writel_relaxed(__gpio_mask(offset), | |
154 | value ? &g->set_data : &g->clr_data); | |
dce1115b DB |
155 | } |
156 | ||
c770844c KS |
157 | static struct davinci_gpio_platform_data * |
158 | davinci_gpio_get_pdata(struct platform_device *pdev) | |
159 | { | |
160 | struct device_node *dn = pdev->dev.of_node; | |
161 | struct davinci_gpio_platform_data *pdata; | |
162 | int ret; | |
163 | u32 val; | |
164 | ||
165 | if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) | |
ab128afc | 166 | return dev_get_platdata(&pdev->dev); |
c770844c KS |
167 | |
168 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
169 | if (!pdata) | |
170 | return NULL; | |
171 | ||
172 | ret = of_property_read_u32(dn, "ti,ngpio", &val); | |
173 | if (ret) | |
174 | goto of_err; | |
175 | ||
176 | pdata->ngpio = val; | |
177 | ||
178 | ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val); | |
179 | if (ret) | |
180 | goto of_err; | |
181 | ||
182 | pdata->gpio_unbanked = val; | |
183 | ||
184 | return pdata; | |
185 | ||
186 | of_err: | |
187 | dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret); | |
188 | return NULL; | |
189 | } | |
190 | ||
118150f2 | 191 | static int davinci_gpio_probe(struct platform_device *pdev) |
dce1115b | 192 | { |
c809e37a | 193 | int bank, i, ret = 0; |
eb3744a2 | 194 | unsigned int ngpio, nbank, nirq; |
118150f2 KS |
195 | struct davinci_gpio_controller *chips; |
196 | struct davinci_gpio_platform_data *pdata; | |
118150f2 | 197 | struct device *dev = &pdev->dev; |
118150f2 | 198 | |
c770844c | 199 | pdata = davinci_gpio_get_pdata(pdev); |
118150f2 KS |
200 | if (!pdata) { |
201 | dev_err(dev, "No platform data found\n"); | |
202 | return -EINVAL; | |
203 | } | |
686b634a | 204 | |
c770844c KS |
205 | dev->platform_data = pdata; |
206 | ||
a994955c MG |
207 | /* |
208 | * The gpio banks conceptually expose a segmented bitmap, | |
474dad54 DB |
209 | * and "ngpio" is one more than the largest zero-based |
210 | * bit index that's valid. | |
211 | */ | |
118150f2 | 212 | ngpio = pdata->ngpio; |
a994955c | 213 | if (ngpio == 0) { |
118150f2 | 214 | dev_err(dev, "How many GPIOs?\n"); |
474dad54 DB |
215 | return -EINVAL; |
216 | } | |
217 | ||
eb3744a2 K |
218 | /* |
219 | * If there are unbanked interrupts then the number of | |
220 | * interrupts is equal to number of gpios else all are banked so | |
221 | * number of interrupts is equal to number of banks(each with 16 gpios) | |
222 | */ | |
223 | if (pdata->gpio_unbanked) | |
224 | nirq = pdata->gpio_unbanked; | |
225 | else | |
226 | nirq = DIV_ROUND_UP(ngpio, 16); | |
227 | ||
c809e37a | 228 | chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL); |
9ea9363c | 229 | if (!chips) |
b8d44293 | 230 | return -ENOMEM; |
118150f2 | 231 | |
fa7569c8 | 232 | gpio_base = devm_platform_ioremap_resource(pdev, 0); |
118150f2 KS |
233 | if (IS_ERR(gpio_base)) |
234 | return PTR_ERR(gpio_base); | |
b8d44293 | 235 | |
eb3744a2 K |
236 | for (i = 0; i < nirq; i++) { |
237 | chips->irqs[i] = platform_get_irq(pdev, i); | |
33b78b5f | 238 | if (chips->irqs[i] < 0) |
73561d28 | 239 | return chips->irqs[i]; |
c1d013a7 K |
240 | } |
241 | ||
587f7a69 | 242 | chips->chip.label = dev_name(dev); |
dce1115b | 243 | |
b5cf3fd8 K |
244 | chips->chip.direction_input = davinci_direction_in; |
245 | chips->chip.get = davinci_gpio_get; | |
246 | chips->chip.direction_output = davinci_direction_out; | |
247 | chips->chip.set = davinci_gpio_set; | |
dce1115b | 248 | |
b5cf3fd8 | 249 | chips->chip.ngpio = ngpio; |
786a9ab1 | 250 | chips->chip.base = pdata->no_auto_base ? pdata->base : -1; |
dce1115b | 251 | |
c770844c | 252 | #ifdef CONFIG_OF_GPIO |
b5cf3fd8 | 253 | chips->chip.parent = dev; |
f0254b51 TR |
254 | chips->chip.request = gpiochip_generic_request; |
255 | chips->chip.free = gpiochip_generic_free; | |
c770844c | 256 | #endif |
b5cf3fd8 | 257 | spin_lock_init(&chips->lock); |
dce1115b | 258 | |
c809e37a AD |
259 | nbank = DIV_ROUND_UP(ngpio, 32); |
260 | for (bank = 0; bank < nbank; bank++) | |
b5cf3fd8 | 261 | chips->regs[bank] = gpio_base + offset_array[bank]; |
3d9edf09 | 262 | |
8327e1ba K |
263 | ret = devm_gpiochip_add_data(dev, &chips->chip, chips); |
264 | if (ret) | |
587f7a69 | 265 | return ret; |
8327e1ba | 266 | |
118150f2 | 267 | platform_set_drvdata(pdev, chips); |
eb3744a2 | 268 | ret = davinci_gpio_irq_setup(pdev); |
5e7a0ce7 | 269 | if (ret) |
587f7a69 | 270 | return ret; |
5e7a0ce7 | 271 | |
3d9edf09 VB |
272 | return 0; |
273 | } | |
3d9edf09 | 274 | |
dce1115b | 275 | /*--------------------------------------------------------------------------*/ |
3d9edf09 VB |
276 | /* |
277 | * We expect irqs will normally be set up as input pins, but they can also be | |
278 | * used as output pins ... which is convenient for testing. | |
279 | * | |
474dad54 | 280 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
7a36071e | 281 | * to their GPIOBNK0 irq, with a bit less overhead. |
3d9edf09 | 282 | * |
474dad54 | 283 | * All those INTC hookups (direct, plus several IRQ banks) can also |
3d9edf09 VB |
284 | * serve as EDMA event triggers. |
285 | */ | |
286 | ||
23265442 | 287 | static void gpio_irq_disable(struct irq_data *d) |
3d9edf09 | 288 | { |
1765d671 | 289 | struct davinci_gpio_regs __iomem *g = irq2regs(d); |
36c05519 | 290 | uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d); |
3d9edf09 | 291 | |
388291c3 LP |
292 | writel_relaxed(mask, &g->clr_falling); |
293 | writel_relaxed(mask, &g->clr_rising); | |
3d9edf09 VB |
294 | } |
295 | ||
23265442 | 296 | static void gpio_irq_enable(struct irq_data *d) |
3d9edf09 | 297 | { |
1765d671 | 298 | struct davinci_gpio_regs __iomem *g = irq2regs(d); |
36c05519 | 299 | uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d); |
5093aec8 | 300 | unsigned status = irqd_get_trigger_type(d); |
3d9edf09 | 301 | |
df4aab46 DB |
302 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
303 | if (!status) | |
304 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | |
305 | ||
306 | if (status & IRQ_TYPE_EDGE_FALLING) | |
388291c3 | 307 | writel_relaxed(mask, &g->set_falling); |
df4aab46 | 308 | if (status & IRQ_TYPE_EDGE_RISING) |
388291c3 | 309 | writel_relaxed(mask, &g->set_rising); |
3d9edf09 VB |
310 | } |
311 | ||
23265442 | 312 | static int gpio_irq_type(struct irq_data *d, unsigned trigger) |
3d9edf09 | 313 | { |
3d9edf09 VB |
314 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
315 | return -EINVAL; | |
316 | ||
3d9edf09 VB |
317 | return 0; |
318 | } | |
319 | ||
320 | static struct irq_chip gpio_irqchip = { | |
321 | .name = "GPIO", | |
23265442 LB |
322 | .irq_enable = gpio_irq_enable, |
323 | .irq_disable = gpio_irq_disable, | |
324 | .irq_set_type = gpio_irq_type, | |
7b75c470 | 325 | .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_SKIP_SET_WAKE, |
3d9edf09 VB |
326 | }; |
327 | ||
bd0b9ac4 | 328 | static void gpio_irq_handler(struct irq_desc *desc) |
3d9edf09 | 329 | { |
74164016 | 330 | struct davinci_gpio_regs __iomem *g; |
3d9edf09 | 331 | u32 mask = 0xffff; |
b5cf3fd8 | 332 | int bank_num; |
f299bb95 | 333 | struct davinci_gpio_controller *d; |
b5cf3fd8 | 334 | struct davinci_gpio_irq_data *irqdata; |
3d9edf09 | 335 | |
b5cf3fd8 K |
336 | irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc); |
337 | bank_num = irqdata->bank_num; | |
338 | g = irqdata->regs; | |
339 | d = irqdata->chip; | |
74164016 | 340 | |
3d9edf09 | 341 | /* we only care about one bank */ |
b5cf3fd8 | 342 | if ((bank_num % 2) == 1) |
3d9edf09 VB |
343 | mask <<= 16; |
344 | ||
345 | /* temporarily mask (level sensitive) parent IRQ */ | |
0d978eb7 | 346 | chained_irq_enter(irq_desc_get_chip(desc), desc); |
3d9edf09 VB |
347 | while (1) { |
348 | u32 status; | |
9211ff31 | 349 | int bit; |
b5cf3fd8 | 350 | irq_hw_number_t hw_irq; |
3d9edf09 VB |
351 | |
352 | /* ack any irqs */ | |
388291c3 | 353 | status = readl_relaxed(&g->intstat) & mask; |
3d9edf09 VB |
354 | if (!status) |
355 | break; | |
388291c3 | 356 | writel_relaxed(status, &g->intstat); |
3d9edf09 VB |
357 | |
358 | /* now demux them to the right lowlevel handler */ | |
f299bb95 | 359 | |
3d9edf09 | 360 | while (status) { |
9211ff31 LP |
361 | bit = __ffs(status); |
362 | status &= ~BIT(bit); | |
b5cf3fd8 K |
363 | /* Max number of gpios per controller is 144 so |
364 | * hw_irq will be in [0..143] | |
365 | */ | |
366 | hw_irq = (bank_num / 2) * 32 + bit; | |
367 | ||
dbd1c54f | 368 | generic_handle_domain_irq(d->irq_domain, hw_irq); |
3d9edf09 VB |
369 | } |
370 | } | |
0d978eb7 | 371 | chained_irq_exit(irq_desc_get_chip(desc), desc); |
3d9edf09 VB |
372 | /* now it may re-trigger */ |
373 | } | |
374 | ||
7a36071e DB |
375 | static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) |
376 | { | |
72a1ca2c | 377 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
7a36071e | 378 | |
6075a8b2 | 379 | if (d->irq_domain) |
b5cf3fd8 | 380 | return irq_create_mapping(d->irq_domain, offset); |
6075a8b2 GS |
381 | else |
382 | return -ENXIO; | |
7a36071e DB |
383 | } |
384 | ||
385 | static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) | |
386 | { | |
72a1ca2c | 387 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
7a36071e | 388 | |
131a10a3 PA |
389 | /* |
390 | * NOTE: we assume for now that only irqs in the first gpio_chip | |
7a36071e DB |
391 | * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). |
392 | */ | |
34af1ab4 | 393 | if (offset < d->gpio_unbanked) |
eb3744a2 | 394 | return d->irqs[offset]; |
7a36071e DB |
395 | else |
396 | return -ENODEV; | |
397 | } | |
398 | ||
ab2dde99 | 399 | static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) |
7a36071e | 400 | { |
ab2dde99 SN |
401 | struct davinci_gpio_controller *d; |
402 | struct davinci_gpio_regs __iomem *g; | |
eb3744a2 | 403 | u32 mask, i; |
ab2dde99 | 404 | |
c16edb8b | 405 | d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data); |
7f8e2a85 | 406 | g = (struct davinci_gpio_regs __iomem *)d->regs[0]; |
eb3744a2 K |
407 | for (i = 0; i < MAX_INT_PER_BANK; i++) |
408 | if (data->irq == d->irqs[i]) | |
409 | break; | |
410 | ||
411 | if (i == MAX_INT_PER_BANK) | |
412 | return -EINVAL; | |
413 | ||
414 | mask = __gpio_mask(i); | |
7a36071e DB |
415 | |
416 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
417 | return -EINVAL; | |
418 | ||
388291c3 | 419 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) |
7a36071e | 420 | ? &g->set_falling : &g->clr_falling); |
388291c3 | 421 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) |
7a36071e DB |
422 | ? &g->set_rising : &g->clr_rising); |
423 | ||
424 | return 0; | |
425 | } | |
426 | ||
9211ff31 LP |
427 | static int |
428 | davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, | |
429 | irq_hw_number_t hw) | |
430 | { | |
8f7cf8c6 K |
431 | struct davinci_gpio_controller *chips = |
432 | (struct davinci_gpio_controller *)d->host_data; | |
b5cf3fd8 | 433 | struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32]; |
9211ff31 LP |
434 | |
435 | irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, | |
436 | "davinci_gpio"); | |
437 | irq_set_irq_type(irq, IRQ_TYPE_NONE); | |
438 | irq_set_chip_data(irq, (__force void *)g); | |
36c05519 | 439 | irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw)); |
9211ff31 LP |
440 | |
441 | return 0; | |
442 | } | |
443 | ||
444 | static const struct irq_domain_ops davinci_gpio_irq_ops = { | |
445 | .map = davinci_gpio_irq_map, | |
446 | .xlate = irq_domain_xlate_onetwocell, | |
447 | }; | |
448 | ||
0c6feb07 GS |
449 | static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq) |
450 | { | |
451 | static struct irq_chip_type gpio_unbanked; | |
452 | ||
ccdbddfe | 453 | gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq)); |
0c6feb07 GS |
454 | |
455 | return &gpio_unbanked.chip; | |
456 | }; | |
457 | ||
458 | static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq) | |
459 | { | |
460 | static struct irq_chip gpio_unbanked; | |
461 | ||
462 | gpio_unbanked = *irq_get_chip(irq); | |
463 | return &gpio_unbanked; | |
464 | }; | |
465 | ||
466 | static const struct of_device_id davinci_gpio_ids[]; | |
467 | ||
3d9edf09 | 468 | /* |
474dad54 DB |
469 | * NOTE: for suspend/resume, probably best to make a platform_device with |
470 | * suspend_late/resume_resume calls hooking into results of the set_wake() | |
3d9edf09 VB |
471 | * calls ... so if no gpios are wakeup events the clock can be disabled, |
472 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 | |
474dad54 | 473 | * (dm6446) can be set appropriately for GPIOV33 pins. |
3d9edf09 VB |
474 | */ |
475 | ||
eb3744a2 | 476 | static int davinci_gpio_irq_setup(struct platform_device *pdev) |
3d9edf09 | 477 | { |
58c0f5aa AS |
478 | unsigned gpio, bank; |
479 | int irq; | |
6dc0048c | 480 | int ret; |
3d9edf09 | 481 | struct clk *clk; |
474dad54 | 482 | u32 binten = 0; |
c1d013a7 | 483 | unsigned ngpio; |
118150f2 | 484 | struct device *dev = &pdev->dev; |
118150f2 KS |
485 | struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); |
486 | struct davinci_gpio_platform_data *pdata = dev->platform_data; | |
487 | struct davinci_gpio_regs __iomem *g; | |
6075a8b2 | 488 | struct irq_domain *irq_domain = NULL; |
0c6feb07 GS |
489 | const struct of_device_id *match; |
490 | struct irq_chip *irq_chip; | |
b5cf3fd8 | 491 | struct davinci_gpio_irq_data *irqdata; |
0c6feb07 GS |
492 | gpio_get_irq_chip_cb_t gpio_get_irq_chip; |
493 | ||
494 | /* | |
495 | * Use davinci_gpio_get_irq_chip by default to handle non DT cases | |
496 | */ | |
497 | gpio_get_irq_chip = davinci_gpio_get_irq_chip; | |
498 | match = of_match_device(of_match_ptr(davinci_gpio_ids), | |
499 | dev); | |
500 | if (match) | |
501 | gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data; | |
a994955c | 502 | |
118150f2 | 503 | ngpio = pdata->ngpio; |
3d9edf09 | 504 | |
118150f2 | 505 | clk = devm_clk_get(dev, "gpio"); |
3d9edf09 | 506 | if (IS_ERR(clk)) { |
1a9ef909 | 507 | dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk)); |
474dad54 | 508 | return PTR_ERR(clk); |
3d9edf09 | 509 | } |
eb3744a2 | 510 | |
6dc0048c AY |
511 | ret = clk_prepare_enable(clk); |
512 | if (ret) | |
513 | return ret; | |
3d9edf09 | 514 | |
6075a8b2 | 515 | if (!pdata->gpio_unbanked) { |
a1a3c2d5 | 516 | irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0); |
6075a8b2 GS |
517 | if (irq < 0) { |
518 | dev_err(dev, "Couldn't allocate IRQ numbers\n"); | |
6dc0048c | 519 | clk_disable_unprepare(clk); |
6075a8b2 GS |
520 | return irq; |
521 | } | |
9211ff31 | 522 | |
310a7e60 | 523 | irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0, |
6075a8b2 GS |
524 | &davinci_gpio_irq_ops, |
525 | chips); | |
526 | if (!irq_domain) { | |
527 | dev_err(dev, "Couldn't register an IRQ domain\n"); | |
6dc0048c | 528 | clk_disable_unprepare(clk); |
6075a8b2 GS |
529 | return -ENODEV; |
530 | } | |
9211ff31 LP |
531 | } |
532 | ||
131a10a3 | 533 | /* |
029d14e9 | 534 | * Arrange gpiod_to_irq() support, handling either direct IRQs or |
7a36071e DB |
535 | * banked IRQs. Having GPIOs in the first GPIO bank use direct |
536 | * IRQs, while the others use banked IRQs, would need some setup | |
537 | * tweaks to recognize hardware which can do that. | |
538 | */ | |
b5cf3fd8 K |
539 | chips->chip.to_irq = gpio_to_irq_banked; |
540 | chips->irq_domain = irq_domain; | |
7a36071e DB |
541 | |
542 | /* | |
543 | * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO | |
544 | * controller only handling trigger modes. We currently assume no | |
545 | * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. | |
546 | */ | |
118150f2 | 547 | if (pdata->gpio_unbanked) { |
7a36071e | 548 | /* pass "bank 0" GPIO IRQs to AINTC */ |
b5cf3fd8 | 549 | chips->chip.to_irq = gpio_to_irq_unbanked; |
b5cf3fd8 | 550 | chips->gpio_unbanked = pdata->gpio_unbanked; |
3685bbce | 551 | binten = GENMASK(pdata->gpio_unbanked / 16, 0); |
7a36071e DB |
552 | |
553 | /* AINTC handles mask/unmask; GPIO handles triggering */ | |
eb3744a2 | 554 | irq = chips->irqs[0]; |
0c6feb07 GS |
555 | irq_chip = gpio_get_irq_chip(irq); |
556 | irq_chip->name = "GPIO-AINTC"; | |
557 | irq_chip->irq_set_type = gpio_irq_type_unbanked; | |
7a36071e DB |
558 | |
559 | /* default trigger: both edges */ | |
b5cf3fd8 | 560 | g = chips->regs[0]; |
388291c3 LP |
561 | writel_relaxed(~0, &g->set_falling); |
562 | writel_relaxed(~0, &g->set_rising); | |
7a36071e DB |
563 | |
564 | /* set the direct IRQs up to use that irqchip */ | |
eb3744a2 K |
565 | for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) { |
566 | irq_set_chip(chips->irqs[gpio], irq_chip); | |
567 | irq_set_handler_data(chips->irqs[gpio], chips); | |
568 | irq_set_status_flags(chips->irqs[gpio], | |
569 | IRQ_TYPE_EDGE_BOTH); | |
7a36071e DB |
570 | } |
571 | ||
572 | goto done; | |
573 | } | |
574 | ||
575 | /* | |
576 | * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we | |
577 | * then chain through our own handler. | |
578 | */ | |
eb3744a2 | 579 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) { |
8f7cf8c6 K |
580 | /* disabled by default, enabled only as needed |
581 | * There are register sets for 32 GPIOs. 2 banks of 16 | |
582 | * GPIOs are covered by each set of registers hence divide by 2 | |
583 | */ | |
b5cf3fd8 | 584 | g = chips->regs[bank / 2]; |
388291c3 LP |
585 | writel_relaxed(~0, &g->clr_falling); |
586 | writel_relaxed(~0, &g->clr_rising); | |
3d9edf09 | 587 | |
f299bb95 IY |
588 | /* |
589 | * Each chip handles 32 gpios, and each irq bank consists of 16 | |
590 | * gpio irqs. Pass the irq bank's corresponding controller to | |
591 | * the chained irq handler. | |
592 | */ | |
b5cf3fd8 K |
593 | irqdata = devm_kzalloc(&pdev->dev, |
594 | sizeof(struct | |
595 | davinci_gpio_irq_data), | |
596 | GFP_KERNEL); | |
6dc0048c AY |
597 | if (!irqdata) { |
598 | clk_disable_unprepare(clk); | |
b5cf3fd8 | 599 | return -ENOMEM; |
6dc0048c | 600 | } |
b5cf3fd8 K |
601 | |
602 | irqdata->regs = g; | |
603 | irqdata->bank_num = bank; | |
604 | irqdata->chip = chips; | |
605 | ||
eb3744a2 K |
606 | irq_set_chained_handler_and_data(chips->irqs[bank], |
607 | gpio_irq_handler, irqdata); | |
3d9edf09 | 608 | |
474dad54 | 609 | binten |= BIT(bank); |
3d9edf09 VB |
610 | } |
611 | ||
7a36071e | 612 | done: |
131a10a3 PA |
613 | /* |
614 | * BINTEN -- per-bank interrupt enable. genirq would also let these | |
3d9edf09 VB |
615 | * bits be set/cleared dynamically. |
616 | */ | |
388291c3 | 617 | writel_relaxed(binten, gpio_base + BINTEN); |
3d9edf09 | 618 | |
3d9edf09 VB |
619 | return 0; |
620 | } | |
118150f2 | 621 | |
0651a730 DT |
622 | static void davinci_gpio_save_context(struct davinci_gpio_controller *chips, |
623 | u32 nbank) | |
624 | { | |
625 | struct davinci_gpio_regs __iomem *g; | |
626 | struct davinci_gpio_regs *context; | |
627 | u32 bank; | |
628 | void __iomem *base; | |
629 | ||
630 | base = chips->regs[0] - offset_array[0]; | |
631 | chips->binten_context = readl_relaxed(base + BINTEN); | |
632 | ||
633 | for (bank = 0; bank < nbank; bank++) { | |
634 | g = chips->regs[bank]; | |
635 | context = &chips->context[bank]; | |
636 | context->dir = readl_relaxed(&g->dir); | |
637 | context->set_data = readl_relaxed(&g->set_data); | |
638 | context->set_rising = readl_relaxed(&g->set_rising); | |
639 | context->set_falling = readl_relaxed(&g->set_falling); | |
640 | } | |
641 | ||
0651a730 DT |
642 | /* Clear all interrupt status registers */ |
643 | writel_relaxed(GENMASK(31, 0), &g->intstat); | |
644 | } | |
645 | ||
646 | static void davinci_gpio_restore_context(struct davinci_gpio_controller *chips, | |
647 | u32 nbank) | |
648 | { | |
649 | struct davinci_gpio_regs __iomem *g; | |
650 | struct davinci_gpio_regs *context; | |
651 | u32 bank; | |
652 | void __iomem *base; | |
653 | ||
654 | base = chips->regs[0] - offset_array[0]; | |
655 | ||
656 | if (readl_relaxed(base + BINTEN) != chips->binten_context) | |
657 | writel_relaxed(chips->binten_context, base + BINTEN); | |
658 | ||
659 | for (bank = 0; bank < nbank; bank++) { | |
660 | g = chips->regs[bank]; | |
661 | context = &chips->context[bank]; | |
662 | if (readl_relaxed(&g->dir) != context->dir) | |
663 | writel_relaxed(context->dir, &g->dir); | |
664 | if (readl_relaxed(&g->set_data) != context->set_data) | |
665 | writel_relaxed(context->set_data, &g->set_data); | |
666 | if (readl_relaxed(&g->set_rising) != context->set_rising) | |
667 | writel_relaxed(context->set_rising, &g->set_rising); | |
668 | if (readl_relaxed(&g->set_falling) != context->set_falling) | |
669 | writel_relaxed(context->set_falling, &g->set_falling); | |
670 | } | |
671 | } | |
672 | ||
673 | static int davinci_gpio_suspend(struct device *dev) | |
674 | { | |
675 | struct davinci_gpio_controller *chips = dev_get_drvdata(dev); | |
676 | struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev); | |
677 | u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32); | |
678 | ||
679 | davinci_gpio_save_context(chips, nbank); | |
680 | ||
681 | return 0; | |
682 | } | |
683 | ||
684 | static int davinci_gpio_resume(struct device *dev) | |
685 | { | |
686 | struct davinci_gpio_controller *chips = dev_get_drvdata(dev); | |
687 | struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev); | |
688 | u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32); | |
689 | ||
690 | davinci_gpio_restore_context(chips, nbank); | |
691 | ||
692 | return 0; | |
693 | } | |
694 | ||
8507f354 | 695 | static DEFINE_SIMPLE_DEV_PM_OPS(davinci_gpio_dev_pm_ops, davinci_gpio_suspend, |
0651a730 DT |
696 | davinci_gpio_resume); |
697 | ||
c770844c | 698 | static const struct of_device_id davinci_gpio_ids[] = { |
0c6feb07 | 699 | { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip}, |
6a4d8b6b | 700 | { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip}, |
0c6feb07 | 701 | { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip}, |
c770844c KS |
702 | { /* sentinel */ }, |
703 | }; | |
704 | MODULE_DEVICE_TABLE(of, davinci_gpio_ids); | |
c770844c | 705 | |
118150f2 KS |
706 | static struct platform_driver davinci_gpio_driver = { |
707 | .probe = davinci_gpio_probe, | |
708 | .driver = { | |
c770844c | 709 | .name = "davinci_gpio", |
0651a730 | 710 | .pm = pm_sleep_ptr(&davinci_gpio_dev_pm_ops), |
c770844c | 711 | .of_match_table = of_match_ptr(davinci_gpio_ids), |
118150f2 KS |
712 | }, |
713 | }; | |
714 | ||
8e84a8e6 | 715 | /* |
118150f2 KS |
716 | * GPIO driver registration needs to be done before machine_init functions |
717 | * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall. | |
718 | */ | |
719 | static int __init davinci_gpio_drv_reg(void) | |
720 | { | |
721 | return platform_driver_register(&davinci_gpio_driver); | |
722 | } | |
723 | postcore_initcall(davinci_gpio_drv_reg); | |
8dab99c9 GLR |
724 | |
725 | static void __exit davinci_gpio_exit(void) | |
726 | { | |
727 | platform_driver_unregister(&davinci_gpio_driver); | |
728 | } | |
729 | module_exit(davinci_gpio_exit); | |
730 | ||
731 | MODULE_AUTHOR("Jan Kotas <jank@cadence.com>"); | |
732 | MODULE_DESCRIPTION("DAVINCI GPIO driver"); | |
733 | MODULE_LICENSE("GPL"); | |
734 | MODULE_ALIAS("platform:gpio-davinci"); |