Commit | Line | Data |
---|---|---|
2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
3d9edf09 VB |
2 | /* |
3 | * TI DaVinci GPIO Support | |
4 | * | |
dce1115b | 5 | * Copyright (c) 2006-2007 David Brownell |
3d9edf09 | 6 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> |
3d9edf09 | 7 | */ |
79b73ff9 | 8 | |
7220c43a | 9 | #include <linux/gpio/driver.h> |
3d9edf09 VB |
10 | #include <linux/errno.h> |
11 | #include <linux/kernel.h> | |
3d9edf09 VB |
12 | #include <linux/clk.h> |
13 | #include <linux/err.h> | |
14 | #include <linux/io.h> | |
118150f2 | 15 | #include <linux/irq.h> |
9211ff31 | 16 | #include <linux/irqdomain.h> |
c770844c KS |
17 | #include <linux/module.h> |
18 | #include <linux/of.h> | |
19 | #include <linux/of_device.h> | |
3c87d7c8 | 20 | #include <linux/pinctrl/consumer.h> |
118150f2 KS |
21 | #include <linux/platform_device.h> |
22 | #include <linux/platform_data/gpio-davinci.h> | |
0d978eb7 | 23 | #include <linux/irqchip/chained_irq.h> |
79b73ff9 AD |
24 | #include <linux/spinlock.h> |
25 | ||
26 | #include <asm-generic/gpio.h> | |
27 | ||
28 | #define MAX_REGS_BANKS 5 | |
29 | #define MAX_INT_PER_BANK 32 | |
3d9edf09 | 30 | |
c12f415a CC |
31 | struct davinci_gpio_regs { |
32 | u32 dir; | |
33 | u32 out_data; | |
34 | u32 set_data; | |
35 | u32 clr_data; | |
36 | u32 in_data; | |
37 | u32 set_rising; | |
38 | u32 clr_rising; | |
39 | u32 set_falling; | |
40 | u32 clr_falling; | |
41 | u32 intstat; | |
42 | }; | |
43 | ||
0c6feb07 GS |
44 | typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq); |
45 | ||
131a10a3 PA |
46 | #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ |
47 | ||
b8d44293 | 48 | static void __iomem *gpio_base; |
8f7cf8c6 | 49 | static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0}; |
3d9edf09 | 50 | |
79b73ff9 AD |
51 | struct davinci_gpio_irq_data { |
52 | void __iomem *regs; | |
53 | struct davinci_gpio_controller *chip; | |
54 | int bank_num; | |
55 | }; | |
56 | ||
57 | struct davinci_gpio_controller { | |
58 | struct gpio_chip chip; | |
59 | struct irq_domain *irq_domain; | |
60 | /* Serialize access to GPIO registers */ | |
61 | spinlock_t lock; | |
62 | void __iomem *regs[MAX_REGS_BANKS]; | |
63 | int gpio_unbanked; | |
64 | int irqs[MAX_INT_PER_BANK]; | |
65 | }; | |
66 | ||
67 | static inline u32 __gpio_mask(unsigned gpio) | |
68 | { | |
69 | return 1 << (gpio % 32); | |
70 | } | |
71 | ||
1765d671 | 72 | static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d) |
21ce873d | 73 | { |
99e9e52d | 74 | struct davinci_gpio_regs __iomem *g; |
21ce873d | 75 | |
1765d671 | 76 | g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d); |
21ce873d KH |
77 | |
78 | return g; | |
79 | } | |
80 | ||
eb3744a2 | 81 | static int davinci_gpio_irq_setup(struct platform_device *pdev); |
dce1115b DB |
82 | |
83 | /*--------------------------------------------------------------------------*/ | |
84 | ||
5b3a05ca | 85 | /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ |
ba4a984e CC |
86 | static inline int __davinci_direction(struct gpio_chip *chip, |
87 | unsigned offset, bool out, int value) | |
3d9edf09 | 88 | { |
72a1ca2c | 89 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
b5cf3fd8 | 90 | struct davinci_gpio_regs __iomem *g; |
b27b6d03 | 91 | unsigned long flags; |
dce1115b | 92 | u32 temp; |
b5cf3fd8 K |
93 | int bank = offset / 32; |
94 | u32 mask = __gpio_mask(offset); | |
3d9edf09 | 95 | |
b5cf3fd8 | 96 | g = d->regs[bank]; |
b27b6d03 | 97 | spin_lock_irqsave(&d->lock, flags); |
388291c3 | 98 | temp = readl_relaxed(&g->dir); |
ba4a984e CC |
99 | if (out) { |
100 | temp &= ~mask; | |
388291c3 | 101 | writel_relaxed(mask, value ? &g->set_data : &g->clr_data); |
ba4a984e CC |
102 | } else { |
103 | temp |= mask; | |
104 | } | |
388291c3 | 105 | writel_relaxed(temp, &g->dir); |
b27b6d03 | 106 | spin_unlock_irqrestore(&d->lock, flags); |
3d9edf09 | 107 | |
dce1115b DB |
108 | return 0; |
109 | } | |
3d9edf09 | 110 | |
ba4a984e CC |
111 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) |
112 | { | |
113 | return __davinci_direction(chip, offset, false, 0); | |
114 | } | |
115 | ||
116 | static int | |
117 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) | |
118 | { | |
119 | return __davinci_direction(chip, offset, true, value); | |
120 | } | |
121 | ||
3d9edf09 VB |
122 | /* |
123 | * Read the pin's value (works even if it's set up as output); | |
124 | * returns zero/nonzero. | |
125 | * | |
126 | * Note that changes are synched to the GPIO clock, so reading values back | |
127 | * right after you've set them may give old values. | |
128 | */ | |
dce1115b | 129 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
3d9edf09 | 130 | { |
72a1ca2c | 131 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
b5cf3fd8 K |
132 | struct davinci_gpio_regs __iomem *g; |
133 | int bank = offset / 32; | |
3d9edf09 | 134 | |
b5cf3fd8 K |
135 | g = d->regs[bank]; |
136 | ||
137 | return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data)); | |
3d9edf09 | 138 | } |
3d9edf09 | 139 | |
dce1115b DB |
140 | /* |
141 | * Assuming the pin is muxed as a gpio output, set its output value. | |
142 | */ | |
143 | static void | |
144 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
3d9edf09 | 145 | { |
72a1ca2c | 146 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
b5cf3fd8 K |
147 | struct davinci_gpio_regs __iomem *g; |
148 | int bank = offset / 32; | |
3d9edf09 | 149 | |
b5cf3fd8 K |
150 | g = d->regs[bank]; |
151 | ||
152 | writel_relaxed(__gpio_mask(offset), | |
153 | value ? &g->set_data : &g->clr_data); | |
dce1115b DB |
154 | } |
155 | ||
c770844c KS |
156 | static struct davinci_gpio_platform_data * |
157 | davinci_gpio_get_pdata(struct platform_device *pdev) | |
158 | { | |
159 | struct device_node *dn = pdev->dev.of_node; | |
160 | struct davinci_gpio_platform_data *pdata; | |
161 | int ret; | |
162 | u32 val; | |
163 | ||
164 | if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) | |
ab128afc | 165 | return dev_get_platdata(&pdev->dev); |
c770844c KS |
166 | |
167 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
168 | if (!pdata) | |
169 | return NULL; | |
170 | ||
171 | ret = of_property_read_u32(dn, "ti,ngpio", &val); | |
172 | if (ret) | |
173 | goto of_err; | |
174 | ||
175 | pdata->ngpio = val; | |
176 | ||
177 | ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val); | |
178 | if (ret) | |
179 | goto of_err; | |
180 | ||
181 | pdata->gpio_unbanked = val; | |
182 | ||
183 | return pdata; | |
184 | ||
185 | of_err: | |
186 | dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret); | |
187 | return NULL; | |
188 | } | |
189 | ||
118150f2 | 190 | static int davinci_gpio_probe(struct platform_device *pdev) |
dce1115b | 191 | { |
c809e37a | 192 | int bank, i, ret = 0; |
eb3744a2 | 193 | unsigned int ngpio, nbank, nirq; |
118150f2 KS |
194 | struct davinci_gpio_controller *chips; |
195 | struct davinci_gpio_platform_data *pdata; | |
118150f2 | 196 | struct device *dev = &pdev->dev; |
118150f2 | 197 | |
c770844c | 198 | pdata = davinci_gpio_get_pdata(pdev); |
118150f2 KS |
199 | if (!pdata) { |
200 | dev_err(dev, "No platform data found\n"); | |
201 | return -EINVAL; | |
202 | } | |
686b634a | 203 | |
c770844c KS |
204 | dev->platform_data = pdata; |
205 | ||
a994955c MG |
206 | /* |
207 | * The gpio banks conceptually expose a segmented bitmap, | |
474dad54 DB |
208 | * and "ngpio" is one more than the largest zero-based |
209 | * bit index that's valid. | |
210 | */ | |
118150f2 | 211 | ngpio = pdata->ngpio; |
a994955c | 212 | if (ngpio == 0) { |
118150f2 | 213 | dev_err(dev, "How many GPIOs?\n"); |
474dad54 DB |
214 | return -EINVAL; |
215 | } | |
216 | ||
c21d500b GS |
217 | if (WARN_ON(ARCH_NR_GPIOS < ngpio)) |
218 | ngpio = ARCH_NR_GPIOS; | |
474dad54 | 219 | |
eb3744a2 K |
220 | /* |
221 | * If there are unbanked interrupts then the number of | |
222 | * interrupts is equal to number of gpios else all are banked so | |
223 | * number of interrupts is equal to number of banks(each with 16 gpios) | |
224 | */ | |
225 | if (pdata->gpio_unbanked) | |
226 | nirq = pdata->gpio_unbanked; | |
227 | else | |
228 | nirq = DIV_ROUND_UP(ngpio, 16); | |
229 | ||
c809e37a | 230 | chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL); |
9ea9363c | 231 | if (!chips) |
b8d44293 | 232 | return -ENOMEM; |
118150f2 | 233 | |
fa7569c8 | 234 | gpio_base = devm_platform_ioremap_resource(pdev, 0); |
118150f2 KS |
235 | if (IS_ERR(gpio_base)) |
236 | return PTR_ERR(gpio_base); | |
b8d44293 | 237 | |
eb3744a2 K |
238 | for (i = 0; i < nirq; i++) { |
239 | chips->irqs[i] = platform_get_irq(pdev, i); | |
33b78b5f KK |
240 | if (chips->irqs[i] < 0) |
241 | return dev_err_probe(dev, chips->irqs[i], "IRQ not populated\n"); | |
c1d013a7 K |
242 | } |
243 | ||
587f7a69 | 244 | chips->chip.label = dev_name(dev); |
dce1115b | 245 | |
b5cf3fd8 K |
246 | chips->chip.direction_input = davinci_direction_in; |
247 | chips->chip.get = davinci_gpio_get; | |
248 | chips->chip.direction_output = davinci_direction_out; | |
249 | chips->chip.set = davinci_gpio_set; | |
dce1115b | 250 | |
b5cf3fd8 | 251 | chips->chip.ngpio = ngpio; |
786a9ab1 | 252 | chips->chip.base = pdata->no_auto_base ? pdata->base : -1; |
dce1115b | 253 | |
c770844c | 254 | #ifdef CONFIG_OF_GPIO |
b5cf3fd8 | 255 | chips->chip.of_gpio_n_cells = 2; |
b5cf3fd8 K |
256 | chips->chip.parent = dev; |
257 | chips->chip.of_node = dev->of_node; | |
f0254b51 TR |
258 | chips->chip.request = gpiochip_generic_request; |
259 | chips->chip.free = gpiochip_generic_free; | |
c770844c | 260 | #endif |
b5cf3fd8 | 261 | spin_lock_init(&chips->lock); |
dce1115b | 262 | |
c809e37a AD |
263 | nbank = DIV_ROUND_UP(ngpio, 32); |
264 | for (bank = 0; bank < nbank; bank++) | |
b5cf3fd8 | 265 | chips->regs[bank] = gpio_base + offset_array[bank]; |
3d9edf09 | 266 | |
8327e1ba K |
267 | ret = devm_gpiochip_add_data(dev, &chips->chip, chips); |
268 | if (ret) | |
587f7a69 | 269 | return ret; |
8327e1ba | 270 | |
118150f2 | 271 | platform_set_drvdata(pdev, chips); |
eb3744a2 | 272 | ret = davinci_gpio_irq_setup(pdev); |
5e7a0ce7 | 273 | if (ret) |
587f7a69 | 274 | return ret; |
5e7a0ce7 | 275 | |
3d9edf09 VB |
276 | return 0; |
277 | } | |
3d9edf09 | 278 | |
dce1115b | 279 | /*--------------------------------------------------------------------------*/ |
3d9edf09 VB |
280 | /* |
281 | * We expect irqs will normally be set up as input pins, but they can also be | |
282 | * used as output pins ... which is convenient for testing. | |
283 | * | |
474dad54 | 284 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
7a36071e | 285 | * to their GPIOBNK0 irq, with a bit less overhead. |
3d9edf09 | 286 | * |
474dad54 | 287 | * All those INTC hookups (direct, plus several IRQ banks) can also |
3d9edf09 VB |
288 | * serve as EDMA event triggers. |
289 | */ | |
290 | ||
23265442 | 291 | static void gpio_irq_disable(struct irq_data *d) |
3d9edf09 | 292 | { |
1765d671 | 293 | struct davinci_gpio_regs __iomem *g = irq2regs(d); |
36c05519 | 294 | uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d); |
3d9edf09 | 295 | |
388291c3 LP |
296 | writel_relaxed(mask, &g->clr_falling); |
297 | writel_relaxed(mask, &g->clr_rising); | |
3d9edf09 VB |
298 | } |
299 | ||
23265442 | 300 | static void gpio_irq_enable(struct irq_data *d) |
3d9edf09 | 301 | { |
1765d671 | 302 | struct davinci_gpio_regs __iomem *g = irq2regs(d); |
36c05519 | 303 | uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d); |
5093aec8 | 304 | unsigned status = irqd_get_trigger_type(d); |
3d9edf09 | 305 | |
df4aab46 DB |
306 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
307 | if (!status) | |
308 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | |
309 | ||
310 | if (status & IRQ_TYPE_EDGE_FALLING) | |
388291c3 | 311 | writel_relaxed(mask, &g->set_falling); |
df4aab46 | 312 | if (status & IRQ_TYPE_EDGE_RISING) |
388291c3 | 313 | writel_relaxed(mask, &g->set_rising); |
3d9edf09 VB |
314 | } |
315 | ||
23265442 | 316 | static int gpio_irq_type(struct irq_data *d, unsigned trigger) |
3d9edf09 | 317 | { |
3d9edf09 VB |
318 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
319 | return -EINVAL; | |
320 | ||
3d9edf09 VB |
321 | return 0; |
322 | } | |
323 | ||
324 | static struct irq_chip gpio_irqchip = { | |
325 | .name = "GPIO", | |
23265442 LB |
326 | .irq_enable = gpio_irq_enable, |
327 | .irq_disable = gpio_irq_disable, | |
328 | .irq_set_type = gpio_irq_type, | |
5093aec8 | 329 | .flags = IRQCHIP_SET_TYPE_MASKED, |
3d9edf09 VB |
330 | }; |
331 | ||
bd0b9ac4 | 332 | static void gpio_irq_handler(struct irq_desc *desc) |
3d9edf09 | 333 | { |
74164016 | 334 | struct davinci_gpio_regs __iomem *g; |
3d9edf09 | 335 | u32 mask = 0xffff; |
b5cf3fd8 | 336 | int bank_num; |
f299bb95 | 337 | struct davinci_gpio_controller *d; |
b5cf3fd8 | 338 | struct davinci_gpio_irq_data *irqdata; |
3d9edf09 | 339 | |
b5cf3fd8 K |
340 | irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc); |
341 | bank_num = irqdata->bank_num; | |
342 | g = irqdata->regs; | |
343 | d = irqdata->chip; | |
74164016 | 344 | |
3d9edf09 | 345 | /* we only care about one bank */ |
b5cf3fd8 | 346 | if ((bank_num % 2) == 1) |
3d9edf09 VB |
347 | mask <<= 16; |
348 | ||
349 | /* temporarily mask (level sensitive) parent IRQ */ | |
0d978eb7 | 350 | chained_irq_enter(irq_desc_get_chip(desc), desc); |
3d9edf09 VB |
351 | while (1) { |
352 | u32 status; | |
9211ff31 | 353 | int bit; |
b5cf3fd8 | 354 | irq_hw_number_t hw_irq; |
3d9edf09 VB |
355 | |
356 | /* ack any irqs */ | |
388291c3 | 357 | status = readl_relaxed(&g->intstat) & mask; |
3d9edf09 VB |
358 | if (!status) |
359 | break; | |
388291c3 | 360 | writel_relaxed(status, &g->intstat); |
3d9edf09 VB |
361 | |
362 | /* now demux them to the right lowlevel handler */ | |
f299bb95 | 363 | |
3d9edf09 | 364 | while (status) { |
9211ff31 LP |
365 | bit = __ffs(status); |
366 | status &= ~BIT(bit); | |
b5cf3fd8 K |
367 | /* Max number of gpios per controller is 144 so |
368 | * hw_irq will be in [0..143] | |
369 | */ | |
370 | hw_irq = (bank_num / 2) * 32 + bit; | |
371 | ||
9211ff31 | 372 | generic_handle_irq( |
b5cf3fd8 | 373 | irq_find_mapping(d->irq_domain, hw_irq)); |
3d9edf09 VB |
374 | } |
375 | } | |
0d978eb7 | 376 | chained_irq_exit(irq_desc_get_chip(desc), desc); |
3d9edf09 VB |
377 | /* now it may re-trigger */ |
378 | } | |
379 | ||
7a36071e DB |
380 | static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) |
381 | { | |
72a1ca2c | 382 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
7a36071e | 383 | |
6075a8b2 | 384 | if (d->irq_domain) |
b5cf3fd8 | 385 | return irq_create_mapping(d->irq_domain, offset); |
6075a8b2 GS |
386 | else |
387 | return -ENXIO; | |
7a36071e DB |
388 | } |
389 | ||
390 | static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) | |
391 | { | |
72a1ca2c | 392 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
7a36071e | 393 | |
131a10a3 PA |
394 | /* |
395 | * NOTE: we assume for now that only irqs in the first gpio_chip | |
7a36071e DB |
396 | * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). |
397 | */ | |
34af1ab4 | 398 | if (offset < d->gpio_unbanked) |
eb3744a2 | 399 | return d->irqs[offset]; |
7a36071e DB |
400 | else |
401 | return -ENODEV; | |
402 | } | |
403 | ||
ab2dde99 | 404 | static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) |
7a36071e | 405 | { |
ab2dde99 SN |
406 | struct davinci_gpio_controller *d; |
407 | struct davinci_gpio_regs __iomem *g; | |
eb3744a2 | 408 | u32 mask, i; |
ab2dde99 | 409 | |
c16edb8b | 410 | d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data); |
7f8e2a85 | 411 | g = (struct davinci_gpio_regs __iomem *)d->regs[0]; |
eb3744a2 K |
412 | for (i = 0; i < MAX_INT_PER_BANK; i++) |
413 | if (data->irq == d->irqs[i]) | |
414 | break; | |
415 | ||
416 | if (i == MAX_INT_PER_BANK) | |
417 | return -EINVAL; | |
418 | ||
419 | mask = __gpio_mask(i); | |
7a36071e DB |
420 | |
421 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
422 | return -EINVAL; | |
423 | ||
388291c3 | 424 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) |
7a36071e | 425 | ? &g->set_falling : &g->clr_falling); |
388291c3 | 426 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) |
7a36071e DB |
427 | ? &g->set_rising : &g->clr_rising); |
428 | ||
429 | return 0; | |
430 | } | |
431 | ||
9211ff31 LP |
432 | static int |
433 | davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, | |
434 | irq_hw_number_t hw) | |
435 | { | |
8f7cf8c6 K |
436 | struct davinci_gpio_controller *chips = |
437 | (struct davinci_gpio_controller *)d->host_data; | |
b5cf3fd8 | 438 | struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32]; |
9211ff31 LP |
439 | |
440 | irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, | |
441 | "davinci_gpio"); | |
442 | irq_set_irq_type(irq, IRQ_TYPE_NONE); | |
443 | irq_set_chip_data(irq, (__force void *)g); | |
36c05519 | 444 | irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw)); |
9211ff31 LP |
445 | |
446 | return 0; | |
447 | } | |
448 | ||
449 | static const struct irq_domain_ops davinci_gpio_irq_ops = { | |
450 | .map = davinci_gpio_irq_map, | |
451 | .xlate = irq_domain_xlate_onetwocell, | |
452 | }; | |
453 | ||
0c6feb07 GS |
454 | static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq) |
455 | { | |
456 | static struct irq_chip_type gpio_unbanked; | |
457 | ||
ccdbddfe | 458 | gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq)); |
0c6feb07 GS |
459 | |
460 | return &gpio_unbanked.chip; | |
461 | }; | |
462 | ||
463 | static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq) | |
464 | { | |
465 | static struct irq_chip gpio_unbanked; | |
466 | ||
467 | gpio_unbanked = *irq_get_chip(irq); | |
468 | return &gpio_unbanked; | |
469 | }; | |
470 | ||
471 | static const struct of_device_id davinci_gpio_ids[]; | |
472 | ||
3d9edf09 | 473 | /* |
474dad54 DB |
474 | * NOTE: for suspend/resume, probably best to make a platform_device with |
475 | * suspend_late/resume_resume calls hooking into results of the set_wake() | |
3d9edf09 VB |
476 | * calls ... so if no gpios are wakeup events the clock can be disabled, |
477 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 | |
474dad54 | 478 | * (dm6446) can be set appropriately for GPIOV33 pins. |
3d9edf09 VB |
479 | */ |
480 | ||
eb3744a2 | 481 | static int davinci_gpio_irq_setup(struct platform_device *pdev) |
3d9edf09 | 482 | { |
58c0f5aa AS |
483 | unsigned gpio, bank; |
484 | int irq; | |
6dc0048c | 485 | int ret; |
3d9edf09 | 486 | struct clk *clk; |
474dad54 | 487 | u32 binten = 0; |
c1d013a7 | 488 | unsigned ngpio; |
118150f2 | 489 | struct device *dev = &pdev->dev; |
118150f2 KS |
490 | struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); |
491 | struct davinci_gpio_platform_data *pdata = dev->platform_data; | |
492 | struct davinci_gpio_regs __iomem *g; | |
6075a8b2 | 493 | struct irq_domain *irq_domain = NULL; |
0c6feb07 GS |
494 | const struct of_device_id *match; |
495 | struct irq_chip *irq_chip; | |
b5cf3fd8 | 496 | struct davinci_gpio_irq_data *irqdata; |
0c6feb07 GS |
497 | gpio_get_irq_chip_cb_t gpio_get_irq_chip; |
498 | ||
499 | /* | |
500 | * Use davinci_gpio_get_irq_chip by default to handle non DT cases | |
501 | */ | |
502 | gpio_get_irq_chip = davinci_gpio_get_irq_chip; | |
503 | match = of_match_device(of_match_ptr(davinci_gpio_ids), | |
504 | dev); | |
505 | if (match) | |
506 | gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data; | |
a994955c | 507 | |
118150f2 | 508 | ngpio = pdata->ngpio; |
3d9edf09 | 509 | |
118150f2 | 510 | clk = devm_clk_get(dev, "gpio"); |
3d9edf09 | 511 | if (IS_ERR(clk)) { |
1a9ef909 | 512 | dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk)); |
474dad54 | 513 | return PTR_ERR(clk); |
3d9edf09 | 514 | } |
eb3744a2 | 515 | |
6dc0048c AY |
516 | ret = clk_prepare_enable(clk); |
517 | if (ret) | |
518 | return ret; | |
3d9edf09 | 519 | |
6075a8b2 | 520 | if (!pdata->gpio_unbanked) { |
a1a3c2d5 | 521 | irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0); |
6075a8b2 GS |
522 | if (irq < 0) { |
523 | dev_err(dev, "Couldn't allocate IRQ numbers\n"); | |
6dc0048c | 524 | clk_disable_unprepare(clk); |
6075a8b2 GS |
525 | return irq; |
526 | } | |
9211ff31 | 527 | |
310a7e60 | 528 | irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0, |
6075a8b2 GS |
529 | &davinci_gpio_irq_ops, |
530 | chips); | |
531 | if (!irq_domain) { | |
532 | dev_err(dev, "Couldn't register an IRQ domain\n"); | |
6dc0048c | 533 | clk_disable_unprepare(clk); |
6075a8b2 GS |
534 | return -ENODEV; |
535 | } | |
9211ff31 LP |
536 | } |
537 | ||
131a10a3 PA |
538 | /* |
539 | * Arrange gpio_to_irq() support, handling either direct IRQs or | |
7a36071e DB |
540 | * banked IRQs. Having GPIOs in the first GPIO bank use direct |
541 | * IRQs, while the others use banked IRQs, would need some setup | |
542 | * tweaks to recognize hardware which can do that. | |
543 | */ | |
b5cf3fd8 K |
544 | chips->chip.to_irq = gpio_to_irq_banked; |
545 | chips->irq_domain = irq_domain; | |
7a36071e DB |
546 | |
547 | /* | |
548 | * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO | |
549 | * controller only handling trigger modes. We currently assume no | |
550 | * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. | |
551 | */ | |
118150f2 | 552 | if (pdata->gpio_unbanked) { |
7a36071e | 553 | /* pass "bank 0" GPIO IRQs to AINTC */ |
b5cf3fd8 | 554 | chips->chip.to_irq = gpio_to_irq_unbanked; |
b5cf3fd8 | 555 | chips->gpio_unbanked = pdata->gpio_unbanked; |
3685bbce | 556 | binten = GENMASK(pdata->gpio_unbanked / 16, 0); |
7a36071e DB |
557 | |
558 | /* AINTC handles mask/unmask; GPIO handles triggering */ | |
eb3744a2 | 559 | irq = chips->irqs[0]; |
0c6feb07 GS |
560 | irq_chip = gpio_get_irq_chip(irq); |
561 | irq_chip->name = "GPIO-AINTC"; | |
562 | irq_chip->irq_set_type = gpio_irq_type_unbanked; | |
7a36071e DB |
563 | |
564 | /* default trigger: both edges */ | |
b5cf3fd8 | 565 | g = chips->regs[0]; |
388291c3 LP |
566 | writel_relaxed(~0, &g->set_falling); |
567 | writel_relaxed(~0, &g->set_rising); | |
7a36071e DB |
568 | |
569 | /* set the direct IRQs up to use that irqchip */ | |
eb3744a2 K |
570 | for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) { |
571 | irq_set_chip(chips->irqs[gpio], irq_chip); | |
572 | irq_set_handler_data(chips->irqs[gpio], chips); | |
573 | irq_set_status_flags(chips->irqs[gpio], | |
574 | IRQ_TYPE_EDGE_BOTH); | |
7a36071e DB |
575 | } |
576 | ||
577 | goto done; | |
578 | } | |
579 | ||
580 | /* | |
581 | * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we | |
582 | * then chain through our own handler. | |
583 | */ | |
eb3744a2 | 584 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) { |
8f7cf8c6 K |
585 | /* disabled by default, enabled only as needed |
586 | * There are register sets for 32 GPIOs. 2 banks of 16 | |
587 | * GPIOs are covered by each set of registers hence divide by 2 | |
588 | */ | |
b5cf3fd8 | 589 | g = chips->regs[bank / 2]; |
388291c3 LP |
590 | writel_relaxed(~0, &g->clr_falling); |
591 | writel_relaxed(~0, &g->clr_rising); | |
3d9edf09 | 592 | |
f299bb95 IY |
593 | /* |
594 | * Each chip handles 32 gpios, and each irq bank consists of 16 | |
595 | * gpio irqs. Pass the irq bank's corresponding controller to | |
596 | * the chained irq handler. | |
597 | */ | |
b5cf3fd8 K |
598 | irqdata = devm_kzalloc(&pdev->dev, |
599 | sizeof(struct | |
600 | davinci_gpio_irq_data), | |
601 | GFP_KERNEL); | |
6dc0048c AY |
602 | if (!irqdata) { |
603 | clk_disable_unprepare(clk); | |
b5cf3fd8 | 604 | return -ENOMEM; |
6dc0048c | 605 | } |
b5cf3fd8 K |
606 | |
607 | irqdata->regs = g; | |
608 | irqdata->bank_num = bank; | |
609 | irqdata->chip = chips; | |
610 | ||
eb3744a2 K |
611 | irq_set_chained_handler_and_data(chips->irqs[bank], |
612 | gpio_irq_handler, irqdata); | |
3d9edf09 | 613 | |
474dad54 | 614 | binten |= BIT(bank); |
3d9edf09 VB |
615 | } |
616 | ||
7a36071e | 617 | done: |
131a10a3 PA |
618 | /* |
619 | * BINTEN -- per-bank interrupt enable. genirq would also let these | |
3d9edf09 VB |
620 | * bits be set/cleared dynamically. |
621 | */ | |
388291c3 | 622 | writel_relaxed(binten, gpio_base + BINTEN); |
3d9edf09 | 623 | |
3d9edf09 VB |
624 | return 0; |
625 | } | |
118150f2 | 626 | |
c770844c | 627 | static const struct of_device_id davinci_gpio_ids[] = { |
0c6feb07 | 628 | { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip}, |
6a4d8b6b | 629 | { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip}, |
0c6feb07 | 630 | { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip}, |
c770844c KS |
631 | { /* sentinel */ }, |
632 | }; | |
633 | MODULE_DEVICE_TABLE(of, davinci_gpio_ids); | |
c770844c | 634 | |
118150f2 KS |
635 | static struct platform_driver davinci_gpio_driver = { |
636 | .probe = davinci_gpio_probe, | |
637 | .driver = { | |
c770844c | 638 | .name = "davinci_gpio", |
c770844c | 639 | .of_match_table = of_match_ptr(davinci_gpio_ids), |
118150f2 KS |
640 | }, |
641 | }; | |
642 | ||
643 | /** | |
644 | * GPIO driver registration needs to be done before machine_init functions | |
645 | * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall. | |
646 | */ | |
647 | static int __init davinci_gpio_drv_reg(void) | |
648 | { | |
649 | return platform_driver_register(&davinci_gpio_driver); | |
650 | } | |
651 | postcore_initcall(davinci_gpio_drv_reg); |