[linux-block.git] / drivers / gpio / gpio-crystalcove.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Intel Crystal Cove GPIO Driver
 *
 * Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
 *
 * Author: Yang, Bin <bin.yang@intel.com>
 */

#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
#include <linux/types.h>

#define CRYSTALCOVE_GPIO_NUM	16
#define CRYSTALCOVE_VGPIO_NUM	95

#define UPDATE_IRQ_TYPE		BIT(0)
#define UPDATE_IRQ_MASK		BIT(1)

#define GPIO0IRQ		0x0b
#define GPIO1IRQ		0x0c
#define MGPIO0IRQS0		0x19
#define MGPIO1IRQS0		0x1a
#define MGPIO0IRQSX		0x1b
#define MGPIO1IRQSX		0x1c
#define GPIO0P0CTLO		0x2b
#define GPIO0P0CTLI		0x33
#define GPIO1P0CTLO		0x3b
#define GPIO1P0CTLI		0x43
#define GPIOPANELCTL		0x52

#define CTLI_INTCNT_DIS		(0)
#define CTLI_INTCNT_NE		(1 << 1)
#define CTLI_INTCNT_PE		(2 << 1)
#define CTLI_INTCNT_BE		(3 << 1)

#define CTLO_DIR_IN		(0)
#define CTLO_DIR_OUT		(1 << 5)

#define CTLO_DRV_CMOS		(0)
#define CTLO_DRV_OD		(1 << 4)

#define CTLO_DRV_REN		(1 << 3)

#define CTLO_RVAL_2KDW		(0)
#define CTLO_RVAL_2KUP		(1 << 1)
#define CTLO_RVAL_50KDW		(2 << 1)
#define CTLO_RVAL_50KUP		(3 << 1)

#define CTLO_INPUT_SET	(CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
#define CTLO_OUTPUT_SET	(CTLO_DIR_OUT | CTLO_INPUT_SET)

enum ctrl_register {
	CTRL_IN,
	CTRL_OUT,
};

/**
 * struct crystalcove_gpio - Crystal Cove GPIO controller
 * @buslock: for bus lock/sync and unlock.
 * @chip: the abstract gpio_chip structure.
 * @regmap: the regmap from the parent device.
 * @update: pending IRQ setting update, to be written to the chip upon unlock.
 * @intcnt_value: the Interrupt Detect value to be written.
 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
 */
struct crystalcove_gpio {
	struct mutex buslock; /* irq_bus_lock */
	struct gpio_chip chip;
	struct regmap *regmap;
	int update;
	int intcnt_value;
	bool set_irq_mask;
};

static inline int to_reg(int gpio, enum ctrl_register reg_type)
{
	int reg;

	if (gpio >= CRYSTALCOVE_GPIO_NUM) {
		/*
		 * Virtual GPIO called from ACPI, for now we only support
		 * the panel ctl.
		 */
		switch (gpio) {
		case 0x5e:
			return GPIOPANELCTL;
		default:
			return -EOPNOTSUPP;
		}
	}

	if (reg_type == CTRL_IN) {
		if (gpio < 8)
			reg = GPIO0P0CTLI;
		else
			reg = GPIO1P0CTLI;
	} else {
		if (gpio < 8)
			reg = GPIO0P0CTLO;
		else
			reg = GPIO1P0CTLO;
	}

	return reg + gpio % 8;
}

static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg, int gpio)
{
	u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
	int mask = BIT(gpio % 8);

	if (cg->set_irq_mask)
		regmap_update_bits(cg->regmap, mirqs0, mask, mask);
	else
		regmap_update_bits(cg->regmap, mirqs0, mask, 0);
}

static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
{
	int reg = to_reg(gpio, CTRL_IN);

	regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
}

static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
{
	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
	int reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return 0;

	return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
}

static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, int value)
{
	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
	int reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return 0;

	return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value);
}

static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
{
	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
	unsigned int val;
	int ret, reg = to_reg(gpio, CTRL_IN);

	if (reg < 0)
		return 0;

	ret = regmap_read(cg->regmap, reg, &val);
	if (ret)
		return ret;

	return val & 0x1;
}

static void crystalcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
{
	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
	int reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return;

	if (value)
		regmap_update_bits(cg->regmap, reg, 1, 1);
	else
		regmap_update_bits(cg->regmap, reg, 1, 0);
}

static int crystalcove_irq_type(struct irq_data *data, unsigned int type)
{
	struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
	irq_hw_number_t hwirq = irqd_to_hwirq(data);

	if (hwirq >= CRYSTALCOVE_GPIO_NUM)
		return 0;

	switch (type) {
	case IRQ_TYPE_NONE:
		cg->intcnt_value = CTLI_INTCNT_DIS;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		cg->intcnt_value = CTLI_INTCNT_BE;
		break;
	case IRQ_TYPE_EDGE_RISING:
		cg->intcnt_value = CTLI_INTCNT_PE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		cg->intcnt_value = CTLI_INTCNT_NE;
		break;
	default:
		return -EINVAL;
	}

	cg->update |= UPDATE_IRQ_TYPE;

	return 0;
}

static void crystalcove_bus_lock(struct irq_data *data)
{
	struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));

	mutex_lock(&cg->buslock);
}

static void crystalcove_bus_sync_unlock(struct irq_data *data)
{
	struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
	irq_hw_number_t hwirq = irqd_to_hwirq(data);

	if (cg->update & UPDATE_IRQ_TYPE)
		crystalcove_update_irq_ctrl(cg, hwirq);
	if (cg->update & UPDATE_IRQ_MASK)
		crystalcove_update_irq_mask(cg, hwirq);
	cg->update = 0;

	mutex_unlock(&cg->buslock);
}

static void crystalcove_irq_unmask(struct irq_data *data)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
	struct crystalcove_gpio *cg = gpiochip_get_data(gc);
	irq_hw_number_t hwirq = irqd_to_hwirq(data);

	if (hwirq >= CRYSTALCOVE_GPIO_NUM)
		return;

	gpiochip_enable_irq(gc, hwirq);

	cg->set_irq_mask = false;
	cg->update |= UPDATE_IRQ_MASK;
}

static void crystalcove_irq_mask(struct irq_data *data)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
	struct crystalcove_gpio *cg = gpiochip_get_data(gc);
	irq_hw_number_t hwirq = irqd_to_hwirq(data);

	if (hwirq >= CRYSTALCOVE_GPIO_NUM)
		return;

	cg->set_irq_mask = true;
	cg->update |= UPDATE_IRQ_MASK;

	gpiochip_disable_irq(gc, hwirq);
}

static const struct irq_chip crystalcove_irqchip = {
	.name			= "Crystal Cove",
	.irq_mask		= crystalcove_irq_mask,
	.irq_unmask		= crystalcove_irq_unmask,
	.irq_set_type		= crystalcove_irq_type,
	.irq_bus_lock		= crystalcove_bus_lock,
	.irq_bus_sync_unlock	= crystalcove_bus_sync_unlock,
	.flags			= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
	GPIOCHIP_IRQ_RESOURCE_HELPERS,
};

static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
{
	struct crystalcove_gpio *cg = data;
	unsigned long pending;
	unsigned int p0, p1;
	int gpio;
	unsigned int virq;

	if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
	    regmap_read(cg->regmap, GPIO1IRQ, &p1))
		return IRQ_NONE;

	regmap_write(cg->regmap, GPIO0IRQ, p0);
	regmap_write(cg->regmap, GPIO1IRQ, p1);

	pending = p0 | p1 << 8;

	for_each_set_bit(gpio, &pending, CRYSTALCOVE_GPIO_NUM) {
		virq = irq_find_mapping(cg->chip.irq.domain, gpio);
		handle_nested_irq(virq);
	}

	return IRQ_HANDLED;
}

static void crystalcove_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
	int gpio, offset;
	unsigned int ctlo, ctli, mirqs0, mirqsx, irq;

	for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
		regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
		regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
			    &mirqs0);
		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
			    &mirqsx);
		regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
			    &irq);

		offset = gpio % 8;
		seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
			   gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
			   ctli & 0x1 ? "hi" : "lo",
			   ctli & CTLI_INTCNT_NE ? "fall" : "    ",
			   ctli & CTLI_INTCNT_PE ? "rise" : "    ",
			   ctlo,
			   mirqs0 & BIT(offset) ? "s0 mask  " : "s0 unmask",
			   mirqsx & BIT(offset) ? "sx mask  " : "sx unmask",
			   irq & BIT(offset) ? "pending" : "       ");
	}
}

static int crystalcove_gpio_probe(struct platform_device *pdev)
{
	int irq = platform_get_irq(pdev, 0);
	struct crystalcove_gpio *cg;
	int retval;
	struct device *dev = pdev->dev.parent;
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
	struct gpio_irq_chip *girq;

	if (irq < 0)
		return irq;

	cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
	if (!cg)
		return -ENOMEM;

	mutex_init(&cg->buslock);
	cg->chip.label = KBUILD_MODNAME;
	cg->chip.direction_input = crystalcove_gpio_dir_in;
	cg->chip.direction_output = crystalcove_gpio_dir_out;
	cg->chip.get = crystalcove_gpio_get;
	cg->chip.set = crystalcove_gpio_set;
	cg->chip.base = -1;
	cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;
	cg->chip.can_sleep = true;
	cg->chip.parent = dev;
	cg->chip.dbg_show = crystalcove_gpio_dbg_show;
	cg->regmap = pmic->regmap;

	girq = &cg->chip.irq;
	gpio_irq_chip_set_chip(girq, &crystalcove_irqchip);
	/* This will let us handle the parent IRQ in the driver */
	girq->parent_handler = NULL;
	girq->num_parents = 0;
	girq->parents = NULL;
	girq->default_type = IRQ_TYPE_NONE;
	girq->handler = handle_simple_irq;
	girq->threaded = true;

	retval = devm_request_threaded_irq(&pdev->dev, irq, NULL,
					   crystalcove_gpio_irq_handler,
					   IRQF_ONESHOT, KBUILD_MODNAME, cg);
	if (retval) {
		dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
		return retval;
	}

	retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg);
	if (retval)
		return retval;

	/* Distuingish IRQ domain from others sharing (MFD) the same fwnode */
	irq_domain_update_bus_token(cg->chip.irq.domain, DOMAIN_BUS_WIRED);

	return 0;
}

static struct platform_driver crystalcove_gpio_driver = {
	.probe = crystalcove_gpio_probe,
	.driver = {
		.name = "crystal_cove_gpio",
	},
};
module_platform_driver(crystalcove_gpio_driver);

MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
e8362430	1	// SPDX-License-Identifier: GPL-2.0
104fb1d5	2	/*
e8362430	3	* Intel Crystal Cove GPIO Driver
104fb1d5 ZL	4	*
	5	* Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
	6	*
104fb1d5 ZL	7	* Author: Yang, Bin <bin.yang@intel.com>
	8	*/
	9
78207c5b AS	10	#include <linux/bitops.h>
78207c5b AS	11	#include <linux/gpio/driver.h>
104fb1d5	12	#include <linux/interrupt.h>
78207c5b	13	#include <linux/mfd/intel_soc_pmic.h>
f1fb9c61	14	#include <linux/module.h>
104fb1d5	15	#include <linux/platform_device.h>
104fb1d5	16	#include <linux/regmap.h>
78207c5b	17	#include <linux/seq_file.h>
386cbe7f	18	#include <linux/types.h>
104fb1d5 ZL	19
104fb1d5 ZL	20	#define CRYSTALCOVE_GPIO_NUM 16
e189ca56	21	#define CRYSTALCOVE_VGPIO_NUM 95
104fb1d5 ZL	22
	23	#define UPDATE_IRQ_TYPE BIT(0)
	24	#define UPDATE_IRQ_MASK BIT(1)
	25
	26	#define GPIO0IRQ 0x0b
	27	#define GPIO1IRQ 0x0c
	28	#define MGPIO0IRQS0 0x19
	29	#define MGPIO1IRQS0 0x1a
	30	#define MGPIO0IRQSX 0x1b
	31	#define MGPIO1IRQSX 0x1c
	32	#define GPIO0P0CTLO 0x2b
	33	#define GPIO0P0CTLI 0x33
	34	#define GPIO1P0CTLO 0x3b
	35	#define GPIO1P0CTLI 0x43
e189ca56	36	#define GPIOPANELCTL 0x52
104fb1d5 ZL	37
	38	#define CTLI_INTCNT_DIS (0)
	39	#define CTLI_INTCNT_NE (1 << 1)
	40	#define CTLI_INTCNT_PE (2 << 1)
	41	#define CTLI_INTCNT_BE (3 << 1)
	42
	43	#define CTLO_DIR_IN (0)
	44	#define CTLO_DIR_OUT (1 << 5)
	45
	46	#define CTLO_DRV_CMOS (0)
	47	#define CTLO_DRV_OD (1 << 4)
	48
	49	#define CTLO_DRV_REN (1 << 3)
	50
	51	#define CTLO_RVAL_2KDW (0)
	52	#define CTLO_RVAL_2KUP (1 << 1)
	53	#define CTLO_RVAL_50KDW (2 << 1)
	54	#define CTLO_RVAL_50KUP (3 << 1)
	55
	56	#define CTLO_INPUT_SET (CTLO_DRV_CMOS \| CTLO_DRV_REN \| CTLO_RVAL_2KUP)
	57	#define CTLO_OUTPUT_SET (CTLO_DIR_OUT \| CTLO_INPUT_SET)
	58
	59	enum ctrl_register {
	60	CTRL_IN,
	61	CTRL_OUT,
	62	};
	63
	64	/**
	65	* struct crystalcove_gpio - Crystal Cove GPIO controller
	66	* @buslock: for bus lock/sync and unlock.
	67	* @chip: the abstract gpio_chip structure.
	68	* @regmap: the regmap from the parent device.
	69	* @update: pending IRQ setting update, to be written to the chip upon unlock.
	70	* @intcnt_value: the Interrupt Detect value to be written.
	71	* @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
	72	*/
	73	struct crystalcove_gpio {
	74	struct mutex buslock; /* irq_bus_lock */
	75	struct gpio_chip chip;
	76	struct regmap *regmap;
	77	int update;
	78	int intcnt_value;
	79	bool set_irq_mask;
	80	};
	81
104fb1d5 ZL	82	static inline int to_reg(int gpio, enum ctrl_register reg_type)
	83	{
	84	int reg;
	85
9a752b4c HG	86	if (gpio >= CRYSTALCOVE_GPIO_NUM) {
	87	/*
	88	* Virtual GPIO called from ACPI, for now we only support
	89	* the panel ctl.
	90	*/
	91	switch (gpio) {
	92	case 0x5e:
	93	return GPIOPANELCTL;
	94	default:
	95	return -EOPNOTSUPP;
	96	}
	97	}
e189ca56	98
104fb1d5 ZL	99	if (reg_type == CTRL_IN) {
	100	if (gpio < 8)
	101	reg = GPIO0P0CTLI;
	102	else
	103	reg = GPIO1P0CTLI;
	104	} else {
	105	if (gpio < 8)
	106	reg = GPIO0P0CTLO;
	107	else
	108	reg = GPIO1P0CTLO;
	109	}
	110
	111	return reg + gpio % 8;
	112	}
	113
68a12c19	114	static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg, int gpio)
104fb1d5 ZL	115	{
	116	u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
	117	int mask = BIT(gpio % 8);
	118
	119	if (cg->set_irq_mask)
	120	regmap_update_bits(cg->regmap, mirqs0, mask, mask);
	121	else
	122	regmap_update_bits(cg->regmap, mirqs0, mask, 0);
	123	}
	124
	125	static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
	126	{
	127	int reg = to_reg(gpio, CTRL_IN);
	128
	129	regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
	130	}
	131
3abbdbe3	132	static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
104fb1d5	133	{
435cc3d4	134	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
9a752b4c	135	int reg = to_reg(gpio, CTRL_OUT);
104fb1d5	136
9a752b4c	137	if (reg < 0)
dcdc3018 AL	138	return 0;
dcdc3018 AL	139
9a752b4c	140	return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
104fb1d5 ZL	141	}
104fb1d5 ZL	142
68a12c19	143	static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, int value)
104fb1d5	144	{
435cc3d4	145	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
9a752b4c	146	int reg = to_reg(gpio, CTRL_OUT);
104fb1d5	147
9a752b4c	148	if (reg < 0)
dcdc3018 AL	149	return 0;
dcdc3018 AL	150
9a752b4c	151	return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET \| value);
104fb1d5 ZL	152	}
104fb1d5 ZL	153
3abbdbe3	154	static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
104fb1d5	155	{
435cc3d4	156	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
104fb1d5	157	unsigned int val;
9a752b4c	158	int ret, reg = to_reg(gpio, CTRL_IN);
104fb1d5	159
9a752b4c	160	if (reg < 0)
dcdc3018 AL	161	return 0;
dcdc3018 AL	162
9a752b4c	163	ret = regmap_read(cg->regmap, reg, &val);
104fb1d5 ZL	164	if (ret)
	165	return ret;
	166
	167	return val & 0x1;
	168	}
	169
68a12c19	170	static void crystalcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
104fb1d5	171	{
435cc3d4	172	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
9a752b4c	173	int reg = to_reg(gpio, CTRL_OUT);
104fb1d5	174
9a752b4c	175	if (reg < 0)
dcdc3018 AL	176	return;
dcdc3018 AL	177
104fb1d5	178	if (value)
9a752b4c	179	regmap_update_bits(cg->regmap, reg, 1, 1);
104fb1d5	180	else
9a752b4c	181	regmap_update_bits(cg->regmap, reg, 1, 0);
104fb1d5 ZL	182	}
104fb1d5 ZL	183
3abbdbe3	184	static int crystalcove_irq_type(struct irq_data *data, unsigned int type)
104fb1d5	185	{
68a12c19	186	struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
b34d2ad7	187	irq_hw_number_t hwirq = irqd_to_hwirq(data);
104fb1d5	188
b34d2ad7	189	if (hwirq >= CRYSTALCOVE_GPIO_NUM)
9a752b4c HG	190	return 0;
9a752b4c HG	191
104fb1d5 ZL	192	switch (type) {
	193	case IRQ_TYPE_NONE:
	194	cg->intcnt_value = CTLI_INTCNT_DIS;
	195	break;
	196	case IRQ_TYPE_EDGE_BOTH:
	197	cg->intcnt_value = CTLI_INTCNT_BE;
	198	break;
	199	case IRQ_TYPE_EDGE_RISING:
	200	cg->intcnt_value = CTLI_INTCNT_PE;
	201	break;
	202	case IRQ_TYPE_EDGE_FALLING:
	203	cg->intcnt_value = CTLI_INTCNT_NE;
	204	break;
	205	default:
	206	return -EINVAL;
	207	}
	208
	209	cg->update \|= UPDATE_IRQ_TYPE;
	210
	211	return 0;
	212	}
	213
	214	static void crystalcove_bus_lock(struct irq_data *data)
	215	{
68a12c19	216	struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
104fb1d5 ZL	217
	218	mutex_lock(&cg->buslock);
	219	}
	220
	221	static void crystalcove_bus_sync_unlock(struct irq_data *data)
	222	{
68a12c19	223	struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
b34d2ad7	224	irq_hw_number_t hwirq = irqd_to_hwirq(data);
104fb1d5 ZL	225
104fb1d5 ZL	226	if (cg->update & UPDATE_IRQ_TYPE)
b34d2ad7	227	crystalcove_update_irq_ctrl(cg, hwirq);
104fb1d5	228	if (cg->update & UPDATE_IRQ_MASK)
b34d2ad7	229	crystalcove_update_irq_mask(cg, hwirq);
104fb1d5 ZL	230	cg->update = 0;
	231
	232	mutex_unlock(&cg->buslock);
	233	}
	234
	235	static void crystalcove_irq_unmask(struct irq_data *data)
	236	{
386cbe7f AS	237	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
	238	struct crystalcove_gpio *cg = gpiochip_get_data(gc);
	239	irq_hw_number_t hwirq = irqd_to_hwirq(data);
104fb1d5	240
386cbe7f AS	241	if (hwirq >= CRYSTALCOVE_GPIO_NUM)
	242	return;
	243
	244	gpiochip_enable_irq(gc, hwirq);
	245
	246	cg->set_irq_mask = false;
	247	cg->update \|= UPDATE_IRQ_MASK;
104fb1d5 ZL	248	}
	249
	250	static void crystalcove_irq_mask(struct irq_data *data)
	251	{
386cbe7f AS	252	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
	253	struct crystalcove_gpio *cg = gpiochip_get_data(gc);
	254	irq_hw_number_t hwirq = irqd_to_hwirq(data);
104fb1d5	255
386cbe7f AS	256	if (hwirq >= CRYSTALCOVE_GPIO_NUM)
	257	return;
	258
	259	cg->set_irq_mask = true;
	260	cg->update \|= UPDATE_IRQ_MASK;
	261
	262	gpiochip_disable_irq(gc, hwirq);
104fb1d5 ZL	263	}
104fb1d5 ZL	264
386cbe7f	265	static const struct irq_chip crystalcove_irqchip = {
104fb1d5 ZL	266	.name = "Crystal Cove",
	267	.irq_mask = crystalcove_irq_mask,
	268	.irq_unmask = crystalcove_irq_unmask,
	269	.irq_set_type = crystalcove_irq_type,
	270	.irq_bus_lock = crystalcove_bus_lock,
	271	.irq_bus_sync_unlock = crystalcove_bus_sync_unlock,
386cbe7f AS	272	.flags = IRQCHIP_SKIP_SET_WAKE \| IRQCHIP_IMMUTABLE,
386cbe7f AS	273	GPIOCHIP_IRQ_RESOURCE_HELPERS,
104fb1d5 ZL	274	};
	275
	276	static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
	277	{
	278	struct crystalcove_gpio *cg = data;
fcce88d9	279	unsigned long pending;
104fb1d5	280	unsigned int p0, p1;
104fb1d5 ZL	281	int gpio;
	282	unsigned int virq;
	283
	284	if (regmap_read(cg->regmap, GPIO0IRQ, &p0) \|\|
	285	regmap_read(cg->regmap, GPIO1IRQ, &p1))
	286	return IRQ_NONE;
	287
	288	regmap_write(cg->regmap, GPIO0IRQ, p0);
	289	regmap_write(cg->regmap, GPIO1IRQ, p1);
	290
	291	pending = p0 \| p1 << 8;
	292
fcce88d9 AS	293	for_each_set_bit(gpio, &pending, CRYSTALCOVE_GPIO_NUM) {
	294	virq = irq_find_mapping(cg->chip.irq.domain, gpio);
	295	handle_nested_irq(virq);
104fb1d5 ZL	296	}
	297
	298	return IRQ_HANDLED;
	299	}
	300
68a12c19	301	static void crystalcove_gpio_dbg_show(struct seq_file s, struct gpio_chip chip)
104fb1d5	302	{
435cc3d4	303	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
104fb1d5 ZL	304	int gpio, offset;
	305	unsigned int ctlo, ctli, mirqs0, mirqsx, irq;
	306
dcdc3018	307	for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
104fb1d5 ZL	308	regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
	309	regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
	310	regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
	311	&mirqs0);
	312	regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
	313	&mirqsx);
	314	regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
	315	&irq);
	316
	317	offset = gpio % 8;
	318	seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
	319	gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
	320	ctli & 0x1 ? "hi" : "lo",
	321	ctli & CTLI_INTCNT_NE ? "fall" : " ",
	322	ctli & CTLI_INTCNT_PE ? "rise" : " ",
	323	ctlo,
	324	mirqs0 & BIT(offset) ? "s0 mask " : "s0 unmask",
	325	mirqsx & BIT(offset) ? "sx mask " : "sx unmask",
	326	irq & BIT(offset) ? "pending" : " ");
	327	}
	328	}
	329
	330	static int crystalcove_gpio_probe(struct platform_device *pdev)
	331	{
	332	int irq = platform_get_irq(pdev, 0);
	333	struct crystalcove_gpio *cg;
	334	int retval;
	335	struct device *dev = pdev->dev.parent;
	336	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
945e72db	337	struct gpio_irq_chip *girq;
104fb1d5 ZL	338
	339	if (irq < 0)
	340	return irq;
	341
	342	cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
	343	if (!cg)
	344	return -ENOMEM;
	345
104fb1d5 ZL	346	mutex_init(&cg->buslock);
	347	cg->chip.label = KBUILD_MODNAME;
	348	cg->chip.direction_input = crystalcove_gpio_dir_in;
	349	cg->chip.direction_output = crystalcove_gpio_dir_out;
	350	cg->chip.get = crystalcove_gpio_get;
	351	cg->chip.set = crystalcove_gpio_set;
	352	cg->chip.base = -1;
dcdc3018	353	cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;
104fb1d5	354	cg->chip.can_sleep = true;
58383c78	355	cg->chip.parent = dev;
104fb1d5 ZL	356	cg->chip.dbg_show = crystalcove_gpio_dbg_show;
	357	cg->regmap = pmic->regmap;
	358
945e72db	359	girq = &cg->chip.irq;
386cbe7f	360	gpio_irq_chip_set_chip(girq, &crystalcove_irqchip);
945e72db LW	361	/* This will let us handle the parent IRQ in the driver */
	362	girq->parent_handler = NULL;
	363	girq->num_parents = 0;
	364	girq->parents = NULL;
	365	girq->default_type = IRQ_TYPE_NONE;
	366	girq->handler = handle_simple_irq;
	367	girq->threaded = true;
104fb1d5	368
a1cdaa64 AS	369	retval = devm_request_threaded_irq(&pdev->dev, irq, NULL,
	370	crystalcove_gpio_irq_handler,
	371	IRQF_ONESHOT, KBUILD_MODNAME, cg);
104fb1d5 ZL	372	if (retval) {
104fb1d5 ZL	373	dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
828e47e4	374	return retval;
104fb1d5 ZL	375	}
104fb1d5 ZL	376
06608bc2 HG	377	retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg);
	378	if (retval)
	379	return retval;
	380
	381	/* Distuingish IRQ domain from others sharing (MFD) the same fwnode */
	382	irq_domain_update_bus_token(cg->chip.irq.domain, DOMAIN_BUS_WIRED);
	383
	384	return 0;
104fb1d5 ZL	385	}
104fb1d5 ZL	386
104fb1d5 ZL	387	static struct platform_driver crystalcove_gpio_driver = {
104fb1d5 ZL	388	.probe = crystalcove_gpio_probe,
104fb1d5 ZL	389	.driver = {
104fb1d5 ZL	390	.name = "crystal_cove_gpio",
104fb1d5 ZL	391	},
104fb1d5 ZL	392	};
104fb1d5 ZL	393	module_platform_driver(crystalcove_gpio_driver);
	394
	395	MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
	396	MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
	397	MODULE_LICENSE("GPL v2");