[linux-2.6-block.git] / drivers / gpio / gpio-creg-snps.c

// SPDX-License-Identifier: GPL-2.0+
//
// Synopsys CREG (Control REGisters) GPIO driver
//
// Copyright (C) 2018 Synopsys
// Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>

#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_platform.h>

#define MAX_GPIO	32

struct creg_layout {
	u8 ngpio;
	u8 shift[MAX_GPIO];
	u8 on[MAX_GPIO];
	u8 off[MAX_GPIO];
	u8 bit_per_gpio[MAX_GPIO];
};

struct creg_gpio {
	struct gpio_chip gc;
	void __iomem *regs;
	spinlock_t lock;
	const struct creg_layout *layout;
};

static void creg_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
{
	struct creg_gpio *hcg = gpiochip_get_data(gc);
	const struct creg_layout *layout = hcg->layout;
	u32 reg, reg_shift, value;
	unsigned long flags;
	int i;

	value = val ? hcg->layout->on[offset] : hcg->layout->off[offset];

	reg_shift = layout->shift[offset];
	for (i = 0; i < offset; i++)
		reg_shift += layout->bit_per_gpio[i] + layout->shift[i];

	spin_lock_irqsave(&hcg->lock, flags);
	reg = readl(hcg->regs);
	reg &= ~(GENMASK(layout->bit_per_gpio[i] - 1, 0) << reg_shift);
	reg |=  (value << reg_shift);
	writel(reg, hcg->regs);
	spin_unlock_irqrestore(&hcg->lock, flags);
}

static int creg_gpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
{
	creg_gpio_set(gc, offset, val);

	return 0;
}

static int creg_gpio_validate_pg(struct device *dev, struct creg_gpio *hcg,
				 int i)
{
	const struct creg_layout *layout = hcg->layout;

	if (layout->bit_per_gpio[i] < 1 || layout->bit_per_gpio[i] > 8)
		return -EINVAL;

	/* Check that on valiue fits it's placeholder */
	if (GENMASK(31, layout->bit_per_gpio[i]) & layout->on[i])
		return -EINVAL;

	/* Check that off valiue fits it's placeholder */
	if (GENMASK(31, layout->bit_per_gpio[i]) & layout->off[i])
		return -EINVAL;

	if (layout->on[i] == layout->off[i])
		return -EINVAL;

	return 0;
}

static int creg_gpio_validate(struct device *dev, struct creg_gpio *hcg,
			      u32 ngpios)
{
	u32 reg_len = 0;
	int i;

	if (hcg->layout->ngpio < 1 || hcg->layout->ngpio > MAX_GPIO)
		return -EINVAL;

	if (ngpios < 1 || ngpios > hcg->layout->ngpio) {
		dev_err(dev, "ngpios must be in [1:%u]\n", hcg->layout->ngpio);
		return -EINVAL;
	}

	for (i = 0; i < hcg->layout->ngpio; i++) {
		if (creg_gpio_validate_pg(dev, hcg, i))
			return -EINVAL;

		reg_len += hcg->layout->shift[i] + hcg->layout->bit_per_gpio[i];
	}

	/* Check that we fit in 32 bit register */
	if (reg_len > 32)
		return -EINVAL;

	return 0;
}

static const struct creg_layout hsdk_cs_ctl = {
	.ngpio		= 10,
	.shift		= { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
	.off		= { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 },
	.on		= { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 },
	.bit_per_gpio	= { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 }
};

static const struct creg_layout axs10x_flsh_cs_ctl = {
	.ngpio		= 1,
	.shift		= { 0 },
	.off		= { 1 },
	.on		= { 3 },
	.bit_per_gpio	= { 2 }
};

static const struct of_device_id creg_gpio_ids[] = {
	{
		.compatible = "snps,creg-gpio-axs10x",
		.data = &axs10x_flsh_cs_ctl
	}, {
		.compatible = "snps,creg-gpio-hsdk",
		.data = &hsdk_cs_ctl
	}, { /* sentinel */ }
};

static int creg_gpio_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	struct device *dev = &pdev->dev;
	struct creg_gpio *hcg;
	struct resource *mem;
	u32 ngpios;
	int ret;

	hcg = devm_kzalloc(dev, sizeof(struct creg_gpio), GFP_KERNEL);
	if (!hcg)
		return -ENOMEM;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	hcg->regs = devm_ioremap_resource(dev, mem);
	if (IS_ERR(hcg->regs))
		return PTR_ERR(hcg->regs);

	match = of_match_node(creg_gpio_ids, pdev->dev.of_node);
	hcg->layout = match->data;
	if (!hcg->layout)
		return -EINVAL;

	ret = of_property_read_u32(dev->of_node, "ngpios", &ngpios);
	if (ret)
		return ret;

	ret = creg_gpio_validate(dev, hcg, ngpios);
	if (ret)
		return ret;

	spin_lock_init(&hcg->lock);

	hcg->gc.label = dev_name(dev);
	hcg->gc.base = -1;
	hcg->gc.ngpio = ngpios;
	hcg->gc.set = creg_gpio_set;
	hcg->gc.direction_output = creg_gpio_dir_out;
	hcg->gc.of_node = dev->of_node;

	ret = devm_gpiochip_add_data(dev, &hcg->gc, hcg);
	if (ret)
		return ret;

	dev_info(dev, "GPIO controller with %d gpios probed\n", ngpios);

	return 0;
}

static struct platform_driver creg_gpio_snps_driver = {
	.driver = {
		.name = "snps-creg-gpio",
		.of_match_table = creg_gpio_ids,
	},
	.probe  = creg_gpio_probe,
};
builtin_platform_driver(creg_gpio_snps_driver);
Commit	Line	Data
2505c7b0 EP	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// Synopsys CREG (Control REGisters) GPIO driver
	4	//
	5	// Copyright (C) 2018 Synopsys
	6	// Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
	7
	8	#include <linux/gpio/driver.h>
	9	#include <linux/io.h>
	10	#include <linux/of.h>
	11	#include <linux/of_platform.h>
	12
	13	#define MAX_GPIO 32
	14
	15	struct creg_layout {
	16	u8 ngpio;
	17	u8 shift[MAX_GPIO];
	18	u8 on[MAX_GPIO];
	19	u8 off[MAX_GPIO];
	20	u8 bit_per_gpio[MAX_GPIO];
	21	};
	22
	23	struct creg_gpio {
	24	struct gpio_chip gc;
	25	void __iomem *regs;
	26	spinlock_t lock;
	27	const struct creg_layout *layout;
	28	};
	29
	30	static void creg_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
	31	{
	32	struct creg_gpio *hcg = gpiochip_get_data(gc);
	33	const struct creg_layout *layout = hcg->layout;
	34	u32 reg, reg_shift, value;
	35	unsigned long flags;
	36	int i;
	37
	38	value = val ? hcg->layout->on[offset] : hcg->layout->off[offset];
	39
	40	reg_shift = layout->shift[offset];
	41	for (i = 0; i < offset; i++)
	42	reg_shift += layout->bit_per_gpio[i] + layout->shift[i];
	43
	44	spin_lock_irqsave(&hcg->lock, flags);
	45	reg = readl(hcg->regs);
	46	reg &= ~(GENMASK(layout->bit_per_gpio[i] - 1, 0) << reg_shift);
	47	reg \|= (value << reg_shift);
	48	writel(reg, hcg->regs);
	49	spin_unlock_irqrestore(&hcg->lock, flags);
	50	}
	51
	52	static int creg_gpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
	53	{
	54	creg_gpio_set(gc, offset, val);
	55
	56	return 0;
	57	}
	58
	59	static int creg_gpio_validate_pg(struct device dev, struct creg_gpio hcg,
	60	int i)
	61	{
	62	const struct creg_layout *layout = hcg->layout;
	63
	64	if (layout->bit_per_gpio[i] < 1 \|\| layout->bit_per_gpio[i] > 8)
65	return -EINVAL;
66
67	/* Check that on valiue fits it's placeholder */
68	if (GENMASK(31, layout->bit_per_gpio[i]) & layout->on[i])
69	return -EINVAL;
70
71	/* Check that off valiue fits it's placeholder */
72	if (GENMASK(31, layout->bit_per_gpio[i]) & layout->off[i])
73	return -EINVAL;
74
75	if (layout->on[i] == layout->off[i])
76	return -EINVAL;
77
78	return 0;
79	}
80
81	static int creg_gpio_validate(struct device dev, struct creg_gpio hcg,
82	u32 ngpios)
83	{
84	u32 reg_len = 0;
85	int i;
86
87	if (hcg->layout->ngpio < 1 \|\| hcg->layout->ngpio > MAX_GPIO)
88	return -EINVAL;
89
90	if (ngpios < 1 \|\| ngpios > hcg->layout->ngpio) {
91	dev_err(dev, "ngpios must be in [1:%u]\n", hcg->layout->ngpio);
92	return -EINVAL;
93	}
94
95	for (i = 0; i < hcg->layout->ngpio; i++) {
96	if (creg_gpio_validate_pg(dev, hcg, i))
97	return -EINVAL;
98
99	reg_len += hcg->layout->shift[i] + hcg->layout->bit_per_gpio[i];
100	}
101
102	/* Check that we fit in 32 bit register */
103	if (reg_len > 32)
104	return -EINVAL;
105
106	return 0;
107	}
108
109	static const struct creg_layout hsdk_cs_ctl = {
110	.ngpio = 10,
111	.shift = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
112	.off = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 },
113	.on = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 },
114	.bit_per_gpio = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 }
115	};
116
117	static const struct creg_layout axs10x_flsh_cs_ctl = {
118	.ngpio = 1,
119	.shift = { 0 },
120	.off = { 1 },
121	.on = { 3 },
122	.bit_per_gpio = { 2 }
123	};
124
125	static const struct of_device_id creg_gpio_ids[] = {
126	{
127	.compatible = "snps,creg-gpio-axs10x",
128	.data = &axs10x_flsh_cs_ctl
129	}, {
130	.compatible = "snps,creg-gpio-hsdk",
131	.data = &hsdk_cs_ctl
132	}, { /* sentinel */ }
133	};
134
135	static int creg_gpio_probe(struct platform_device *pdev)
136	{
137	const struct of_device_id *match;
138	struct device *dev = &pdev->dev;
139	struct creg_gpio *hcg;
140	struct resource *mem;
141	u32 ngpios;
142	int ret;
143
144	hcg = devm_kzalloc(dev, sizeof(struct creg_gpio), GFP_KERNEL);
145	if (!hcg)
146	return -ENOMEM;
147
148	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
149	hcg->regs = devm_ioremap_resource(dev, mem);
150	if (IS_ERR(hcg->regs))
151	return PTR_ERR(hcg->regs);
152
153	match = of_match_node(creg_gpio_ids, pdev->dev.of_node);
154	hcg->layout = match->data;
155	if (!hcg->layout)
156	return -EINVAL;
157
158	ret = of_property_read_u32(dev->of_node, "ngpios", &ngpios);
159	if (ret)
160	return ret;
161
162	ret = creg_gpio_validate(dev, hcg, ngpios);
163	if (ret)
164	return ret;
165
166	spin_lock_init(&hcg->lock);
167
168	hcg->gc.label = dev_name(dev);
169	hcg->gc.base = -1;
170	hcg->gc.ngpio = ngpios;
171	hcg->gc.set = creg_gpio_set;
172	hcg->gc.direction_output = creg_gpio_dir_out;
173	hcg->gc.of_node = dev->of_node;
174
175	ret = devm_gpiochip_add_data(dev, &hcg->gc, hcg);
176	if (ret)
177	return ret;
178
179	dev_info(dev, "GPIO controller with %d gpios probed\n", ngpios);
180
181	return 0;
182	}
183
184	static struct platform_driver creg_gpio_snps_driver = {
185	.driver = {
186	.name = "snps-creg-gpio",
187	.of_match_table = creg_gpio_ids,
188	},
189	.probe = creg_gpio_probe,
190	};
191	builtin_platform_driver(creg_gpio_snps_driver);