[linux-block.git] / drivers / gpio / gpio-ath79.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 *  Atheros AR71XX/AR724X/AR913X GPIO API support
 *
 *  Copyright (C) 2015 Alban Bedel <albeu@free.fr>
 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
 *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 */

#include <linux/gpio/driver.h>
#include <linux/platform_data/gpio-ath79.h>
#include <linux/of_device.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/irq.h>

#define AR71XX_GPIO_REG_OE		0x00
#define AR71XX_GPIO_REG_IN		0x04
#define AR71XX_GPIO_REG_SET		0x0c
#define AR71XX_GPIO_REG_CLEAR		0x10

#define AR71XX_GPIO_REG_INT_ENABLE	0x14
#define AR71XX_GPIO_REG_INT_TYPE	0x18
#define AR71XX_GPIO_REG_INT_POLARITY	0x1c
#define AR71XX_GPIO_REG_INT_PENDING	0x20
#define AR71XX_GPIO_REG_INT_MASK	0x24

struct ath79_gpio_ctrl {
	struct gpio_chip gc;
	void __iomem *base;
	raw_spinlock_t lock;
	unsigned long both_edges;
};

static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *data)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);

	return container_of(gc, struct ath79_gpio_ctrl, gc);
}

static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg)
{
	return readl(ctrl->base + reg);
}

static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl,
			unsigned reg, u32 val)
{
	writel(val, ctrl->base + reg);
}

static bool ath79_gpio_update_bits(
	struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits)
{
	u32 old_val, new_val;

	old_val = ath79_gpio_read(ctrl, reg);
	new_val = (old_val & ~mask) | (bits & mask);

	if (new_val != old_val)
		ath79_gpio_write(ctrl, reg, new_val);

	return new_val != old_val;
}

static void ath79_gpio_irq_unmask(struct irq_data *data)
{
	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	u32 mask = BIT(irqd_to_hwirq(data));
	unsigned long flags;

	gpiochip_enable_irq(&ctrl->gc, irqd_to_hwirq(data));
	raw_spin_lock_irqsave(&ctrl->lock, flags);
	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
}

static void ath79_gpio_irq_mask(struct irq_data *data)
{
	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	u32 mask = BIT(irqd_to_hwirq(data));
	unsigned long flags;

	raw_spin_lock_irqsave(&ctrl->lock, flags);
	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
	gpiochip_disable_irq(&ctrl->gc, irqd_to_hwirq(data));
}

static void ath79_gpio_irq_enable(struct irq_data *data)
{
	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	u32 mask = BIT(irqd_to_hwirq(data));
	unsigned long flags;

	raw_spin_lock_irqsave(&ctrl->lock, flags);
	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
}

static void ath79_gpio_irq_disable(struct irq_data *data)
{
	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	u32 mask = BIT(irqd_to_hwirq(data));
	unsigned long flags;

	raw_spin_lock_irqsave(&ctrl->lock, flags);
	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
}

static int ath79_gpio_irq_set_type(struct irq_data *data,
				unsigned int flow_type)
{
	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	u32 mask = BIT(irqd_to_hwirq(data));
	u32 type = 0, polarity = 0;
	unsigned long flags;
	bool disabled;

	switch (flow_type) {
	case IRQ_TYPE_EDGE_RISING:
		polarity |= mask;
		fallthrough;
	case IRQ_TYPE_EDGE_FALLING:
	case IRQ_TYPE_EDGE_BOTH:
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		polarity |= mask;
		fallthrough;
	case IRQ_TYPE_LEVEL_LOW:
		type |= mask;
		break;

	default:
		return -EINVAL;
	}

	raw_spin_lock_irqsave(&ctrl->lock, flags);

	if (flow_type == IRQ_TYPE_EDGE_BOTH) {
		ctrl->both_edges |= mask;
		polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
	} else {
		ctrl->both_edges &= ~mask;
	}

	/* As the IRQ configuration can't be loaded atomically we
	 * have to disable the interrupt while the configuration state
	 * is invalid.
	 */
	disabled = ath79_gpio_update_bits(
		ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);

	ath79_gpio_update_bits(
		ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type);
	ath79_gpio_update_bits(
		ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity);

	if (disabled)
		ath79_gpio_update_bits(
			ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);

	raw_spin_unlock_irqrestore(&ctrl->lock, flags);

	return 0;
}

static const struct irq_chip ath79_gpio_irqchip = {
	.name = "gpio-ath79",
	.irq_enable = ath79_gpio_irq_enable,
	.irq_disable = ath79_gpio_irq_disable,
	.irq_mask = ath79_gpio_irq_mask,
	.irq_unmask = ath79_gpio_irq_unmask,
	.irq_set_type = ath79_gpio_irq_set_type,
	.flags = IRQCHIP_IMMUTABLE,
	GPIOCHIP_IRQ_RESOURCE_HELPERS,
};

static void ath79_gpio_irq_handler(struct irq_desc *desc)
{
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	struct irq_chip *irqchip = irq_desc_get_chip(desc);
	struct ath79_gpio_ctrl *ctrl =
		container_of(gc, struct ath79_gpio_ctrl, gc);
	unsigned long flags, pending;
	u32 both_edges, state;
	int irq;

	chained_irq_enter(irqchip, desc);

	raw_spin_lock_irqsave(&ctrl->lock, flags);

	pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);

	/* Update the polarity of the both edges irqs */
	both_edges = ctrl->both_edges & pending;
	if (both_edges) {
		state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
		ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,
				both_edges, ~state);
	}

	raw_spin_unlock_irqrestore(&ctrl->lock, flags);

	for_each_set_bit(irq, &pending, gc->ngpio)
		generic_handle_domain_irq(gc->irq.domain, irq);

	chained_irq_exit(irqchip, desc);
}

static const struct of_device_id ath79_gpio_of_match[] = {
	{ .compatible = "qca,ar7100-gpio" },
	{ .compatible = "qca,ar9340-gpio" },
	{},
};
MODULE_DEVICE_TABLE(of, ath79_gpio_of_match);

static int ath79_gpio_probe(struct platform_device *pdev)
{
	struct ath79_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct ath79_gpio_ctrl *ctrl;
	struct gpio_irq_chip *girq;
	u32 ath79_gpio_count;
	bool oe_inverted;
	int err;

	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
	if (!ctrl)
		return -ENOMEM;

	if (np) {
		err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
		if (err) {
			dev_err(dev, "ngpios property is not valid\n");
			return err;
		}
		oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
	} else if (pdata) {
		ath79_gpio_count = pdata->ngpios;
		oe_inverted = pdata->oe_inverted;
	} else {
		dev_err(dev, "No DT node or platform data found\n");
		return -EINVAL;
	}

	if (ath79_gpio_count >= 32) {
		dev_err(dev, "ngpios must be less than 32\n");
		return -EINVAL;
	}

	ctrl->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(ctrl->base))
		return PTR_ERR(ctrl->base);

	raw_spin_lock_init(&ctrl->lock);
	err = bgpio_init(&ctrl->gc, dev, 4,
			ctrl->base + AR71XX_GPIO_REG_IN,
			ctrl->base + AR71XX_GPIO_REG_SET,
			ctrl->base + AR71XX_GPIO_REG_CLEAR,
			oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE,
			oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL,
			0);
	if (err) {
		dev_err(dev, "bgpio_init failed\n");
		return err;
	}
	/* Use base 0 to stay compatible with legacy platforms */
	ctrl->gc.base = 0;

	/* Optional interrupt setup */
	if (!np || of_property_read_bool(np, "interrupt-controller")) {
		girq = &ctrl->gc.irq;
		gpio_irq_chip_set_chip(girq, &ath79_gpio_irqchip);
		girq->parent_handler = ath79_gpio_irq_handler;
		girq->num_parents = 1;
		girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
					     GFP_KERNEL);
		if (!girq->parents)
			return -ENOMEM;
		girq->parents[0] = platform_get_irq(pdev, 0);
		girq->default_type = IRQ_TYPE_NONE;
		girq->handler = handle_simple_irq;
	}

	return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
}

static struct platform_driver ath79_gpio_driver = {
	.driver = {
		.name = "ath79-gpio",
		.of_match_table	= ath79_gpio_of_match,
	},
	.probe = ath79_gpio_probe,
};

module_platform_driver(ath79_gpio_driver);

MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
6eae43c5 GJ	2	/*
	3	* Atheros AR71XX/AR724X/AR913X GPIO API support
	4	*
28be55df	5	* Copyright (C) 2015 Alban Bedel <albeu@free.fr>
5b5b544e GJ	6	* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5b5b544e GJ	7	* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
6eae43c5	8	* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6eae43c5 GJ	9	*/
6eae43c5 GJ	10
49a5bd88	11	#include <linux/gpio/driver.h>
2ddf3a79 AB	12	#include <linux/platform_data/gpio-ath79.h>
2ddf3a79 AB	13	#include <linux/of_device.h>
2b8f89e1	14	#include <linux/interrupt.h>
2034b9dc	15	#include <linux/module.h>
2b8f89e1	16	#include <linux/irq.h>
6eae43c5	17
409d8783 AB	18	#define AR71XX_GPIO_REG_OE 0x00
	19	#define AR71XX_GPIO_REG_IN 0x04
	20	#define AR71XX_GPIO_REG_SET 0x0c
	21	#define AR71XX_GPIO_REG_CLEAR 0x10
6eae43c5	22
2b8f89e1 AB	23	#define AR71XX_GPIO_REG_INT_ENABLE 0x14
	24	#define AR71XX_GPIO_REG_INT_TYPE 0x18
	25	#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
	26	#define AR71XX_GPIO_REG_INT_PENDING 0x20
	27	#define AR71XX_GPIO_REG_INT_MASK 0x24
	28
49a5bd88	29	struct ath79_gpio_ctrl {
ab32770e	30	struct gpio_chip gc;
49a5bd88	31	void __iomem *base;
a080ce53	32	raw_spinlock_t lock;
2b8f89e1 AB	33	unsigned long both_edges;
	34	};
	35
	36	static struct ath79_gpio_ctrl irq_data_to_ath79_gpio(struct irq_data data)
	37	{
	38	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
	39
	40	return container_of(gc, struct ath79_gpio_ctrl, gc);
	41	}
	42
	43	static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg)
	44	{
	45	return readl(ctrl->base + reg);
	46	}
	47
	48	static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl,
	49	unsigned reg, u32 val)
	50	{
23211b08	51	writel(val, ctrl->base + reg);
2b8f89e1 AB	52	}
	53
	54	static bool ath79_gpio_update_bits(
	55	struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits)
	56	{
	57	u32 old_val, new_val;
	58
	59	old_val = ath79_gpio_read(ctrl, reg);
	60	new_val = (old_val & ~mask) \| (bits & mask);
	61
	62	if (new_val != old_val)
	63	ath79_gpio_write(ctrl, reg, new_val);
	64
	65	return new_val != old_val;
	66	}
	67
	68	static void ath79_gpio_irq_unmask(struct irq_data *data)
	69	{
	70	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	71	u32 mask = BIT(irqd_to_hwirq(data));
	72	unsigned long flags;
	73
b11ce7e4	74	gpiochip_enable_irq(&ctrl->gc, irqd_to_hwirq(data));
a080ce53	75	raw_spin_lock_irqsave(&ctrl->lock, flags);
2b8f89e1	76	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
a080ce53	77	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
2b8f89e1 AB	78	}
	79
	80	static void ath79_gpio_irq_mask(struct irq_data *data)
	81	{
	82	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	83	u32 mask = BIT(irqd_to_hwirq(data));
	84	unsigned long flags;
	85
a080ce53	86	raw_spin_lock_irqsave(&ctrl->lock, flags);
2b8f89e1	87	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
a080ce53	88	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
b11ce7e4	89	gpiochip_disable_irq(&ctrl->gc, irqd_to_hwirq(data));
2b8f89e1 AB	90	}
	91
	92	static void ath79_gpio_irq_enable(struct irq_data *data)
	93	{
	94	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	95	u32 mask = BIT(irqd_to_hwirq(data));
	96	unsigned long flags;
	97
a080ce53	98	raw_spin_lock_irqsave(&ctrl->lock, flags);
2b8f89e1 AB	99	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
2b8f89e1 AB	100	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
a080ce53	101	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
2b8f89e1 AB	102	}
	103
	104	static void ath79_gpio_irq_disable(struct irq_data *data)
	105	{
	106	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	107	u32 mask = BIT(irqd_to_hwirq(data));
	108	unsigned long flags;
	109
a080ce53	110	raw_spin_lock_irqsave(&ctrl->lock, flags);
2b8f89e1 AB	111	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
2b8f89e1 AB	112	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
a080ce53	113	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
2b8f89e1 AB	114	}
	115
	116	static int ath79_gpio_irq_set_type(struct irq_data *data,
	117	unsigned int flow_type)
	118	{
	119	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	120	u32 mask = BIT(irqd_to_hwirq(data));
	121	u32 type = 0, polarity = 0;
	122	unsigned long flags;
	123	bool disabled;
	124
	125	switch (flow_type) {
	126	case IRQ_TYPE_EDGE_RISING:
	127	polarity \|= mask;
d49ee562	128	fallthrough;
2b8f89e1 AB	129	case IRQ_TYPE_EDGE_FALLING:
	130	case IRQ_TYPE_EDGE_BOTH:
	131	break;
	132
	133	case IRQ_TYPE_LEVEL_HIGH:
	134	polarity \|= mask;
df561f66	135	fallthrough;
2b8f89e1 AB	136	case IRQ_TYPE_LEVEL_LOW:
	137	type \|= mask;
	138	break;
	139
	140	default:
	141	return -EINVAL;
	142	}
	143
a080ce53	144	raw_spin_lock_irqsave(&ctrl->lock, flags);
2b8f89e1 AB	145
	146	if (flow_type == IRQ_TYPE_EDGE_BOTH) {
	147	ctrl->both_edges \|= mask;
	148	polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
	149	} else {
	150	ctrl->both_edges &= ~mask;
	151	}
	152
	153	/* As the IRQ configuration can't be loaded atomically we
	154	* have to disable the interrupt while the configuration state
	155	* is invalid.
	156	*/
	157	disabled = ath79_gpio_update_bits(
	158	ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
	159
	160	ath79_gpio_update_bits(
	161	ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type);
	162	ath79_gpio_update_bits(
	163	ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity);
	164
	165	if (disabled)
	166	ath79_gpio_update_bits(
	167	ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
	168
a080ce53	169	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
2b8f89e1 AB	170
	171	return 0;
	172	}
	173
b11ce7e4	174	static const struct irq_chip ath79_gpio_irqchip = {
2b8f89e1 AB	175	.name = "gpio-ath79",
	176	.irq_enable = ath79_gpio_irq_enable,
	177	.irq_disable = ath79_gpio_irq_disable,
	178	.irq_mask = ath79_gpio_irq_mask,
	179	.irq_unmask = ath79_gpio_irq_unmask,
	180	.irq_set_type = ath79_gpio_irq_set_type,
b11ce7e4 LW	181	.flags = IRQCHIP_IMMUTABLE,
b11ce7e4 LW	182	GPIOCHIP_IRQ_RESOURCE_HELPERS,
49a5bd88 AB	183	};
49a5bd88 AB	184
2b8f89e1 AB	185	static void ath79_gpio_irq_handler(struct irq_desc *desc)
	186	{
	187	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	188	struct irq_chip *irqchip = irq_desc_get_chip(desc);
	189	struct ath79_gpio_ctrl *ctrl =
	190	container_of(gc, struct ath79_gpio_ctrl, gc);
	191	unsigned long flags, pending;
	192	u32 both_edges, state;
	193	int irq;
	194
	195	chained_irq_enter(irqchip, desc);
	196
a080ce53	197	raw_spin_lock_irqsave(&ctrl->lock, flags);
2b8f89e1 AB	198
	199	pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);
	200
	201	/* Update the polarity of the both edges irqs */
	202	both_edges = ctrl->both_edges & pending;
	203	if (both_edges) {
	204	state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
	205	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,
	206	both_edges, ~state);
	207	}
	208
a080ce53	209	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
2b8f89e1	210
dbd1c54f MZ	211	for_each_set_bit(irq, &pending, gc->ngpio)
dbd1c54f MZ	212	generic_handle_domain_irq(gc->irq.domain, irq);
2b8f89e1 AB	213
	214	chained_irq_exit(irqchip, desc);
	215	}
	216
2ddf3a79 AB	217	static const struct of_device_id ath79_gpio_of_match[] = {
	218	{ .compatible = "qca,ar7100-gpio" },
	219	{ .compatible = "qca,ar9340-gpio" },
	220	{},
	221	};
6d8d271e	222	MODULE_DEVICE_TABLE(of, ath79_gpio_of_match);
2ddf3a79 AB	223
2ddf3a79 AB	224	static int ath79_gpio_probe(struct platform_device *pdev)
6eae43c5	225	{
ab128afc	226	struct ath79_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
aee5cec5 LW	227	struct device *dev = &pdev->dev;
aee5cec5 LW	228	struct device_node *np = dev->of_node;
49a5bd88	229	struct ath79_gpio_ctrl *ctrl;
aee5cec5	230	struct gpio_irq_chip *girq;
49a5bd88	231	u32 ath79_gpio_count;
2ddf3a79	232	bool oe_inverted;
6eae43c5 GJ	233	int err;
6eae43c5 GJ	234
aee5cec5	235	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
49a5bd88 AB	236	if (!ctrl)
	237	return -ENOMEM;
	238
2ddf3a79 AB	239	if (np) {
	240	err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
	241	if (err) {
aee5cec5	242	dev_err(dev, "ngpios property is not valid\n");
2ddf3a79 AB	243	return err;
2ddf3a79 AB	244	}
2ddf3a79 AB	245	oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
	246	} else if (pdata) {
	247	ath79_gpio_count = pdata->ngpios;
	248	oe_inverted = pdata->oe_inverted;
	249	} else {
aee5cec5	250	dev_err(dev, "No DT node or platform data found\n");
2ddf3a79 AB	251	return -EINVAL;
	252	}
	253
f0d3c72c	254	if (ath79_gpio_count >= 32) {
aee5cec5	255	dev_err(dev, "ngpios must be less than 32\n");
f0d3c72c AL	256	return -EINVAL;
	257	}
	258
71b4da2b BG	259	ctrl->base = devm_platform_ioremap_resource(pdev, 0);
	260	if (IS_ERR(ctrl->base))
	261	return PTR_ERR(ctrl->base);
6eae43c5	262
a080ce53	263	raw_spin_lock_init(&ctrl->lock);
aee5cec5	264	err = bgpio_init(&ctrl->gc, dev, 4,
ab32770e AB	265	ctrl->base + AR71XX_GPIO_REG_IN,
	266	ctrl->base + AR71XX_GPIO_REG_SET,
	267	ctrl->base + AR71XX_GPIO_REG_CLEAR,
	268	oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE,
	269	oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL,
	270	0);
	271	if (err) {
aee5cec5	272	dev_err(dev, "bgpio_init failed\n");
ab32770e	273	return err;
5b5b544e	274	}
ab32770e AB	275	/* Use base 0 to stay compatible with legacy platforms */
ab32770e AB	276	ctrl->gc.base = 0;
6eae43c5	277
aee5cec5 LW	278	/* Optional interrupt setup */
	279	if (!np \|\| of_property_read_bool(np, "interrupt-controller")) {
	280	girq = &ctrl->gc.irq;
b11ce7e4	281	gpio_irq_chip_set_chip(girq, &ath79_gpio_irqchip);
aee5cec5 LW	282	girq->parent_handler = ath79_gpio_irq_handler;
	283	girq->num_parents = 1;
	284	girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
	285	GFP_KERNEL);
	286	if (!girq->parents)
	287	return -ENOMEM;
	288	girq->parents[0] = platform_get_irq(pdev, 0);
	289	girq->default_type = IRQ_TYPE_NONE;
	290	girq->handler = handle_simple_irq;
2ddf3a79 AB	291	}
2ddf3a79 AB	292
cd440753	293	return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
2f890cf0 AB	294	}
2f890cf0 AB	295
2ddf3a79 AB	296	static struct platform_driver ath79_gpio_driver = {
	297	.driver = {
	298	.name = "ath79-gpio",
	299	.of_match_table = ath79_gpio_of_match,
	300	},
	301	.probe = ath79_gpio_probe,
	302	};
	303
	304	module_platform_driver(ath79_gpio_driver);
539340f3 JC	305
	306	MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");
	307	MODULE_LICENSE("GPL v2");