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361b7911 JS |
1 | /* |
2 | * Copyright 2015 IBM Corp. | |
3 | * | |
4 | * Joel Stanley <joel@jms.id.au> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
5ae4cb94 AJ |
12 | #include <asm/div64.h> |
13 | #include <linux/clk.h> | |
14 | #include <linux/gpio/driver.h> | |
15 | #include <linux/hashtable.h> | |
361b7911 JS |
16 | #include <linux/init.h> |
17 | #include <linux/io.h> | |
5ae4cb94 AJ |
18 | #include <linux/kernel.h> |
19 | #include <linux/module.h> | |
361b7911 | 20 | #include <linux/pinctrl/consumer.h> |
5ae4cb94 AJ |
21 | #include <linux/platform_device.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/string.h> | |
361b7911 | 24 | |
1736f75d AJ |
25 | struct aspeed_bank_props { |
26 | unsigned int bank; | |
27 | u32 input; | |
28 | u32 output; | |
29 | }; | |
30 | ||
31 | struct aspeed_gpio_config { | |
32 | unsigned int nr_gpios; | |
33 | const struct aspeed_bank_props *props; | |
34 | }; | |
35 | ||
5ae4cb94 AJ |
36 | /* |
37 | * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled | |
38 | * @timer_users: Tracks the number of users for each timer | |
39 | * | |
40 | * The @timer_users has four elements but the first element is unused. This is | |
41 | * to simplify accounting and indexing, as a zero value in @offset_timer | |
42 | * represents disabled debouncing for the GPIO. Any other value for an element | |
43 | * of @offset_timer is used as an index into @timer_users. This behaviour of | |
44 | * the zero value aligns with the behaviour of zero built from the timer | |
45 | * configuration registers (i.e. debouncing is disabled). | |
46 | */ | |
361b7911 JS |
47 | struct aspeed_gpio { |
48 | struct gpio_chip chip; | |
49 | spinlock_t lock; | |
50 | void __iomem *base; | |
51 | int irq; | |
1736f75d | 52 | const struct aspeed_gpio_config *config; |
5ae4cb94 AJ |
53 | |
54 | u8 *offset_timer; | |
55 | unsigned int timer_users[4]; | |
56 | struct clk *clk; | |
361b7911 JS |
57 | }; |
58 | ||
59 | struct aspeed_gpio_bank { | |
60 | uint16_t val_regs; | |
61 | uint16_t irq_regs; | |
5ae4cb94 | 62 | uint16_t debounce_regs; |
1b43d269 | 63 | uint16_t tolerance_regs; |
7153f8ef | 64 | const char names[4][3]; |
361b7911 JS |
65 | }; |
66 | ||
5ae4cb94 AJ |
67 | static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 }; |
68 | ||
361b7911 JS |
69 | static const struct aspeed_gpio_bank aspeed_gpio_banks[] = { |
70 | { | |
71 | .val_regs = 0x0000, | |
72 | .irq_regs = 0x0008, | |
5ae4cb94 | 73 | .debounce_regs = 0x0040, |
1b43d269 | 74 | .tolerance_regs = 0x001c, |
7153f8ef | 75 | .names = { "A", "B", "C", "D" }, |
361b7911 JS |
76 | }, |
77 | { | |
78 | .val_regs = 0x0020, | |
79 | .irq_regs = 0x0028, | |
5ae4cb94 | 80 | .debounce_regs = 0x0048, |
1b43d269 | 81 | .tolerance_regs = 0x003c, |
7153f8ef | 82 | .names = { "E", "F", "G", "H" }, |
361b7911 JS |
83 | }, |
84 | { | |
85 | .val_regs = 0x0070, | |
86 | .irq_regs = 0x0098, | |
5ae4cb94 | 87 | .debounce_regs = 0x00b0, |
1b43d269 | 88 | .tolerance_regs = 0x00ac, |
7153f8ef | 89 | .names = { "I", "J", "K", "L" }, |
361b7911 JS |
90 | }, |
91 | { | |
92 | .val_regs = 0x0078, | |
93 | .irq_regs = 0x00e8, | |
5ae4cb94 | 94 | .debounce_regs = 0x0100, |
1b43d269 | 95 | .tolerance_regs = 0x00fc, |
7153f8ef | 96 | .names = { "M", "N", "O", "P" }, |
361b7911 JS |
97 | }, |
98 | { | |
99 | .val_regs = 0x0080, | |
100 | .irq_regs = 0x0118, | |
5ae4cb94 | 101 | .debounce_regs = 0x0130, |
1b43d269 | 102 | .tolerance_regs = 0x012c, |
7153f8ef | 103 | .names = { "Q", "R", "S", "T" }, |
361b7911 JS |
104 | }, |
105 | { | |
106 | .val_regs = 0x0088, | |
107 | .irq_regs = 0x0148, | |
5ae4cb94 | 108 | .debounce_regs = 0x0160, |
1b43d269 | 109 | .tolerance_regs = 0x015c, |
7153f8ef | 110 | .names = { "U", "V", "W", "X" }, |
361b7911 | 111 | }, |
1736f75d AJ |
112 | { |
113 | .val_regs = 0x01E0, | |
114 | .irq_regs = 0x0178, | |
5ae4cb94 | 115 | .debounce_regs = 0x0190, |
1b43d269 | 116 | .tolerance_regs = 0x018c, |
1736f75d AJ |
117 | .names = { "Y", "Z", "AA", "AB" }, |
118 | }, | |
119 | { | |
1b43d269 AJ |
120 | .val_regs = 0x01e8, |
121 | .irq_regs = 0x01a8, | |
5ae4cb94 | 122 | .debounce_regs = 0x01c0, |
1b43d269 | 123 | .tolerance_regs = 0x01bc, |
1736f75d AJ |
124 | .names = { "AC", "", "", "" }, |
125 | }, | |
361b7911 JS |
126 | }; |
127 | ||
128 | #define GPIO_BANK(x) ((x) >> 5) | |
129 | #define GPIO_OFFSET(x) ((x) & 0x1f) | |
130 | #define GPIO_BIT(x) BIT(GPIO_OFFSET(x)) | |
131 | ||
132 | #define GPIO_DATA 0x00 | |
133 | #define GPIO_DIR 0x04 | |
134 | ||
135 | #define GPIO_IRQ_ENABLE 0x00 | |
136 | #define GPIO_IRQ_TYPE0 0x04 | |
137 | #define GPIO_IRQ_TYPE1 0x08 | |
138 | #define GPIO_IRQ_TYPE2 0x0c | |
139 | #define GPIO_IRQ_STATUS 0x10 | |
140 | ||
5ae4cb94 AJ |
141 | #define GPIO_DEBOUNCE_SEL1 0x00 |
142 | #define GPIO_DEBOUNCE_SEL2 0x04 | |
143 | ||
144 | #define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o)) | |
145 | #define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1) | |
146 | #define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0) | |
147 | ||
361b7911 JS |
148 | static const struct aspeed_gpio_bank *to_bank(unsigned int offset) |
149 | { | |
150 | unsigned int bank = GPIO_BANK(offset); | |
151 | ||
fe13862c | 152 | WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks)); |
361b7911 JS |
153 | return &aspeed_gpio_banks[bank]; |
154 | } | |
155 | ||
1736f75d AJ |
156 | static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props) |
157 | { | |
158 | return !(props->input || props->output); | |
159 | } | |
160 | ||
161 | static inline const struct aspeed_bank_props *find_bank_props( | |
162 | struct aspeed_gpio *gpio, unsigned int offset) | |
163 | { | |
164 | const struct aspeed_bank_props *props = gpio->config->props; | |
165 | ||
166 | while (!is_bank_props_sentinel(props)) { | |
167 | if (props->bank == GPIO_BANK(offset)) | |
168 | return props; | |
169 | props++; | |
170 | } | |
171 | ||
172 | return NULL; | |
173 | } | |
174 | ||
175 | static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) | |
176 | { | |
177 | const struct aspeed_bank_props *props = find_bank_props(gpio, offset); | |
178 | const struct aspeed_gpio_bank *bank = to_bank(offset); | |
179 | unsigned int group = GPIO_OFFSET(offset) / 8; | |
180 | ||
181 | return bank->names[group][0] != '\0' && | |
182 | (!props || ((props->input | props->output) & GPIO_BIT(offset))); | |
183 | } | |
184 | ||
185 | static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) | |
186 | { | |
187 | const struct aspeed_bank_props *props = find_bank_props(gpio, offset); | |
188 | ||
189 | return !props || (props->input & GPIO_BIT(offset)); | |
190 | } | |
191 | ||
192 | #define have_irq(g, o) have_input((g), (o)) | |
5ae4cb94 | 193 | #define have_debounce(g, o) have_input((g), (o)) |
1736f75d AJ |
194 | |
195 | static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset) | |
196 | { | |
197 | const struct aspeed_bank_props *props = find_bank_props(gpio, offset); | |
198 | ||
199 | return !props || (props->output & GPIO_BIT(offset)); | |
200 | } | |
201 | ||
361b7911 JS |
202 | static void __iomem *bank_val_reg(struct aspeed_gpio *gpio, |
203 | const struct aspeed_gpio_bank *bank, | |
204 | unsigned int reg) | |
205 | { | |
206 | return gpio->base + bank->val_regs + reg; | |
207 | } | |
208 | ||
209 | static void __iomem *bank_irq_reg(struct aspeed_gpio *gpio, | |
210 | const struct aspeed_gpio_bank *bank, | |
211 | unsigned int reg) | |
212 | { | |
213 | return gpio->base + bank->irq_regs + reg; | |
214 | } | |
215 | ||
216 | static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset) | |
217 | { | |
218 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); | |
219 | const struct aspeed_gpio_bank *bank = to_bank(offset); | |
220 | ||
221 | return !!(ioread32(bank_val_reg(gpio, bank, GPIO_DATA)) | |
222 | & GPIO_BIT(offset)); | |
223 | } | |
224 | ||
225 | static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, | |
226 | int val) | |
227 | { | |
228 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); | |
229 | const struct aspeed_gpio_bank *bank = to_bank(offset); | |
230 | void __iomem *addr; | |
231 | u32 reg; | |
232 | ||
233 | addr = bank_val_reg(gpio, bank, GPIO_DATA); | |
234 | reg = ioread32(addr); | |
235 | ||
236 | if (val) | |
237 | reg |= GPIO_BIT(offset); | |
238 | else | |
239 | reg &= ~GPIO_BIT(offset); | |
240 | ||
241 | iowrite32(reg, addr); | |
242 | } | |
243 | ||
244 | static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, | |
245 | int val) | |
246 | { | |
247 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); | |
248 | unsigned long flags; | |
249 | ||
250 | spin_lock_irqsave(&gpio->lock, flags); | |
251 | ||
252 | __aspeed_gpio_set(gc, offset, val); | |
253 | ||
254 | spin_unlock_irqrestore(&gpio->lock, flags); | |
255 | } | |
256 | ||
257 | static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) | |
258 | { | |
259 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); | |
260 | const struct aspeed_gpio_bank *bank = to_bank(offset); | |
261 | unsigned long flags; | |
262 | u32 reg; | |
263 | ||
1736f75d AJ |
264 | if (!have_input(gpio, offset)) |
265 | return -ENOTSUPP; | |
266 | ||
361b7911 JS |
267 | spin_lock_irqsave(&gpio->lock, flags); |
268 | ||
269 | reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR)); | |
270 | iowrite32(reg & ~GPIO_BIT(offset), bank_val_reg(gpio, bank, GPIO_DIR)); | |
271 | ||
272 | spin_unlock_irqrestore(&gpio->lock, flags); | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
277 | static int aspeed_gpio_dir_out(struct gpio_chip *gc, | |
278 | unsigned int offset, int val) | |
279 | { | |
280 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); | |
281 | const struct aspeed_gpio_bank *bank = to_bank(offset); | |
282 | unsigned long flags; | |
283 | u32 reg; | |
284 | ||
1736f75d AJ |
285 | if (!have_output(gpio, offset)) |
286 | return -ENOTSUPP; | |
287 | ||
361b7911 JS |
288 | spin_lock_irqsave(&gpio->lock, flags); |
289 | ||
290 | reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR)); | |
291 | iowrite32(reg | GPIO_BIT(offset), bank_val_reg(gpio, bank, GPIO_DIR)); | |
292 | ||
293 | __aspeed_gpio_set(gc, offset, val); | |
294 | ||
295 | spin_unlock_irqrestore(&gpio->lock, flags); | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
300 | static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) | |
301 | { | |
302 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); | |
303 | const struct aspeed_gpio_bank *bank = to_bank(offset); | |
304 | unsigned long flags; | |
305 | u32 val; | |
306 | ||
1736f75d | 307 | if (!have_input(gpio, offset)) |
619e96f4 | 308 | return 0; |
1736f75d AJ |
309 | |
310 | if (!have_output(gpio, offset)) | |
619e96f4 | 311 | return 1; |
1736f75d | 312 | |
361b7911 JS |
313 | spin_lock_irqsave(&gpio->lock, flags); |
314 | ||
315 | val = ioread32(bank_val_reg(gpio, bank, GPIO_DIR)) & GPIO_BIT(offset); | |
316 | ||
317 | spin_unlock_irqrestore(&gpio->lock, flags); | |
318 | ||
319 | return !val; | |
320 | ||
321 | } | |
322 | ||
323 | static inline int irqd_to_aspeed_gpio_data(struct irq_data *d, | |
324 | struct aspeed_gpio **gpio, | |
325 | const struct aspeed_gpio_bank **bank, | |
326 | u32 *bit) | |
327 | { | |
328 | int offset; | |
1736f75d | 329 | struct aspeed_gpio *internal; |
361b7911 JS |
330 | |
331 | offset = irqd_to_hwirq(d); | |
332 | ||
1736f75d AJ |
333 | internal = irq_data_get_irq_chip_data(d); |
334 | ||
335 | /* This might be a bit of a questionable place to check */ | |
336 | if (!have_irq(internal, offset)) | |
337 | return -ENOTSUPP; | |
338 | ||
339 | *gpio = internal; | |
361b7911 JS |
340 | *bank = to_bank(offset); |
341 | *bit = GPIO_BIT(offset); | |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
346 | static void aspeed_gpio_irq_ack(struct irq_data *d) | |
347 | { | |
348 | const struct aspeed_gpio_bank *bank; | |
349 | struct aspeed_gpio *gpio; | |
350 | unsigned long flags; | |
351 | void __iomem *status_addr; | |
352 | u32 bit; | |
353 | int rc; | |
354 | ||
355 | rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit); | |
356 | if (rc) | |
357 | return; | |
358 | ||
359 | status_addr = bank_irq_reg(gpio, bank, GPIO_IRQ_STATUS); | |
360 | ||
361 | spin_lock_irqsave(&gpio->lock, flags); | |
362 | iowrite32(bit, status_addr); | |
363 | spin_unlock_irqrestore(&gpio->lock, flags); | |
364 | } | |
365 | ||
366 | static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set) | |
367 | { | |
368 | const struct aspeed_gpio_bank *bank; | |
369 | struct aspeed_gpio *gpio; | |
370 | unsigned long flags; | |
371 | u32 reg, bit; | |
372 | void __iomem *addr; | |
373 | int rc; | |
374 | ||
375 | rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit); | |
376 | if (rc) | |
377 | return; | |
378 | ||
379 | addr = bank_irq_reg(gpio, bank, GPIO_IRQ_ENABLE); | |
380 | ||
381 | spin_lock_irqsave(&gpio->lock, flags); | |
382 | ||
383 | reg = ioread32(addr); | |
384 | if (set) | |
385 | reg |= bit; | |
386 | else | |
f241632f | 387 | reg &= ~bit; |
361b7911 JS |
388 | iowrite32(reg, addr); |
389 | ||
390 | spin_unlock_irqrestore(&gpio->lock, flags); | |
391 | } | |
392 | ||
393 | static void aspeed_gpio_irq_mask(struct irq_data *d) | |
394 | { | |
395 | aspeed_gpio_irq_set_mask(d, false); | |
396 | } | |
397 | ||
398 | static void aspeed_gpio_irq_unmask(struct irq_data *d) | |
399 | { | |
400 | aspeed_gpio_irq_set_mask(d, true); | |
401 | } | |
402 | ||
403 | static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type) | |
404 | { | |
405 | u32 type0 = 0; | |
406 | u32 type1 = 0; | |
407 | u32 type2 = 0; | |
408 | u32 bit, reg; | |
409 | const struct aspeed_gpio_bank *bank; | |
410 | irq_flow_handler_t handler; | |
411 | struct aspeed_gpio *gpio; | |
412 | unsigned long flags; | |
413 | void __iomem *addr; | |
414 | int rc; | |
415 | ||
416 | rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit); | |
417 | if (rc) | |
418 | return -EINVAL; | |
419 | ||
420 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
421 | case IRQ_TYPE_EDGE_BOTH: | |
422 | type2 |= bit; | |
e80df7b8 | 423 | /* fall through */ |
361b7911 JS |
424 | case IRQ_TYPE_EDGE_RISING: |
425 | type0 |= bit; | |
e80df7b8 | 426 | /* fall through */ |
361b7911 JS |
427 | case IRQ_TYPE_EDGE_FALLING: |
428 | handler = handle_edge_irq; | |
429 | break; | |
430 | case IRQ_TYPE_LEVEL_HIGH: | |
431 | type0 |= bit; | |
e80df7b8 | 432 | /* fall through */ |
361b7911 JS |
433 | case IRQ_TYPE_LEVEL_LOW: |
434 | type1 |= bit; | |
435 | handler = handle_level_irq; | |
436 | break; | |
437 | default: | |
438 | return -EINVAL; | |
439 | } | |
440 | ||
441 | spin_lock_irqsave(&gpio->lock, flags); | |
442 | ||
443 | addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE0); | |
444 | reg = ioread32(addr); | |
445 | reg = (reg & ~bit) | type0; | |
446 | iowrite32(reg, addr); | |
447 | ||
448 | addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE1); | |
449 | reg = ioread32(addr); | |
450 | reg = (reg & ~bit) | type1; | |
451 | iowrite32(reg, addr); | |
452 | ||
453 | addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE2); | |
454 | reg = ioread32(addr); | |
455 | reg = (reg & ~bit) | type2; | |
456 | iowrite32(reg, addr); | |
457 | ||
458 | spin_unlock_irqrestore(&gpio->lock, flags); | |
459 | ||
460 | irq_set_handler_locked(d, handler); | |
461 | ||
462 | return 0; | |
463 | } | |
464 | ||
465 | static void aspeed_gpio_irq_handler(struct irq_desc *desc) | |
466 | { | |
467 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); | |
468 | struct irq_chip *ic = irq_desc_get_chip(desc); | |
469 | struct aspeed_gpio *data = gpiochip_get_data(gc); | |
470 | unsigned int i, p, girq; | |
471 | unsigned long reg; | |
472 | ||
473 | chained_irq_enter(ic, desc); | |
474 | ||
475 | for (i = 0; i < ARRAY_SIZE(aspeed_gpio_banks); i++) { | |
476 | const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; | |
477 | ||
478 | reg = ioread32(bank_irq_reg(data, bank, GPIO_IRQ_STATUS)); | |
479 | ||
480 | for_each_set_bit(p, ®, 32) { | |
f0fbe7bc | 481 | girq = irq_find_mapping(gc->irq.domain, i * 32 + p); |
361b7911 JS |
482 | generic_handle_irq(girq); |
483 | } | |
484 | ||
485 | } | |
486 | ||
487 | chained_irq_exit(ic, desc); | |
488 | } | |
489 | ||
490 | static struct irq_chip aspeed_gpio_irqchip = { | |
491 | .name = "aspeed-gpio", | |
492 | .irq_ack = aspeed_gpio_irq_ack, | |
493 | .irq_mask = aspeed_gpio_irq_mask, | |
494 | .irq_unmask = aspeed_gpio_irq_unmask, | |
495 | .irq_set_type = aspeed_gpio_set_type, | |
496 | }; | |
497 | ||
1736f75d AJ |
498 | static void set_irq_valid_mask(struct aspeed_gpio *gpio) |
499 | { | |
500 | const struct aspeed_bank_props *props = gpio->config->props; | |
501 | ||
502 | while (!is_bank_props_sentinel(props)) { | |
503 | unsigned int offset; | |
504 | const unsigned long int input = props->input; | |
505 | ||
506 | /* Pretty crummy approach, but similar to GPIO core */ | |
507 | for_each_clear_bit(offset, &input, 32) { | |
508 | unsigned int i = props->bank * 32 + offset; | |
509 | ||
510 | if (i >= gpio->config->nr_gpios) | |
511 | break; | |
512 | ||
dc7b0387 | 513 | clear_bit(i, gpio->chip.irq.valid_mask); |
1736f75d AJ |
514 | } |
515 | ||
516 | props++; | |
517 | } | |
518 | } | |
519 | ||
361b7911 JS |
520 | static int aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio, |
521 | struct platform_device *pdev) | |
522 | { | |
523 | int rc; | |
524 | ||
525 | rc = platform_get_irq(pdev, 0); | |
526 | if (rc < 0) | |
527 | return rc; | |
528 | ||
529 | gpio->irq = rc; | |
530 | ||
1736f75d AJ |
531 | set_irq_valid_mask(gpio); |
532 | ||
361b7911 JS |
533 | rc = gpiochip_irqchip_add(&gpio->chip, &aspeed_gpio_irqchip, |
534 | 0, handle_bad_irq, IRQ_TYPE_NONE); | |
535 | if (rc) { | |
536 | dev_info(&pdev->dev, "Could not add irqchip\n"); | |
537 | return rc; | |
538 | } | |
539 | ||
540 | gpiochip_set_chained_irqchip(&gpio->chip, &aspeed_gpio_irqchip, | |
541 | gpio->irq, aspeed_gpio_irq_handler); | |
542 | ||
543 | return 0; | |
544 | } | |
545 | ||
1b43d269 AJ |
546 | static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip, |
547 | unsigned int offset, bool enable) | |
548 | { | |
549 | struct aspeed_gpio *gpio = gpiochip_get_data(chip); | |
550 | const struct aspeed_gpio_bank *bank; | |
551 | unsigned long flags; | |
552 | u32 val; | |
553 | ||
554 | bank = to_bank(offset); | |
555 | ||
556 | spin_lock_irqsave(&gpio->lock, flags); | |
557 | val = readl(gpio->base + bank->tolerance_regs); | |
558 | ||
559 | if (enable) | |
560 | val |= GPIO_BIT(offset); | |
561 | else | |
562 | val &= ~GPIO_BIT(offset); | |
563 | ||
564 | writel(val, gpio->base + bank->tolerance_regs); | |
565 | spin_unlock_irqrestore(&gpio->lock, flags); | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
361b7911 JS |
570 | static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset) |
571 | { | |
1736f75d AJ |
572 | if (!have_gpio(gpiochip_get_data(chip), offset)) |
573 | return -ENODEV; | |
574 | ||
a9a1d2a7 | 575 | return pinctrl_gpio_request(chip->base + offset); |
361b7911 JS |
576 | } |
577 | ||
578 | static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset) | |
579 | { | |
a9a1d2a7 | 580 | pinctrl_gpio_free(chip->base + offset); |
361b7911 JS |
581 | } |
582 | ||
5ae4cb94 AJ |
583 | static inline void __iomem *bank_debounce_reg(struct aspeed_gpio *gpio, |
584 | const struct aspeed_gpio_bank *bank, | |
585 | unsigned int reg) | |
586 | { | |
587 | return gpio->base + bank->debounce_regs + reg; | |
588 | } | |
589 | ||
590 | static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs, | |
591 | u32 *cycles) | |
592 | { | |
593 | u64 rate; | |
594 | u64 n; | |
595 | u32 r; | |
596 | ||
597 | rate = clk_get_rate(gpio->clk); | |
598 | if (!rate) | |
599 | return -ENOTSUPP; | |
600 | ||
601 | n = rate * usecs; | |
602 | r = do_div(n, 1000000); | |
603 | ||
604 | if (n >= U32_MAX) | |
605 | return -ERANGE; | |
606 | ||
607 | /* At least as long as the requested time */ | |
608 | *cycles = n + (!!r); | |
609 | ||
610 | return 0; | |
611 | } | |
612 | ||
613 | /* Call under gpio->lock */ | |
614 | static int register_allocated_timer(struct aspeed_gpio *gpio, | |
615 | unsigned int offset, unsigned int timer) | |
616 | { | |
617 | if (WARN(gpio->offset_timer[offset] != 0, | |
618 | "Offset %d already allocated timer %d\n", | |
619 | offset, gpio->offset_timer[offset])) | |
620 | return -EINVAL; | |
621 | ||
622 | if (WARN(gpio->timer_users[timer] == UINT_MAX, | |
623 | "Timer user count would overflow\n")) | |
624 | return -EPERM; | |
625 | ||
626 | gpio->offset_timer[offset] = timer; | |
627 | gpio->timer_users[timer]++; | |
628 | ||
629 | return 0; | |
630 | } | |
631 | ||
632 | /* Call under gpio->lock */ | |
633 | static int unregister_allocated_timer(struct aspeed_gpio *gpio, | |
634 | unsigned int offset) | |
635 | { | |
636 | if (WARN(gpio->offset_timer[offset] == 0, | |
637 | "No timer allocated to offset %d\n", offset)) | |
638 | return -EINVAL; | |
639 | ||
640 | if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0, | |
641 | "No users recorded for timer %d\n", | |
642 | gpio->offset_timer[offset])) | |
643 | return -EINVAL; | |
644 | ||
645 | gpio->timer_users[gpio->offset_timer[offset]]--; | |
646 | gpio->offset_timer[offset] = 0; | |
647 | ||
648 | return 0; | |
649 | } | |
650 | ||
651 | /* Call under gpio->lock */ | |
652 | static inline bool timer_allocation_registered(struct aspeed_gpio *gpio, | |
653 | unsigned int offset) | |
654 | { | |
655 | return gpio->offset_timer[offset] > 0; | |
656 | } | |
657 | ||
658 | /* Call under gpio->lock */ | |
659 | static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset, | |
660 | unsigned int timer) | |
661 | { | |
662 | const struct aspeed_gpio_bank *bank = to_bank(offset); | |
663 | const u32 mask = GPIO_BIT(offset); | |
664 | void __iomem *addr; | |
665 | u32 val; | |
666 | ||
667 | addr = bank_debounce_reg(gpio, bank, GPIO_DEBOUNCE_SEL1); | |
668 | val = ioread32(addr); | |
669 | iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr); | |
670 | ||
671 | addr = bank_debounce_reg(gpio, bank, GPIO_DEBOUNCE_SEL2); | |
672 | val = ioread32(addr); | |
673 | iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr); | |
674 | } | |
675 | ||
676 | static int enable_debounce(struct gpio_chip *chip, unsigned int offset, | |
677 | unsigned long usecs) | |
678 | { | |
679 | struct aspeed_gpio *gpio = gpiochip_get_data(chip); | |
680 | u32 requested_cycles; | |
681 | unsigned long flags; | |
682 | int rc; | |
683 | int i; | |
684 | ||
df563c85 JS |
685 | if (!gpio->clk) |
686 | return -EINVAL; | |
687 | ||
5ae4cb94 AJ |
688 | rc = usecs_to_cycles(gpio, usecs, &requested_cycles); |
689 | if (rc < 0) { | |
690 | dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n", | |
691 | usecs, clk_get_rate(gpio->clk), rc); | |
692 | return rc; | |
693 | } | |
694 | ||
695 | spin_lock_irqsave(&gpio->lock, flags); | |
696 | ||
697 | if (timer_allocation_registered(gpio, offset)) { | |
698 | rc = unregister_allocated_timer(gpio, offset); | |
699 | if (rc < 0) | |
700 | goto out; | |
701 | } | |
702 | ||
703 | /* Try to find a timer already configured for the debounce period */ | |
704 | for (i = 1; i < ARRAY_SIZE(debounce_timers); i++) { | |
705 | u32 cycles; | |
706 | ||
707 | cycles = ioread32(gpio->base + debounce_timers[i]); | |
708 | if (requested_cycles == cycles) | |
709 | break; | |
710 | } | |
711 | ||
712 | if (i == ARRAY_SIZE(debounce_timers)) { | |
713 | int j; | |
714 | ||
715 | /* | |
716 | * As there are no timers configured for the requested debounce | |
717 | * period, find an unused timer instead | |
718 | */ | |
719 | for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) { | |
720 | if (gpio->timer_users[j] == 0) | |
721 | break; | |
722 | } | |
723 | ||
724 | if (j == ARRAY_SIZE(gpio->timer_users)) { | |
725 | dev_warn(chip->parent, | |
726 | "Debounce timers exhausted, cannot debounce for period %luus\n", | |
727 | usecs); | |
728 | ||
729 | rc = -EPERM; | |
730 | ||
731 | /* | |
732 | * We already adjusted the accounting to remove @offset | |
733 | * as a user of its previous timer, so also configure | |
734 | * the hardware so @offset has timers disabled for | |
735 | * consistency. | |
736 | */ | |
737 | configure_timer(gpio, offset, 0); | |
738 | goto out; | |
739 | } | |
740 | ||
741 | i = j; | |
742 | ||
743 | iowrite32(requested_cycles, gpio->base + debounce_timers[i]); | |
744 | } | |
745 | ||
746 | if (WARN(i == 0, "Cannot register index of disabled timer\n")) { | |
747 | rc = -EINVAL; | |
748 | goto out; | |
749 | } | |
750 | ||
751 | register_allocated_timer(gpio, offset, i); | |
752 | configure_timer(gpio, offset, i); | |
753 | ||
754 | out: | |
755 | spin_unlock_irqrestore(&gpio->lock, flags); | |
756 | ||
757 | return rc; | |
758 | } | |
759 | ||
760 | static int disable_debounce(struct gpio_chip *chip, unsigned int offset) | |
761 | { | |
762 | struct aspeed_gpio *gpio = gpiochip_get_data(chip); | |
763 | unsigned long flags; | |
764 | int rc; | |
765 | ||
766 | spin_lock_irqsave(&gpio->lock, flags); | |
767 | ||
768 | rc = unregister_allocated_timer(gpio, offset); | |
769 | if (!rc) | |
770 | configure_timer(gpio, offset, 0); | |
771 | ||
772 | spin_unlock_irqrestore(&gpio->lock, flags); | |
773 | ||
774 | return rc; | |
775 | } | |
776 | ||
777 | static int set_debounce(struct gpio_chip *chip, unsigned int offset, | |
778 | unsigned long usecs) | |
779 | { | |
780 | struct aspeed_gpio *gpio = gpiochip_get_data(chip); | |
781 | ||
782 | if (!have_debounce(gpio, offset)) | |
783 | return -ENOTSUPP; | |
784 | ||
785 | if (usecs) | |
786 | return enable_debounce(chip, offset, usecs); | |
787 | ||
788 | return disable_debounce(chip, offset); | |
789 | } | |
790 | ||
791 | static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset, | |
792 | unsigned long config) | |
793 | { | |
794 | unsigned long param = pinconf_to_config_param(config); | |
795 | u32 arg = pinconf_to_config_argument(config); | |
796 | ||
797 | if (param == PIN_CONFIG_INPUT_DEBOUNCE) | |
798 | return set_debounce(chip, offset, arg); | |
799 | else if (param == PIN_CONFIG_BIAS_DISABLE || | |
800 | param == PIN_CONFIG_BIAS_PULL_DOWN || | |
801 | param == PIN_CONFIG_DRIVE_STRENGTH) | |
802 | return pinctrl_gpio_set_config(offset, config); | |
c3bafe01 AJ |
803 | else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN || |
804 | param == PIN_CONFIG_DRIVE_OPEN_SOURCE) | |
805 | /* Return -ENOTSUPP to trigger emulation, as per datasheet */ | |
806 | return -ENOTSUPP; | |
1b43d269 AJ |
807 | else if (param == PIN_CONFIG_PERSIST_STATE) |
808 | return aspeed_gpio_reset_tolerance(chip, offset, arg); | |
5ae4cb94 AJ |
809 | |
810 | return -ENOTSUPP; | |
811 | } | |
812 | ||
1736f75d AJ |
813 | /* |
814 | * Any banks not specified in a struct aspeed_bank_props array are assumed to | |
815 | * have the properties: | |
816 | * | |
817 | * { .input = 0xffffffff, .output = 0xffffffff } | |
818 | */ | |
819 | ||
820 | static const struct aspeed_bank_props ast2400_bank_props[] = { | |
821 | /* input output */ | |
822 | { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ | |
823 | { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */ | |
824 | { }, | |
825 | }; | |
826 | ||
827 | static const struct aspeed_gpio_config ast2400_config = | |
828 | /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */ | |
829 | { .nr_gpios = 220, .props = ast2400_bank_props, }; | |
830 | ||
831 | static const struct aspeed_bank_props ast2500_bank_props[] = { | |
832 | /* input output */ | |
833 | { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ | |
834 | { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */ | |
835 | { 7, 0x000000ff, 0x000000ff }, /* AC */ | |
836 | { }, | |
837 | }; | |
838 | ||
839 | static const struct aspeed_gpio_config ast2500_config = | |
840 | /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */ | |
841 | { .nr_gpios = 232, .props = ast2500_bank_props, }; | |
842 | ||
843 | static const struct of_device_id aspeed_gpio_of_table[] = { | |
844 | { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, }, | |
845 | { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, }, | |
846 | {} | |
847 | }; | |
848 | MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table); | |
849 | ||
361b7911 JS |
850 | static int __init aspeed_gpio_probe(struct platform_device *pdev) |
851 | { | |
1736f75d | 852 | const struct of_device_id *gpio_id; |
361b7911 JS |
853 | struct aspeed_gpio *gpio; |
854 | struct resource *res; | |
855 | int rc; | |
856 | ||
857 | gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); | |
858 | if (!gpio) | |
859 | return -ENOMEM; | |
860 | ||
861 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
361b7911 | 862 | gpio->base = devm_ioremap_resource(&pdev->dev, res); |
7f8b9657 WY |
863 | if (IS_ERR(gpio->base)) |
864 | return PTR_ERR(gpio->base); | |
361b7911 JS |
865 | |
866 | spin_lock_init(&gpio->lock); | |
867 | ||
1736f75d AJ |
868 | gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); |
869 | if (!gpio_id) | |
870 | return -EINVAL; | |
871 | ||
5ae4cb94 AJ |
872 | gpio->clk = of_clk_get(pdev->dev.of_node, 0); |
873 | if (IS_ERR(gpio->clk)) { | |
874 | dev_warn(&pdev->dev, | |
754c0458 | 875 | "Failed to get clock from devicetree, debouncing disabled\n"); |
5ae4cb94 AJ |
876 | gpio->clk = NULL; |
877 | } | |
878 | ||
1736f75d | 879 | gpio->config = gpio_id->data; |
361b7911 | 880 | |
5ae4cb94 | 881 | gpio->chip.parent = &pdev->dev; |
1736f75d | 882 | gpio->chip.ngpio = gpio->config->nr_gpios; |
361b7911 JS |
883 | gpio->chip.parent = &pdev->dev; |
884 | gpio->chip.direction_input = aspeed_gpio_dir_in; | |
885 | gpio->chip.direction_output = aspeed_gpio_dir_out; | |
886 | gpio->chip.get_direction = aspeed_gpio_get_direction; | |
887 | gpio->chip.request = aspeed_gpio_request; | |
888 | gpio->chip.free = aspeed_gpio_free; | |
889 | gpio->chip.get = aspeed_gpio_get; | |
890 | gpio->chip.set = aspeed_gpio_set; | |
5ae4cb94 | 891 | gpio->chip.set_config = aspeed_gpio_set_config; |
361b7911 JS |
892 | gpio->chip.label = dev_name(&pdev->dev); |
893 | gpio->chip.base = -1; | |
dc7b0387 | 894 | gpio->chip.irq.need_valid_mask = true; |
361b7911 JS |
895 | |
896 | rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); | |
897 | if (rc < 0) | |
898 | return rc; | |
899 | ||
5ae4cb94 AJ |
900 | gpio->offset_timer = |
901 | devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL); | |
902 | ||
361b7911 JS |
903 | return aspeed_gpio_setup_irqs(gpio, pdev); |
904 | } | |
905 | ||
361b7911 JS |
906 | static struct platform_driver aspeed_gpio_driver = { |
907 | .driver = { | |
908 | .name = KBUILD_MODNAME, | |
909 | .of_match_table = aspeed_gpio_of_table, | |
910 | }, | |
911 | }; | |
912 | ||
913 | module_platform_driver_probe(aspeed_gpio_driver, aspeed_gpio_probe); | |
914 | ||
915 | MODULE_DESCRIPTION("Aspeed GPIO Driver"); | |
e50237c7 | 916 | MODULE_LICENSE("GPL"); |