[linux-2.6-block.git] / drivers / gpio / gpio-aspeed-sgpio.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2019 American Megatrends International LLC.
 *
 * Author: Karthikeyan Mani <karthikeyanm@amiindia.co.in>
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/gpio/driver.h>
#include <linux/hashtable.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/string.h>

#define ASPEED_SGPIO_CTRL		0x54

#define ASPEED_SGPIO_CLK_DIV_MASK	GENMASK(31, 16)
#define ASPEED_SGPIO_ENABLE		BIT(0)
#define ASPEED_SGPIO_PINS_SHIFT		6

struct aspeed_sgpio_pdata {
	const u32 pin_mask;
};

struct aspeed_sgpio {
	struct gpio_chip chip;
	struct irq_chip intc;
	struct clk *pclk;
	spinlock_t lock;
	void __iomem *base;
	int irq;
};

struct aspeed_sgpio_bank {
	u16    val_regs;
	u16    rdata_reg;
	u16    irq_regs;
	u16    tolerance_regs;
	const char  names[4][3];
};

/*
 * Note: The "value" register returns the input value when the GPIO is
 *	 configured as an input.
 *
 *	 The "rdata" register returns the output value when the GPIO is
 *	 configured as an output.
 */
static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
	{
		.val_regs = 0x0000,
		.rdata_reg = 0x0070,
		.irq_regs = 0x0004,
		.tolerance_regs = 0x0018,
		.names = { "A", "B", "C", "D" },
	},
	{
		.val_regs = 0x001C,
		.rdata_reg = 0x0074,
		.irq_regs = 0x0020,
		.tolerance_regs = 0x0034,
		.names = { "E", "F", "G", "H" },
	},
	{
		.val_regs = 0x0038,
		.rdata_reg = 0x0078,
		.irq_regs = 0x003C,
		.tolerance_regs = 0x0050,
		.names = { "I", "J", "K", "L" },
	},
	{
		.val_regs = 0x0090,
		.rdata_reg = 0x007C,
		.irq_regs = 0x0094,
		.tolerance_regs = 0x00A8,
		.names = { "M", "N", "O", "P" },
	},
};

enum aspeed_sgpio_reg {
	reg_val,
	reg_rdata,
	reg_irq_enable,
	reg_irq_type0,
	reg_irq_type1,
	reg_irq_type2,
	reg_irq_status,
	reg_tolerance,
};

#define GPIO_VAL_VALUE      0x00
#define GPIO_IRQ_ENABLE     0x00
#define GPIO_IRQ_TYPE0      0x04
#define GPIO_IRQ_TYPE1      0x08
#define GPIO_IRQ_TYPE2      0x0C
#define GPIO_IRQ_STATUS     0x10

static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
				     const struct aspeed_sgpio_bank *bank,
				     const enum aspeed_sgpio_reg reg)
{
	switch (reg) {
	case reg_val:
		return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
	case reg_rdata:
		return gpio->base + bank->rdata_reg;
	case reg_irq_enable:
		return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
	case reg_irq_type0:
		return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
	case reg_irq_type1:
		return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
	case reg_irq_type2:
		return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
	case reg_irq_status:
		return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
	case reg_tolerance:
		return gpio->base + bank->tolerance_regs;
	default:
		/* acturally if code runs to here, it's an error case */
		BUG();
	}
}

#define GPIO_BANK(x)    ((x) >> 6)
#define GPIO_OFFSET(x)  ((x) & GENMASK(5, 0))
#define GPIO_BIT(x)     BIT(GPIO_OFFSET(x) >> 1)

static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
{
	unsigned int bank;

	bank = GPIO_BANK(offset);

	WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
	return &aspeed_sgpio_banks[bank];
}

static int aspeed_sgpio_init_valid_mask(struct gpio_chip *gc,
		unsigned long *valid_mask, unsigned int ngpios)
{
	bitmap_set(valid_mask, 0, ngpios);
	return 0;
}

static void aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
		unsigned long *valid_mask, unsigned int ngpios)
{
	unsigned int i;

	/* input GPIOs are even bits */
	for (i = 0; i < ngpios; i++) {
		if (i % 2)
			clear_bit(i, valid_mask);
	}
}

static bool aspeed_sgpio_is_input(unsigned int offset)
{
	return !(offset % 2);
}

static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
{
	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
	const struct aspeed_sgpio_bank *bank = to_bank(offset);
	unsigned long flags;
	enum aspeed_sgpio_reg reg;
	int rc = 0;

	spin_lock_irqsave(&gpio->lock, flags);

	reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));

	spin_unlock_irqrestore(&gpio->lock, flags);

	return rc;
}

static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
{
	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
	const struct aspeed_sgpio_bank *bank = to_bank(offset);
	void __iomem *addr_r, *addr_w;
	u32 reg = 0;

	if (aspeed_sgpio_is_input(offset))
		return -EINVAL;

	/* Since this is an output, read the cached value from rdata, then
	 * update val. */
	addr_r = bank_reg(gpio, bank, reg_rdata);
	addr_w = bank_reg(gpio, bank, reg_val);

	reg = ioread32(addr_r);

	if (val)
		reg |= GPIO_BIT(offset);
	else
		reg &= ~GPIO_BIT(offset);

	iowrite32(reg, addr_w);

	return 0;
}

static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
{
	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
	unsigned long flags;

	spin_lock_irqsave(&gpio->lock, flags);

	sgpio_set_value(gc, offset, val);

	spin_unlock_irqrestore(&gpio->lock, flags);
}

static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
{
	return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
}

static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
{
	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
	unsigned long flags;
	int rc;

	/* No special action is required for setting the direction; we'll
	 * error-out in sgpio_set_value if this isn't an output GPIO */

	spin_lock_irqsave(&gpio->lock, flags);
	rc = sgpio_set_value(gc, offset, val);
	spin_unlock_irqrestore(&gpio->lock, flags);

	return rc;
}

static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
{
	return !!aspeed_sgpio_is_input(offset);
}

static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
					struct aspeed_sgpio **gpio,
					const struct aspeed_sgpio_bank **bank,
					u32 *bit, int *offset)
{
	struct aspeed_sgpio *internal;

	*offset = irqd_to_hwirq(d);
	internal = irq_data_get_irq_chip_data(d);
	WARN_ON(!internal);

	*gpio = internal;
	*bank = to_bank(*offset);
	*bit = GPIO_BIT(*offset);
}

static void aspeed_sgpio_irq_ack(struct irq_data *d)
{
	const struct aspeed_sgpio_bank *bank;
	struct aspeed_sgpio *gpio;
	unsigned long flags;
	void __iomem *status_addr;
	int offset;
	u32 bit;

	irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);

	status_addr = bank_reg(gpio, bank, reg_irq_status);

	spin_lock_irqsave(&gpio->lock, flags);

	iowrite32(bit, status_addr);

	spin_unlock_irqrestore(&gpio->lock, flags);
}

static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set)
{
	const struct aspeed_sgpio_bank *bank;
	struct aspeed_sgpio *gpio;
	unsigned long flags;
	u32 reg, bit;
	void __iomem *addr;
	int offset;

	irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
	addr = bank_reg(gpio, bank, reg_irq_enable);

	spin_lock_irqsave(&gpio->lock, flags);

	reg = ioread32(addr);
	if (set)
		reg |= bit;
	else
		reg &= ~bit;

	iowrite32(reg, addr);

	spin_unlock_irqrestore(&gpio->lock, flags);
}

static void aspeed_sgpio_irq_mask(struct irq_data *d)
{
	aspeed_sgpio_irq_set_mask(d, false);
}

static void aspeed_sgpio_irq_unmask(struct irq_data *d)
{
	aspeed_sgpio_irq_set_mask(d, true);
}

static int aspeed_sgpio_set_type(struct irq_data *d, unsigned int type)
{
	u32 type0 = 0;
	u32 type1 = 0;
	u32 type2 = 0;
	u32 bit, reg;
	const struct aspeed_sgpio_bank *bank;
	irq_flow_handler_t handler;
	struct aspeed_sgpio *gpio;
	unsigned long flags;
	void __iomem *addr;
	int offset;

	irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_EDGE_BOTH:
		type2 |= bit;
		fallthrough;
	case IRQ_TYPE_EDGE_RISING:
		type0 |= bit;
		fallthrough;
	case IRQ_TYPE_EDGE_FALLING:
		handler = handle_edge_irq;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		type0 |= bit;
		fallthrough;
	case IRQ_TYPE_LEVEL_LOW:
		type1 |= bit;
		handler = handle_level_irq;
		break;
	default:
		return -EINVAL;
	}

	spin_lock_irqsave(&gpio->lock, flags);

	addr = bank_reg(gpio, bank, reg_irq_type0);
	reg = ioread32(addr);
	reg = (reg & ~bit) | type0;
	iowrite32(reg, addr);

	addr = bank_reg(gpio, bank, reg_irq_type1);
	reg = ioread32(addr);
	reg = (reg & ~bit) | type1;
	iowrite32(reg, addr);

	addr = bank_reg(gpio, bank, reg_irq_type2);
	reg = ioread32(addr);
	reg = (reg & ~bit) | type2;
	iowrite32(reg, addr);

	spin_unlock_irqrestore(&gpio->lock, flags);

	irq_set_handler_locked(d, handler);

	return 0;
}

static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
{
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	struct irq_chip *ic = irq_desc_get_chip(desc);
	struct aspeed_sgpio *data = gpiochip_get_data(gc);
	unsigned int i, p;
	unsigned long reg;

	chained_irq_enter(ic, desc);

	for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
		const struct aspeed_sgpio_bank *bank = &aspeed_sgpio_banks[i];

		reg = ioread32(bank_reg(data, bank, reg_irq_status));

		for_each_set_bit(p, &reg, 32)
			generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
	}

	chained_irq_exit(ic, desc);
}

static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
				   struct platform_device *pdev)
{
	int rc, i;
	const struct aspeed_sgpio_bank *bank;
	struct gpio_irq_chip *irq;

	rc = platform_get_irq(pdev, 0);
	if (rc < 0)
		return rc;

	gpio->irq = rc;

	/* Disable IRQ and clear Interrupt status registers for all SGPIO Pins. */
	for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
		bank =  &aspeed_sgpio_banks[i];
		/* disable irq enable bits */
		iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable));
		/* clear status bits */
		iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status));
	}

	gpio->intc.name = dev_name(&pdev->dev);
	gpio->intc.irq_ack = aspeed_sgpio_irq_ack;
	gpio->intc.irq_mask = aspeed_sgpio_irq_mask;
	gpio->intc.irq_unmask = aspeed_sgpio_irq_unmask;
	gpio->intc.irq_set_type = aspeed_sgpio_set_type;

	irq = &gpio->chip.irq;
	irq->chip = &gpio->intc;
	irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask;
	irq->handler = handle_bad_irq;
	irq->default_type = IRQ_TYPE_NONE;
	irq->parent_handler = aspeed_sgpio_irq_handler;
	irq->parent_handler_data = gpio;
	irq->parents = &gpio->irq;
	irq->num_parents = 1;

	/* Apply default IRQ settings */
	for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
		bank = &aspeed_sgpio_banks[i];
		/* set falling or level-low irq */
		iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0));
		/* trigger type is edge */
		iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1));
		/* single edge trigger */
		iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type2));
	}

	return 0;
}

static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
	.pin_mask = GENMASK(9, 6),
};

static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip,
					unsigned int offset, bool enable)
{
	struct aspeed_sgpio *gpio = gpiochip_get_data(chip);
	unsigned long flags;
	void __iomem *reg;
	u32 val;

	reg = bank_reg(gpio, to_bank(offset), reg_tolerance);

	spin_lock_irqsave(&gpio->lock, flags);

	val = readl(reg);

	if (enable)
		val |= GPIO_BIT(offset);
	else
		val &= ~GPIO_BIT(offset);

	writel(val, reg);

	spin_unlock_irqrestore(&gpio->lock, flags);

	return 0;
}

static int aspeed_sgpio_set_config(struct gpio_chip *chip, unsigned int offset,
				   unsigned long config)
{
	unsigned long param = pinconf_to_config_param(config);
	u32 arg = pinconf_to_config_argument(config);

	if (param == PIN_CONFIG_PERSIST_STATE)
		return aspeed_sgpio_reset_tolerance(chip, offset, arg);

	return -ENOTSUPP;
}

static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata = {
	.pin_mask = GENMASK(10, 6),
};

static const struct of_device_id aspeed_sgpio_of_table[] = {
	{ .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata, },
	{ .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata, },
	{ .compatible = "aspeed,ast2600-sgpiom", .data = &ast2600_sgpiom_pdata, },
	{}
};

MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);

static int __init aspeed_sgpio_probe(struct platform_device *pdev)
{
	u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask;
	const struct aspeed_sgpio_pdata *pdata;
	struct aspeed_sgpio *gpio;
	unsigned long apb_freq;
	int rc;

	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
	if (!gpio)
		return -ENOMEM;

	gpio->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(gpio->base))
		return PTR_ERR(gpio->base);

	pdata = device_get_match_data(&pdev->dev);
	if (!pdata)
		return -EINVAL;

	pin_mask = pdata->pin_mask;

	rc = device_property_read_u32(&pdev->dev, "ngpios", &nr_gpios);
	if (rc < 0) {
		dev_err(&pdev->dev, "Could not read ngpios property\n");
		return -EINVAL;
	} else if (nr_gpios % 8) {
		dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n",
			nr_gpios);
		return -EINVAL;
	}

	rc = device_property_read_u32(&pdev->dev, "bus-frequency", &sgpio_freq);
	if (rc < 0) {
		dev_err(&pdev->dev, "Could not read bus-frequency property\n");
		return -EINVAL;
	}

	gpio->pclk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(gpio->pclk)) {
		dev_err(&pdev->dev, "devm_clk_get failed\n");
		return PTR_ERR(gpio->pclk);
	}

	apb_freq = clk_get_rate(gpio->pclk);

	/*
	 * From the datasheet,
	 *	SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1)
	 *	period = 2 * (GPIO254[31:16] + 1) / PCLK
	 *	frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK)
	 *	frequency = PCLK / (2 * (GPIO254[31:16] + 1))
	 *	frequency * 2 * (GPIO254[31:16] + 1) = PCLK
	 *	GPIO254[31:16] = PCLK / (frequency * 2) - 1
	 */
	if (sgpio_freq == 0)
		return -EINVAL;

	sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1;

	if (sgpio_clk_div > (1 << 16) - 1)
		return -EINVAL;

	gpio_cnt_regval = ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT) & pin_mask;
	iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) | gpio_cnt_regval |
		  ASPEED_SGPIO_ENABLE, gpio->base + ASPEED_SGPIO_CTRL);

	spin_lock_init(&gpio->lock);

	gpio->chip.parent = &pdev->dev;
	gpio->chip.ngpio = nr_gpios * 2;
	gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask;
	gpio->chip.direction_input = aspeed_sgpio_dir_in;
	gpio->chip.direction_output = aspeed_sgpio_dir_out;
	gpio->chip.get_direction = aspeed_sgpio_get_direction;
	gpio->chip.request = NULL;
	gpio->chip.free = NULL;
	gpio->chip.get = aspeed_sgpio_get;
	gpio->chip.set = aspeed_sgpio_set;
	gpio->chip.set_config = aspeed_sgpio_set_config;
	gpio->chip.label = dev_name(&pdev->dev);
	gpio->chip.base = -1;

	aspeed_sgpio_setup_irqs(gpio, pdev);

	rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
	if (rc < 0)
		return rc;

	return 0;
}

static struct platform_driver aspeed_sgpio_driver = {
	.driver = {
		.name = KBUILD_MODNAME,
		.of_match_table = aspeed_sgpio_of_table,
	},
};

module_platform_driver_probe(aspeed_sgpio_driver, aspeed_sgpio_probe);
MODULE_DESCRIPTION("Aspeed Serial GPIO Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
7db47faa HZ	1	// SPDX-License-Identifier: GPL-2.0-or-later
	2	/*
	3	* Copyright 2019 American Megatrends International LLC.
	4	*
	5	* Author: Karthikeyan Mani <karthikeyanm@amiindia.co.in>
	6	*/
	7
	8	#include <linux/bitfield.h>
	9	#include <linux/clk.h>
	10	#include <linux/gpio/driver.h>
	11	#include <linux/hashtable.h>
	12	#include <linux/init.h>
	13	#include <linux/io.h>
	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/spinlock.h>
	18	#include <linux/string.h>
	19
7db47faa HZ	20	#define ASPEED_SGPIO_CTRL 0x54
7db47faa HZ	21
7db47faa HZ	22	#define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16)
7db47faa HZ	23	#define ASPEED_SGPIO_ENABLE BIT(0)
e1f85d25 SL	24	#define ASPEED_SGPIO_PINS_SHIFT 6
	25
	26	struct aspeed_sgpio_pdata {
	27	const u32 pin_mask;
	28	};
7db47faa HZ	29
	30	struct aspeed_sgpio {
	31	struct gpio_chip chip;
09ac953b	32	struct irq_chip intc;
7db47faa HZ	33	struct clk *pclk;
	34	spinlock_t lock;
	35	void __iomem *base;
7db47faa HZ	36	int irq;
	37	};
	38
	39	struct aspeed_sgpio_bank {
8a3581c6 SL	40	u16 val_regs;
	41	u16 rdata_reg;
	42	u16 irq_regs;
	43	u16 tolerance_regs;
7db47faa HZ	44	const char names[4][3];
	45	};
	46
	47	/*
	48	* Note: The "value" register returns the input value when the GPIO is
	49	* configured as an input.
	50	*
	51	* The "rdata" register returns the output value when the GPIO is
	52	* configured as an output.
	53	*/
	54	static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
	55	{
	56	.val_regs = 0x0000,
	57	.rdata_reg = 0x0070,
	58	.irq_regs = 0x0004,
8a3581c6	59	.tolerance_regs = 0x0018,
7db47faa HZ	60	.names = { "A", "B", "C", "D" },
	61	},
	62	{
	63	.val_regs = 0x001C,
	64	.rdata_reg = 0x0074,
	65	.irq_regs = 0x0020,
8a3581c6	66	.tolerance_regs = 0x0034,
7db47faa HZ	67	.names = { "E", "F", "G", "H" },
	68	},
	69	{
	70	.val_regs = 0x0038,
	71	.rdata_reg = 0x0078,
	72	.irq_regs = 0x003C,
8a3581c6	73	.tolerance_regs = 0x0050,
e1f85d25 SL	74	.names = { "I", "J", "K", "L" },
	75	},
	76	{
	77	.val_regs = 0x0090,
	78	.rdata_reg = 0x007C,
	79	.irq_regs = 0x0094,
8a3581c6	80	.tolerance_regs = 0x00A8,
e1f85d25	81	.names = { "M", "N", "O", "P" },
7db47faa HZ	82	},
	83	};
	84
	85	enum aspeed_sgpio_reg {
	86	reg_val,
	87	reg_rdata,
	88	reg_irq_enable,
	89	reg_irq_type0,
	90	reg_irq_type1,
	91	reg_irq_type2,
	92	reg_irq_status,
8a3581c6	93	reg_tolerance,
7db47faa HZ	94	};
	95
	96	#define GPIO_VAL_VALUE 0x00
	97	#define GPIO_IRQ_ENABLE 0x00
	98	#define GPIO_IRQ_TYPE0 0x04
	99	#define GPIO_IRQ_TYPE1 0x08
	100	#define GPIO_IRQ_TYPE2 0x0C
	101	#define GPIO_IRQ_STATUS 0x10
	102
	103	static void __iomem bank_reg(struct aspeed_sgpio gpio,
	104	const struct aspeed_sgpio_bank *bank,
	105	const enum aspeed_sgpio_reg reg)
	106	{
	107	switch (reg) {
	108	case reg_val:
	109	return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
	110	case reg_rdata:
	111	return gpio->base + bank->rdata_reg;
	112	case reg_irq_enable:
	113	return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
	114	case reg_irq_type0:
	115	return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
	116	case reg_irq_type1:
	117	return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
	118	case reg_irq_type2:
	119	return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
	120	case reg_irq_status:
	121	return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
8a3581c6 SL	122	case reg_tolerance:
8a3581c6 SL	123	return gpio->base + bank->tolerance_regs;
7db47faa HZ	124	default:
7db47faa HZ	125	/* acturally if code runs to here, it's an error case */
11e299de	126	BUG();
7db47faa HZ	127	}
	128	}
	129
e1f85d25 SL	130	#define GPIO_BANK(x) ((x) >> 6)
	131	#define GPIO_OFFSET(x) ((x) & GENMASK(5, 0))
	132	#define GPIO_BIT(x) BIT(GPIO_OFFSET(x) >> 1)
7db47faa HZ	133
	134	static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
	135	{
ac67b07e JK	136	unsigned int bank;
	137
	138	bank = GPIO_BANK(offset);
7db47faa HZ	139
	140	WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
	141	return &aspeed_sgpio_banks[bank];
	142	}
	143
ac67b07e JK	144	static int aspeed_sgpio_init_valid_mask(struct gpio_chip *gc,
	145	unsigned long *valid_mask, unsigned int ngpios)
	146	{
e1f85d25	147	bitmap_set(valid_mask, 0, ngpios);
ac67b07e JK	148	return 0;
	149	}
	150
	151	static void aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
	152	unsigned long *valid_mask, unsigned int ngpios)
	153	{
e1f85d25	154	unsigned int i;
ac67b07e	155
e1f85d25 SL	156	/* input GPIOs are even bits */
	157	for (i = 0; i < ngpios; i++) {
	158	if (i % 2)
	159	clear_bit(i, valid_mask);
	160	}
ac67b07e JK	161	}
	162
	163	static bool aspeed_sgpio_is_input(unsigned int offset)
	164	{
e1f85d25	165	return !(offset % 2);
ac67b07e JK	166	}
ac67b07e JK	167
7db47faa HZ	168	static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
	169	{
	170	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
	171	const struct aspeed_sgpio_bank *bank = to_bank(offset);
	172	unsigned long flags;
	173	enum aspeed_sgpio_reg reg;
7db47faa HZ	174	int rc = 0;
	175
	176	spin_lock_irqsave(&gpio->lock, flags);
	177
ac67b07e	178	reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
7db47faa HZ	179	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
	180
	181	spin_unlock_irqrestore(&gpio->lock, flags);
	182
	183	return rc;
	184	}
	185
ac67b07e	186	static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
7db47faa HZ	187	{
	188	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
	189	const struct aspeed_sgpio_bank *bank = to_bank(offset);
ac67b07e	190	void __iomem addr_r, addr_w;
7db47faa HZ	191	u32 reg = 0;
7db47faa HZ	192
ac67b07e JK	193	if (aspeed_sgpio_is_input(offset))
	194	return -EINVAL;
	195
	196	/* Since this is an output, read the cached value from rdata, then
	197	* update val. */
	198	addr_r = bank_reg(gpio, bank, reg_rdata);
	199	addr_w = bank_reg(gpio, bank, reg_val);
	200
	201	reg = ioread32(addr_r);
7db47faa HZ	202
	203	if (val)
	204	reg \|= GPIO_BIT(offset);
	205	else
	206	reg &= ~GPIO_BIT(offset);
	207
ac67b07e JK	208	iowrite32(reg, addr_w);
	209
	210	return 0;
7db47faa HZ	211	}
	212
	213	static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
	214	{
	215	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
	216	unsigned long flags;
	217
	218	spin_lock_irqsave(&gpio->lock, flags);
	219
	220	sgpio_set_value(gc, offset, val);
	221
	222	spin_unlock_irqrestore(&gpio->lock, flags);
	223	}
	224
	225	static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
	226	{
ac67b07e	227	return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
7db47faa HZ	228	}
	229
	230	static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
	231	{
	232	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
	233	unsigned long flags;
ac67b07e	234	int rc;
7db47faa	235
ac67b07e JK	236	/* No special action is required for setting the direction; we'll
ac67b07e JK	237	* error-out in sgpio_set_value if this isn't an output GPIO */
7db47faa	238
ac67b07e JK	239	spin_lock_irqsave(&gpio->lock, flags);
ac67b07e JK	240	rc = sgpio_set_value(gc, offset, val);
7db47faa HZ	241	spin_unlock_irqrestore(&gpio->lock, flags);
7db47faa HZ	242
ac67b07e	243	return rc;
7db47faa HZ	244	}
	245
	246	static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
	247	{
ac67b07e	248	return !!aspeed_sgpio_is_input(offset);
7db47faa HZ	249	}
	250
	251	static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
	252	struct aspeed_sgpio **gpio,
	253	const struct aspeed_sgpio_bank **bank,
	254	u32 bit, int offset)
	255	{
	256	struct aspeed_sgpio *internal;
	257
	258	*offset = irqd_to_hwirq(d);
	259	internal = irq_data_get_irq_chip_data(d);
	260	WARN_ON(!internal);
	261
	262	*gpio = internal;
	263	bank = to_bank(offset);
	264	bit = GPIO_BIT(offset);
	265	}
	266
	267	static void aspeed_sgpio_irq_ack(struct irq_data *d)
	268	{
	269	const struct aspeed_sgpio_bank *bank;
	270	struct aspeed_sgpio *gpio;
	271	unsigned long flags;
	272	void __iomem *status_addr;
	273	int offset;
	274	u32 bit;
	275
	276	irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
	277
	278	status_addr = bank_reg(gpio, bank, reg_irq_status);
	279
	280	spin_lock_irqsave(&gpio->lock, flags);
	281
	282	iowrite32(bit, status_addr);
	283
	284	spin_unlock_irqrestore(&gpio->lock, flags);
	285	}
	286
	287	static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set)
	288	{
	289	const struct aspeed_sgpio_bank *bank;
	290	struct aspeed_sgpio *gpio;
	291	unsigned long flags;
	292	u32 reg, bit;
	293	void __iomem *addr;
	294	int offset;
	295
	296	irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
	297	addr = bank_reg(gpio, bank, reg_irq_enable);
	298
	299	spin_lock_irqsave(&gpio->lock, flags);
	300
	301	reg = ioread32(addr);
	302	if (set)
	303	reg \|= bit;
	304	else
	305	reg &= ~bit;
	306
	307	iowrite32(reg, addr);
	308
	309	spin_unlock_irqrestore(&gpio->lock, flags);
	310	}
	311
	312	static void aspeed_sgpio_irq_mask(struct irq_data *d)
313	{
314	aspeed_sgpio_irq_set_mask(d, false);
315	}
316
317	static void aspeed_sgpio_irq_unmask(struct irq_data *d)
318	{
319	aspeed_sgpio_irq_set_mask(d, true);
320	}
321
322	static int aspeed_sgpio_set_type(struct irq_data *d, unsigned int type)
323	{
324	u32 type0 = 0;
325	u32 type1 = 0;
326	u32 type2 = 0;
327	u32 bit, reg;
328	const struct aspeed_sgpio_bank *bank;
329	irq_flow_handler_t handler;
330	struct aspeed_sgpio *gpio;
331	unsigned long flags;
332	void __iomem *addr;
333	int offset;
334
335	irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
336
337	switch (type & IRQ_TYPE_SENSE_MASK) {
338	case IRQ_TYPE_EDGE_BOTH:
339	type2 \|= bit;
df561f66	340	fallthrough;
7db47faa HZ	341	case IRQ_TYPE_EDGE_RISING:
7db47faa HZ	342	type0 \|= bit;
df561f66	343	fallthrough;
7db47faa HZ	344	case IRQ_TYPE_EDGE_FALLING:
	345	handler = handle_edge_irq;
	346	break;
	347	case IRQ_TYPE_LEVEL_HIGH:
	348	type0 \|= bit;
df561f66	349	fallthrough;
7db47faa HZ	350	case IRQ_TYPE_LEVEL_LOW:
	351	type1 \|= bit;
	352	handler = handle_level_irq;
	353	break;
	354	default:
	355	return -EINVAL;
	356	}
	357
	358	spin_lock_irqsave(&gpio->lock, flags);
	359
	360	addr = bank_reg(gpio, bank, reg_irq_type0);
	361	reg = ioread32(addr);
	362	reg = (reg & ~bit) \| type0;
	363	iowrite32(reg, addr);
	364
	365	addr = bank_reg(gpio, bank, reg_irq_type1);
	366	reg = ioread32(addr);
	367	reg = (reg & ~bit) \| type1;
	368	iowrite32(reg, addr);
	369
	370	addr = bank_reg(gpio, bank, reg_irq_type2);
	371	reg = ioread32(addr);
	372	reg = (reg & ~bit) \| type2;
	373	iowrite32(reg, addr);
	374
	375	spin_unlock_irqrestore(&gpio->lock, flags);
	376
	377	irq_set_handler_locked(d, handler);
	378
	379	return 0;
	380	}
	381
	382	static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
	383	{
	384	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	385	struct irq_chip *ic = irq_desc_get_chip(desc);
	386	struct aspeed_sgpio *data = gpiochip_get_data(gc);
dbd1c54f	387	unsigned int i, p;
7db47faa HZ	388	unsigned long reg;
	389
	390	chained_irq_enter(ic, desc);
	391
	392	for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
	393	const struct aspeed_sgpio_bank *bank = &aspeed_sgpio_banks[i];
	394
	395	reg = ioread32(bank_reg(data, bank, reg_irq_status));
	396
dbd1c54f	397	for_each_set_bit(p, &reg, 32)
f6c35df2	398	generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
7db47faa HZ	399	}
	400
	401	chained_irq_exit(ic, desc);
	402	}
	403
7db47faa HZ	404	static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
	405	struct platform_device *pdev)
	406	{
	407	int rc, i;
	408	const struct aspeed_sgpio_bank *bank;
	409	struct gpio_irq_chip *irq;
	410
	411	rc = platform_get_irq(pdev, 0);
	412	if (rc < 0)
	413	return rc;
	414
	415	gpio->irq = rc;
	416
0d311d8b	417	/* Disable IRQ and clear Interrupt status registers for all SGPIO Pins. */
7db47faa HZ	418	for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
	419	bank = &aspeed_sgpio_banks[i];
	420	/* disable irq enable bits */
	421	iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable));
	422	/* clear status bits */
	423	iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status));
	424	}
	425
09ac953b SL	426	gpio->intc.name = dev_name(&pdev->dev);
	427	gpio->intc.irq_ack = aspeed_sgpio_irq_ack;
	428	gpio->intc.irq_mask = aspeed_sgpio_irq_mask;
	429	gpio->intc.irq_unmask = aspeed_sgpio_irq_unmask;
	430	gpio->intc.irq_set_type = aspeed_sgpio_set_type;
	431
7db47faa	432	irq = &gpio->chip.irq;
09ac953b	433	irq->chip = &gpio->intc;
ac67b07e	434	irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask;
7db47faa HZ	435	irq->handler = handle_bad_irq;
	436	irq->default_type = IRQ_TYPE_NONE;
	437	irq->parent_handler = aspeed_sgpio_irq_handler;
	438	irq->parent_handler_data = gpio;
	439	irq->parents = &gpio->irq;
	440	irq->num_parents = 1;
	441
bf0d394e	442	/* Apply default IRQ settings */
7db47faa HZ	443	for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
	444	bank = &aspeed_sgpio_banks[i];
	445	/* set falling or level-low irq */
	446	iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0));
	447	/* trigger type is edge */
	448	iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1));
bf0d394e JK	449	/* single edge trigger */
bf0d394e JK	450	iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type2));
7db47faa HZ	451	}
	452
	453	return 0;
	454	}
	455
e1f85d25 SL	456	static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
	457	.pin_mask = GENMASK(9, 6),
	458	};
	459
8a3581c6 SL	460	static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip,
	461	unsigned int offset, bool enable)
	462	{
	463	struct aspeed_sgpio *gpio = gpiochip_get_data(chip);
	464	unsigned long flags;
	465	void __iomem *reg;
	466	u32 val;
	467
	468	reg = bank_reg(gpio, to_bank(offset), reg_tolerance);
	469
	470	spin_lock_irqsave(&gpio->lock, flags);
	471
	472	val = readl(reg);
	473
	474	if (enable)
	475	val \|= GPIO_BIT(offset);
	476	else
	477	val &= ~GPIO_BIT(offset);
	478
	479	writel(val, reg);
	480
	481	spin_unlock_irqrestore(&gpio->lock, flags);
	482
	483	return 0;
	484	}
	485
	486	static int aspeed_sgpio_set_config(struct gpio_chip *chip, unsigned int offset,
	487	unsigned long config)
	488	{
	489	unsigned long param = pinconf_to_config_param(config);
	490	u32 arg = pinconf_to_config_argument(config);
	491
	492	if (param == PIN_CONFIG_PERSIST_STATE)
	493	return aspeed_sgpio_reset_tolerance(chip, offset, arg);
	494
	495	return -ENOTSUPP;
	496	}
	497
e1f85d25 SL	498	static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata = {
	499	.pin_mask = GENMASK(10, 6),
	500	};
	501
7db47faa	502	static const struct of_device_id aspeed_sgpio_of_table[] = {
e1f85d25 SL	503	{ .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata, },
	504	{ .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata, },
	505	{ .compatible = "aspeed,ast2600-sgpiom", .data = &ast2600_sgpiom_pdata, },
7db47faa HZ	506	{}
	507	};
	508
	509	MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
	510
	511	static int __init aspeed_sgpio_probe(struct platform_device *pdev)
	512	{
e1f85d25 SL	513	u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask;
e1f85d25 SL	514	const struct aspeed_sgpio_pdata *pdata;
7db47faa	515	struct aspeed_sgpio *gpio;
7db47faa	516	unsigned long apb_freq;
e1f85d25	517	int rc;
7db47faa HZ	518
	519	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
	520	if (!gpio)
	521	return -ENOMEM;
	522
	523	gpio->base = devm_platform_ioremap_resource(pdev, 0);
	524	if (IS_ERR(gpio->base))
	525	return PTR_ERR(gpio->base);
	526
e1f85d25 SL	527	pdata = device_get_match_data(&pdev->dev);
	528	if (!pdata)
	529	return -EINVAL;
	530
	531	pin_mask = pdata->pin_mask;
	532
1f857b67	533	rc = device_property_read_u32(&pdev->dev, "ngpios", &nr_gpios);
7db47faa HZ	534	if (rc < 0) {
	535	dev_err(&pdev->dev, "Could not read ngpios property\n");
	536	return -EINVAL;
f43837f4 SL	537	} else if (nr_gpios % 8) {
	538	dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n",
	539	nr_gpios);
7db47faa HZ	540	return -EINVAL;
	541	}
	542
1f857b67	543	rc = device_property_read_u32(&pdev->dev, "bus-frequency", &sgpio_freq);
7db47faa HZ	544	if (rc < 0) {
	545	dev_err(&pdev->dev, "Could not read bus-frequency property\n");
	546	return -EINVAL;
	547	}
	548
	549	gpio->pclk = devm_clk_get(&pdev->dev, NULL);
	550	if (IS_ERR(gpio->pclk)) {
	551	dev_err(&pdev->dev, "devm_clk_get failed\n");
	552	return PTR_ERR(gpio->pclk);
	553	}
	554
	555	apb_freq = clk_get_rate(gpio->pclk);
	556
	557	/*
	558	* From the datasheet,
	559	* SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1)
	560	* period = 2 * (GPIO254[31:16] + 1) / PCLK
	561	* frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK)
	562	* frequency = PCLK / (2 * (GPIO254[31:16] + 1))
	563	* frequency * 2 * (GPIO254[31:16] + 1) = PCLK
	564	* GPIO254[31:16] = PCLK / (frequency * 2) - 1
	565	*/
	566	if (sgpio_freq == 0)
	567	return -EINVAL;
	568
	569	sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1;
	570
	571	if (sgpio_clk_div > (1 << 16) - 1)
	572	return -EINVAL;
	573
e1f85d25 SL	574	gpio_cnt_regval = ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT) & pin_mask;
	575	iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) \| gpio_cnt_regval \|
	576	ASPEED_SGPIO_ENABLE, gpio->base + ASPEED_SGPIO_CTRL);
7db47faa HZ	577
	578	spin_lock_init(&gpio->lock);
	579
	580	gpio->chip.parent = &pdev->dev;
e1f85d25	581	gpio->chip.ngpio = nr_gpios * 2;
ac67b07e	582	gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask;
7db47faa HZ	583	gpio->chip.direction_input = aspeed_sgpio_dir_in;
	584	gpio->chip.direction_output = aspeed_sgpio_dir_out;
	585	gpio->chip.get_direction = aspeed_sgpio_get_direction;
	586	gpio->chip.request = NULL;
	587	gpio->chip.free = NULL;
	588	gpio->chip.get = aspeed_sgpio_get;
	589	gpio->chip.set = aspeed_sgpio_set;
8a3581c6	590	gpio->chip.set_config = aspeed_sgpio_set_config;
7db47faa HZ	591	gpio->chip.label = dev_name(&pdev->dev);
	592	gpio->chip.base = -1;
	593
7db47faa HZ	594	aspeed_sgpio_setup_irqs(gpio, pdev);
	595
	596	rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
	597	if (rc < 0)
	598	return rc;
	599
	600	return 0;
	601	}
	602
	603	static struct platform_driver aspeed_sgpio_driver = {
	604	.driver = {
	605	.name = KBUILD_MODNAME,
	606	.of_match_table = aspeed_sgpio_of_table,
	607	},
	608	};
	609
	610	module_platform_driver_probe(aspeed_sgpio_driver, aspeed_sgpio_probe);
	611	MODULE_DESCRIPTION("Aspeed Serial GPIO Driver");
	612	MODULE_LICENSE("GPL");