[linux-2.6-block.git] / drivers / gpio / gpio-amd8111.c

// SPDX-License-Identifier: GPL-2.0
/*
 * GPIO driver for AMD 8111 south bridges
 *
 * Copyright (c) 2012 Dmitry Eremin-Solenikov
 *
 * Based on the AMD RNG driver:
 * Copyright 2005 (c) MontaVista Software, Inc.
 * with the majority of the code coming from:
 *
 * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
 * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
 *
 * derived from
 *
 * Hardware driver for the AMD 768 Random Number Generator (RNG)
 * (c) Copyright 2001 Red Hat Inc
 *
 * derived from
 *
 * Hardware driver for Intel i810 Random Number Generator (RNG)
 * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
 * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
 */
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/gpio/driver.h>
#include <linux/pci.h>
#include <linux/spinlock.h>

#define PMBASE_OFFSET 0xb0
#define PMBASE_SIZE   0x30

#define AMD_REG_GPIO(i) (0x10 + (i))

#define AMD_GPIO_LTCH_STS	0x40 /* Latch status, w1 */
#define AMD_GPIO_RTIN		0x20 /* Real Time in, ro */
#define AMD_GPIO_DEBOUNCE	0x10 /* Debounce, rw */
#define AMD_GPIO_MODE_MASK	0x0c /* Pin Mode Select, rw */
#define AMD_GPIO_MODE_IN	0x00
#define AMD_GPIO_MODE_OUT	0x04
/* Enable alternative (e.g. clkout, IRQ, etc) function of the pin */
#define AMD_GPIO_MODE_ALTFN	0x08 /* Or 0x09 */
#define AMD_GPIO_X_MASK		0x03 /* In/Out specific, rw */
#define AMD_GPIO_X_IN_ACTIVEHI	0x01 /* Active High */
#define AMD_GPIO_X_IN_LATCH	0x02 /* Latched version is selected */
#define AMD_GPIO_X_OUT_LOW	0x00
#define AMD_GPIO_X_OUT_HI	0x01
#define AMD_GPIO_X_OUT_CLK0	0x02
#define AMD_GPIO_X_OUT_CLK1	0x03

/*
 * Data for PCI driver interface
 *
 * This data only exists for exporting the supported
 * PCI ids via MODULE_DEVICE_TABLE.  We do not actually
 * register a pci_driver, because someone else might one day
 * want to register another driver on the same PCI id.
 */
static const struct pci_device_id pci_tbl[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS), 0 },
	{ 0, },	/* terminate list */
};
MODULE_DEVICE_TABLE(pci, pci_tbl);

struct amd_gpio {
	struct gpio_chip	chip;
	u32			pmbase;
	void __iomem		*pm;
	struct pci_dev		*pdev;
	spinlock_t		lock; /* guards hw registers and orig table */
	u8			orig[32];
};

static int amd_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	struct amd_gpio *agp = gpiochip_get_data(chip);

	agp->orig[offset] = ioread8(agp->pm + AMD_REG_GPIO(offset)) &
		(AMD_GPIO_DEBOUNCE | AMD_GPIO_MODE_MASK | AMD_GPIO_X_MASK);

	dev_dbg(&agp->pdev->dev, "Requested gpio %d, data %x\n", offset, agp->orig[offset]);

	return 0;
}

static void amd_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	struct amd_gpio *agp = gpiochip_get_data(chip);

	dev_dbg(&agp->pdev->dev, "Freed gpio %d, data %x\n", offset, agp->orig[offset]);

	iowrite8(agp->orig[offset], agp->pm + AMD_REG_GPIO(offset));
}

static void amd_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct amd_gpio *agp = gpiochip_get_data(chip);
	u8 temp;
	unsigned long flags;

	spin_lock_irqsave(&agp->lock, flags);
	temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
	temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_OUT | (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW);
	iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
	spin_unlock_irqrestore(&agp->lock, flags);

	dev_dbg(&agp->pdev->dev, "Setting gpio %d, value %d, reg=%02x\n", offset, !!value, temp);
}

static int amd_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct amd_gpio *agp = gpiochip_get_data(chip);
	u8 temp;

	temp = ioread8(agp->pm + AMD_REG_GPIO(offset));

	dev_dbg(&agp->pdev->dev, "Getting gpio %d, reg=%02x\n", offset, temp);

	return (temp & AMD_GPIO_RTIN) ? 1 : 0;
}

static int amd_gpio_dirout(struct gpio_chip *chip, unsigned offset, int value)
{
	struct amd_gpio *agp = gpiochip_get_data(chip);
	u8 temp;
	unsigned long flags;

	spin_lock_irqsave(&agp->lock, flags);
	temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
	temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_OUT | (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW);
	iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
	spin_unlock_irqrestore(&agp->lock, flags);

	dev_dbg(&agp->pdev->dev, "Dirout gpio %d, value %d, reg=%02x\n", offset, !!value, temp);

	return 0;
}

static int amd_gpio_dirin(struct gpio_chip *chip, unsigned offset)
{
	struct amd_gpio *agp = gpiochip_get_data(chip);
	u8 temp;
	unsigned long flags;

	spin_lock_irqsave(&agp->lock, flags);
	temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
	temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_IN;
	iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
	spin_unlock_irqrestore(&agp->lock, flags);

	dev_dbg(&agp->pdev->dev, "Dirin gpio %d, reg=%02x\n", offset, temp);

	return 0;
}

static struct amd_gpio gp = {
	.chip = {
		.label		= "AMD GPIO",
		.owner		= THIS_MODULE,
		.base		= -1,
		.ngpio		= 32,
		.request	= amd_gpio_request,
		.free		= amd_gpio_free,
		.set		= amd_gpio_set,
		.get		= amd_gpio_get,
		.direction_output = amd_gpio_dirout,
		.direction_input = amd_gpio_dirin,
	},
};

static int __init amd_gpio_init(void)
{
	int err = -ENODEV;
	struct pci_dev *pdev = NULL;
	const struct pci_device_id *ent;

	/* We look for our device - AMD South Bridge
	 * I don't know about a system with two such bridges,
	 * so we can assume that there is max. one device.
	 *
	 * We can't use plain pci_driver mechanism,
	 * as the device is really a multiple function device,
	 * main driver that binds to the pci_device is an smbus
	 * driver and have to find & bind to the device this way.
	 */
	for_each_pci_dev(pdev) {
		ent = pci_match_id(pci_tbl, pdev);
		if (ent)
			goto found;
	}
	/* Device not found. */
	goto out;

found:
	err = pci_read_config_dword(pdev, 0x58, &gp.pmbase);
	if (err)
		goto out;
	err = -EIO;
	gp.pmbase &= 0x0000FF00;
	if (gp.pmbase == 0)
		goto out;
	if (!devm_request_region(&pdev->dev, gp.pmbase + PMBASE_OFFSET,
		PMBASE_SIZE, "AMD GPIO")) {
		dev_err(&pdev->dev, "AMD GPIO region 0x%x already in use!\n",
			gp.pmbase + PMBASE_OFFSET);
		err = -EBUSY;
		goto out;
	}
	gp.pm = ioport_map(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE);
	if (!gp.pm) {
		dev_err(&pdev->dev, "Couldn't map io port into io memory\n");
		err = -ENOMEM;
		goto out;
	}
	gp.pdev = pdev;
	gp.chip.parent = &pdev->dev;

	spin_lock_init(&gp.lock);

	dev_info(&pdev->dev, "AMD-8111 GPIO detected\n");
	err = gpiochip_add_data(&gp.chip, &gp);
	if (err) {
		dev_err(&pdev->dev, "GPIO registering failed (%d)\n", err);
		ioport_unmap(gp.pm);
		goto out;
	}
	return 0;

out:
	pci_dev_put(pdev);
	return err;
}

static void __exit amd_gpio_exit(void)
{
	gpiochip_remove(&gp.chip);
	ioport_unmap(gp.pm);
	pci_dev_put(gp.pdev);
}

module_init(amd_gpio_init);
module_exit(amd_gpio_exit);

MODULE_AUTHOR("The Linux Kernel team");
MODULE_DESCRIPTION("GPIO driver for AMD chipsets");
MODULE_LICENSE("GPL");
Commit	Line	Data
37ddba02	1	// SPDX-License-Identifier: GPL-2.0
f942a7de DES	2	/*
	3	* GPIO driver for AMD 8111 south bridges
	4	*
	5	* Copyright (c) 2012 Dmitry Eremin-Solenikov
	6	*
	7	* Based on the AMD RNG driver:
	8	* Copyright 2005 (c) MontaVista Software, Inc.
	9	* with the majority of the code coming from:
	10	*
	11	* Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
	12	* (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
	13	*
	14	* derived from
	15	*
	16	* Hardware driver for the AMD 768 Random Number Generator (RNG)
	17	* (c) Copyright 2001 Red Hat Inc
	18	*
	19	* derived from
	20	*
	21	* Hardware driver for Intel i810 Random Number Generator (RNG)
	22	* Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
	23	* Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
f942a7de	24	*/
35568c40	25	#include <linux/ioport.h>
f942a7de DES	26	#include <linux/module.h>
f942a7de DES	27	#include <linux/kernel.h>
3708c665	28	#include <linux/gpio/driver.h>
f942a7de DES	29	#include <linux/pci.h>
	30	#include <linux/spinlock.h>
	31
	32	#define PMBASE_OFFSET 0xb0
	33	#define PMBASE_SIZE 0x30
	34
	35	#define AMD_REG_GPIO(i) (0x10 + (i))
	36
	37	#define AMD_GPIO_LTCH_STS 0x40 /* Latch status, w1 */
	38	#define AMD_GPIO_RTIN 0x20 /* Real Time in, ro */
	39	#define AMD_GPIO_DEBOUNCE 0x10 /* Debounce, rw */
	40	#define AMD_GPIO_MODE_MASK 0x0c /* Pin Mode Select, rw */
	41	#define AMD_GPIO_MODE_IN 0x00
	42	#define AMD_GPIO_MODE_OUT 0x04
	43	/* Enable alternative (e.g. clkout, IRQ, etc) function of the pin */
	44	#define AMD_GPIO_MODE_ALTFN 0x08 /* Or 0x09 */
	45	#define AMD_GPIO_X_MASK 0x03 /* In/Out specific, rw */
	46	#define AMD_GPIO_X_IN_ACTIVEHI 0x01 /* Active High */
	47	#define AMD_GPIO_X_IN_LATCH 0x02 /* Latched version is selected */
	48	#define AMD_GPIO_X_OUT_LOW 0x00
	49	#define AMD_GPIO_X_OUT_HI 0x01
	50	#define AMD_GPIO_X_OUT_CLK0 0x02
	51	#define AMD_GPIO_X_OUT_CLK1 0x03
	52
	53	/*
	54	* Data for PCI driver interface
	55	*
	56	* This data only exists for exporting the supported
	57	* PCI ids via MODULE_DEVICE_TABLE. We do not actually
	58	* register a pci_driver, because someone else might one day
	59	* want to register another driver on the same PCI id.
	60	*/
14f4a883	61	static const struct pci_device_id pci_tbl[] = {
f942a7de DES	62	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS), 0 },
	63	{ 0, }, /* terminate list */
	64	};
	65	MODULE_DEVICE_TABLE(pci, pci_tbl);
	66
	67	struct amd_gpio {
	68	struct gpio_chip chip;
	69	u32 pmbase;
	70	void __iomem *pm;
	71	struct pci_dev *pdev;
	72	spinlock_t lock; /* guards hw registers and orig table */
	73	u8 orig[32];
	74	};
	75
f942a7de DES	76	static int amd_gpio_request(struct gpio_chip *chip, unsigned offset)
f942a7de DES	77	{
57683ec2	78	struct amd_gpio *agp = gpiochip_get_data(chip);
f942a7de DES	79
	80	agp->orig[offset] = ioread8(agp->pm + AMD_REG_GPIO(offset)) &
	81	(AMD_GPIO_DEBOUNCE \| AMD_GPIO_MODE_MASK \| AMD_GPIO_X_MASK);
	82
	83	dev_dbg(&agp->pdev->dev, "Requested gpio %d, data %x\n", offset, agp->orig[offset]);
	84
	85	return 0;
	86	}
	87
	88	static void amd_gpio_free(struct gpio_chip *chip, unsigned offset)
	89	{
57683ec2	90	struct amd_gpio *agp = gpiochip_get_data(chip);
f942a7de DES	91
	92	dev_dbg(&agp->pdev->dev, "Freed gpio %d, data %x\n", offset, agp->orig[offset]);
	93
	94	iowrite8(agp->orig[offset], agp->pm + AMD_REG_GPIO(offset));
	95	}
	96
	97	static void amd_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	98	{
57683ec2	99	struct amd_gpio *agp = gpiochip_get_data(chip);
f942a7de DES	100	u8 temp;
	101	unsigned long flags;
	102
	103	spin_lock_irqsave(&agp->lock, flags);
	104	temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
	105	temp = (temp & AMD_GPIO_DEBOUNCE) \| AMD_GPIO_MODE_OUT \| (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW);
	106	iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
	107	spin_unlock_irqrestore(&agp->lock, flags);
	108
	109	dev_dbg(&agp->pdev->dev, "Setting gpio %d, value %d, reg=%02x\n", offset, !!value, temp);
	110	}
	111
	112	static int amd_gpio_get(struct gpio_chip *chip, unsigned offset)
	113	{
57683ec2	114	struct amd_gpio *agp = gpiochip_get_data(chip);
f942a7de DES	115	u8 temp;
	116
	117	temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
	118
	119	dev_dbg(&agp->pdev->dev, "Getting gpio %d, reg=%02x\n", offset, temp);
	120
	121	return (temp & AMD_GPIO_RTIN) ? 1 : 0;
	122	}
	123
	124	static int amd_gpio_dirout(struct gpio_chip *chip, unsigned offset, int value)
	125	{
57683ec2	126	struct amd_gpio *agp = gpiochip_get_data(chip);
f942a7de DES	127	u8 temp;
	128	unsigned long flags;
	129
	130	spin_lock_irqsave(&agp->lock, flags);
	131	temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
	132	temp = (temp & AMD_GPIO_DEBOUNCE) \| AMD_GPIO_MODE_OUT \| (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW);
	133	iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
	134	spin_unlock_irqrestore(&agp->lock, flags);
	135
	136	dev_dbg(&agp->pdev->dev, "Dirout gpio %d, value %d, reg=%02x\n", offset, !!value, temp);
	137
	138	return 0;
	139	}
	140
	141	static int amd_gpio_dirin(struct gpio_chip *chip, unsigned offset)
	142	{
57683ec2	143	struct amd_gpio *agp = gpiochip_get_data(chip);
f942a7de DES	144	u8 temp;
	145	unsigned long flags;
	146
	147	spin_lock_irqsave(&agp->lock, flags);
	148	temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
	149	temp = (temp & AMD_GPIO_DEBOUNCE) \| AMD_GPIO_MODE_IN;
	150	iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
	151	spin_unlock_irqrestore(&agp->lock, flags);
	152
	153	dev_dbg(&agp->pdev->dev, "Dirin gpio %d, reg=%02x\n", offset, temp);
	154
	155	return 0;
	156	}
	157
	158	static struct amd_gpio gp = {
	159	.chip = {
	160	.label = "AMD GPIO",
	161	.owner = THIS_MODULE,
	162	.base = -1,
	163	.ngpio = 32,
	164	.request = amd_gpio_request,
	165	.free = amd_gpio_free,
	166	.set = amd_gpio_set,
	167	.get = amd_gpio_get,
	168	.direction_output = amd_gpio_dirout,
	169	.direction_input = amd_gpio_dirin,
	170	},
	171	};
	172
	173	static int __init amd_gpio_init(void)
	174	{
	175	int err = -ENODEV;
	176	struct pci_dev *pdev = NULL;
	177	const struct pci_device_id *ent;
	178
f942a7de DES	179	/* We look for our device - AMD South Bridge
	180	* I don't know about a system with two such bridges,
	181	* so we can assume that there is max. one device.
	182	*
	183	* We can't use plain pci_driver mechanism,
	184	* as the device is really a multiple function device,
	185	* main driver that binds to the pci_device is an smbus
	186	* driver and have to find & bind to the device this way.
	187	*/
	188	for_each_pci_dev(pdev) {
	189	ent = pci_match_id(pci_tbl, pdev);
	190	if (ent)
	191	goto found;
	192	}
	193	/* Device not found. */
	194	goto out;
	195
	196	found:
	197	err = pci_read_config_dword(pdev, 0x58, &gp.pmbase);
	198	if (err)
	199	goto out;
	200	err = -EIO;
	201	gp.pmbase &= 0x0000FF00;
	202	if (gp.pmbase == 0)
	203	goto out;
35568c40 WBG	204	if (!devm_request_region(&pdev->dev, gp.pmbase + PMBASE_OFFSET,
35568c40 WBG	205	PMBASE_SIZE, "AMD GPIO")) {
f942a7de DES	206	dev_err(&pdev->dev, "AMD GPIO region 0x%x already in use!\n",
	207	gp.pmbase + PMBASE_OFFSET);
	208	err = -EBUSY;
	209	goto out;
	210	}
	211	gp.pm = ioport_map(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE);
ffe4770b VB	212	if (!gp.pm) {
	213	dev_err(&pdev->dev, "Couldn't map io port into io memory\n");
	214	err = -ENOMEM;
	215	goto out;
	216	}
f942a7de	217	gp.pdev = pdev;
58383c78	218	gp.chip.parent = &pdev->dev;
f942a7de DES	219
	220	spin_lock_init(&gp.lock);
	221
a922a244	222	dev_info(&pdev->dev, "AMD-8111 GPIO detected\n");
57683ec2	223	err = gpiochip_add_data(&gp.chip, &gp);
f942a7de	224	if (err) {
a922a244	225	dev_err(&pdev->dev, "GPIO registering failed (%d)\n", err);
8fb87deb	226	ioport_unmap(gp.pm);
f942a7de DES	227	goto out;
f942a7de DES	228	}
45fecdb9 XW	229	return 0;
45fecdb9 XW	230
f942a7de	231	out:
45fecdb9	232	pci_dev_put(pdev);
f942a7de DES	233	return err;
	234	}
	235
	236	static void __exit amd_gpio_exit(void)
	237	{
9f5132ae	238	gpiochip_remove(&gp.chip);
f942a7de	239	ioport_unmap(gp.pm);
45fecdb9	240	pci_dev_put(gp.pdev);
f942a7de DES	241	}
	242
	243	module_init(amd_gpio_init);
	244	module_exit(amd_gpio_exit);
	245
	246	MODULE_AUTHOR("The Linux Kernel team");
	247	MODULE_DESCRIPTION("GPIO driver for AMD chipsets");
	248	MODULE_LICENSE("GPL");