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5e969a40 TR |
1 | /* |
2 | * Copyright (C) 2011-2012 Avionic Design GmbH | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <linux/gpio.h> | |
10 | #include <linux/i2c.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/irqdomain.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/of_irq.h> | |
15 | #include <linux/seq_file.h> | |
16 | #include <linux/slab.h> | |
17 | ||
18 | #define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift) | |
19 | #define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift) | |
20 | #define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift) | |
21 | #define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift) | |
22 | #define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift) | |
23 | ||
24 | struct adnp { | |
25 | struct i2c_client *client; | |
26 | struct gpio_chip gpio; | |
27 | unsigned int reg_shift; | |
28 | ||
29 | struct mutex i2c_lock; | |
30 | ||
31 | struct irq_domain *domain; | |
32 | struct mutex irq_lock; | |
33 | ||
34 | u8 *irq_enable; | |
35 | u8 *irq_level; | |
36 | u8 *irq_rise; | |
37 | u8 *irq_fall; | |
38 | u8 *irq_high; | |
39 | u8 *irq_low; | |
40 | }; | |
41 | ||
42 | static inline struct adnp *to_adnp(struct gpio_chip *chip) | |
43 | { | |
44 | return container_of(chip, struct adnp, gpio); | |
45 | } | |
46 | ||
47 | static int adnp_read(struct adnp *adnp, unsigned offset, uint8_t *value) | |
48 | { | |
49 | int err; | |
50 | ||
51 | err = i2c_smbus_read_byte_data(adnp->client, offset); | |
52 | if (err < 0) { | |
53 | dev_err(adnp->gpio.dev, "%s failed: %d\n", | |
54 | "i2c_smbus_read_byte_data()", err); | |
55 | return err; | |
56 | } | |
57 | ||
58 | *value = err; | |
59 | return 0; | |
60 | } | |
61 | ||
62 | static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value) | |
63 | { | |
64 | int err; | |
65 | ||
66 | err = i2c_smbus_write_byte_data(adnp->client, offset, value); | |
67 | if (err < 0) { | |
68 | dev_err(adnp->gpio.dev, "%s failed: %d\n", | |
69 | "i2c_smbus_write_byte_data()", err); | |
70 | return err; | |
71 | } | |
72 | ||
73 | return 0; | |
74 | } | |
75 | ||
76 | static int adnp_gpio_get(struct gpio_chip *chip, unsigned offset) | |
77 | { | |
78 | struct adnp *adnp = to_adnp(chip); | |
79 | unsigned int reg = offset >> adnp->reg_shift; | |
80 | unsigned int pos = offset & 7; | |
81 | u8 value; | |
82 | int err; | |
83 | ||
84 | err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value); | |
85 | if (err < 0) | |
86 | return err; | |
87 | ||
88 | return (value & BIT(pos)) ? 1 : 0; | |
89 | } | |
90 | ||
91 | static void __adnp_gpio_set(struct adnp *adnp, unsigned offset, int value) | |
92 | { | |
93 | unsigned int reg = offset >> adnp->reg_shift; | |
94 | unsigned int pos = offset & 7; | |
95 | int err; | |
96 | u8 val; | |
97 | ||
98 | err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val); | |
99 | if (err < 0) | |
100 | return; | |
101 | ||
102 | if (value) | |
103 | val |= BIT(pos); | |
104 | else | |
105 | val &= ~BIT(pos); | |
106 | ||
107 | adnp_write(adnp, GPIO_PLR(adnp) + reg, val); | |
108 | } | |
109 | ||
110 | static void adnp_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
111 | { | |
112 | struct adnp *adnp = to_adnp(chip); | |
113 | ||
114 | mutex_lock(&adnp->i2c_lock); | |
115 | __adnp_gpio_set(adnp, offset, value); | |
116 | mutex_unlock(&adnp->i2c_lock); | |
117 | } | |
118 | ||
119 | static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
120 | { | |
121 | struct adnp *adnp = to_adnp(chip); | |
122 | unsigned int reg = offset >> adnp->reg_shift; | |
123 | unsigned int pos = offset & 7; | |
124 | u8 value; | |
125 | int err; | |
126 | ||
127 | mutex_lock(&adnp->i2c_lock); | |
128 | ||
129 | err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value); | |
130 | if (err < 0) | |
131 | goto out; | |
132 | ||
133 | value &= ~BIT(pos); | |
134 | ||
135 | err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value); | |
136 | if (err < 0) | |
137 | goto out; | |
138 | ||
139 | err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value); | |
140 | if (err < 0) | |
141 | goto out; | |
142 | ||
143 | if (err & BIT(pos)) | |
144 | err = -EACCES; | |
145 | ||
146 | err = 0; | |
147 | ||
148 | out: | |
149 | mutex_unlock(&adnp->i2c_lock); | |
150 | return err; | |
151 | } | |
152 | ||
153 | static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |
154 | int value) | |
155 | { | |
156 | struct adnp *adnp = to_adnp(chip); | |
157 | unsigned int reg = offset >> adnp->reg_shift; | |
158 | unsigned int pos = offset & 7; | |
159 | int err; | |
160 | u8 val; | |
161 | ||
162 | mutex_lock(&adnp->i2c_lock); | |
163 | ||
164 | err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val); | |
165 | if (err < 0) | |
166 | goto out; | |
167 | ||
168 | val |= BIT(pos); | |
169 | ||
170 | err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val); | |
171 | if (err < 0) | |
172 | goto out; | |
173 | ||
174 | err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val); | |
175 | if (err < 0) | |
176 | goto out; | |
177 | ||
178 | if (!(val & BIT(pos))) { | |
179 | err = -EPERM; | |
180 | goto out; | |
181 | } | |
182 | ||
183 | __adnp_gpio_set(adnp, offset, value); | |
184 | err = 0; | |
185 | ||
186 | out: | |
187 | mutex_unlock(&adnp->i2c_lock); | |
188 | return err; | |
189 | } | |
190 | ||
191 | static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
192 | { | |
193 | struct adnp *adnp = to_adnp(chip); | |
194 | unsigned int num_regs = 1 << adnp->reg_shift, i, j; | |
195 | int err; | |
196 | ||
197 | for (i = 0; i < num_regs; i++) { | |
198 | u8 ddr, plr, ier, isr; | |
199 | ||
200 | mutex_lock(&adnp->i2c_lock); | |
201 | ||
202 | err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr); | |
203 | if (err < 0) { | |
204 | mutex_unlock(&adnp->i2c_lock); | |
205 | return; | |
206 | } | |
207 | ||
208 | err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr); | |
209 | if (err < 0) { | |
210 | mutex_unlock(&adnp->i2c_lock); | |
211 | return; | |
212 | } | |
213 | ||
214 | err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier); | |
215 | if (err < 0) { | |
216 | mutex_unlock(&adnp->i2c_lock); | |
217 | return; | |
218 | } | |
219 | ||
220 | err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr); | |
221 | if (err < 0) { | |
222 | mutex_unlock(&adnp->i2c_lock); | |
223 | return; | |
224 | } | |
225 | ||
226 | mutex_unlock(&adnp->i2c_lock); | |
227 | ||
228 | for (j = 0; j < 8; j++) { | |
229 | unsigned int bit = (i << adnp->reg_shift) + j; | |
230 | const char *direction = "input "; | |
231 | const char *level = "low "; | |
232 | const char *interrupt = "disabled"; | |
233 | const char *pending = ""; | |
234 | ||
235 | if (ddr & BIT(j)) | |
236 | direction = "output"; | |
237 | ||
238 | if (plr & BIT(j)) | |
239 | level = "high"; | |
240 | ||
241 | if (ier & BIT(j)) | |
242 | interrupt = "enabled "; | |
243 | ||
244 | if (isr & BIT(j)) | |
245 | pending = "pending"; | |
246 | ||
247 | seq_printf(s, "%2u: %s %s IRQ %s %s\n", bit, | |
248 | direction, level, interrupt, pending); | |
249 | } | |
250 | } | |
251 | } | |
252 | ||
253 | static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios) | |
254 | { | |
255 | struct gpio_chip *chip = &adnp->gpio; | |
256 | ||
257 | adnp->reg_shift = get_count_order(num_gpios) - 3; | |
258 | ||
259 | chip->direction_input = adnp_gpio_direction_input; | |
260 | chip->direction_output = adnp_gpio_direction_output; | |
261 | chip->get = adnp_gpio_get; | |
262 | chip->set = adnp_gpio_set; | |
9fb1f39e | 263 | chip->can_sleep = true; |
5e969a40 TR |
264 | |
265 | if (IS_ENABLED(CONFIG_DEBUG_FS)) | |
266 | chip->dbg_show = adnp_gpio_dbg_show; | |
267 | ||
268 | chip->base = -1; | |
269 | chip->ngpio = num_gpios; | |
270 | chip->label = adnp->client->name; | |
271 | chip->dev = &adnp->client->dev; | |
272 | chip->of_node = chip->dev->of_node; | |
273 | chip->owner = THIS_MODULE; | |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
278 | static irqreturn_t adnp_irq(int irq, void *data) | |
279 | { | |
280 | struct adnp *adnp = data; | |
281 | unsigned int num_regs, i; | |
282 | ||
283 | num_regs = 1 << adnp->reg_shift; | |
284 | ||
285 | for (i = 0; i < num_regs; i++) { | |
286 | unsigned int base = i << adnp->reg_shift, bit; | |
287 | u8 changed, level, isr, ier; | |
288 | unsigned long pending; | |
289 | int err; | |
290 | ||
291 | mutex_lock(&adnp->i2c_lock); | |
292 | ||
293 | err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level); | |
294 | if (err < 0) { | |
295 | mutex_unlock(&adnp->i2c_lock); | |
296 | continue; | |
297 | } | |
298 | ||
299 | err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr); | |
300 | if (err < 0) { | |
301 | mutex_unlock(&adnp->i2c_lock); | |
302 | continue; | |
303 | } | |
304 | ||
305 | err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier); | |
306 | if (err < 0) { | |
307 | mutex_unlock(&adnp->i2c_lock); | |
308 | continue; | |
309 | } | |
310 | ||
311 | mutex_unlock(&adnp->i2c_lock); | |
312 | ||
313 | /* determine pins that changed levels */ | |
314 | changed = level ^ adnp->irq_level[i]; | |
315 | ||
316 | /* compute edge-triggered interrupts */ | |
317 | pending = changed & ((adnp->irq_fall[i] & ~level) | | |
318 | (adnp->irq_rise[i] & level)); | |
319 | ||
320 | /* add in level-triggered interrupts */ | |
321 | pending |= (adnp->irq_high[i] & level) | | |
322 | (adnp->irq_low[i] & ~level); | |
323 | ||
324 | /* mask out non-pending and disabled interrupts */ | |
325 | pending &= isr & ier; | |
326 | ||
327 | for_each_set_bit(bit, &pending, 8) { | |
472f95b9 LW |
328 | unsigned int child_irq; |
329 | child_irq = irq_find_mapping(adnp->domain, base + bit); | |
330 | handle_nested_irq(child_irq); | |
5e969a40 TR |
331 | } |
332 | } | |
333 | ||
334 | return IRQ_HANDLED; | |
335 | } | |
336 | ||
337 | static int adnp_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
338 | { | |
339 | struct adnp *adnp = to_adnp(chip); | |
340 | return irq_create_mapping(adnp->domain, offset); | |
341 | } | |
342 | ||
343 | static void adnp_irq_mask(struct irq_data *data) | |
344 | { | |
345 | struct adnp *adnp = irq_data_get_irq_chip_data(data); | |
346 | unsigned int reg = data->hwirq >> adnp->reg_shift; | |
347 | unsigned int pos = data->hwirq & 7; | |
348 | ||
349 | adnp->irq_enable[reg] &= ~BIT(pos); | |
350 | } | |
351 | ||
352 | static void adnp_irq_unmask(struct irq_data *data) | |
353 | { | |
354 | struct adnp *adnp = irq_data_get_irq_chip_data(data); | |
355 | unsigned int reg = data->hwirq >> adnp->reg_shift; | |
356 | unsigned int pos = data->hwirq & 7; | |
357 | ||
358 | adnp->irq_enable[reg] |= BIT(pos); | |
359 | } | |
360 | ||
361 | static int adnp_irq_set_type(struct irq_data *data, unsigned int type) | |
362 | { | |
363 | struct adnp *adnp = irq_data_get_irq_chip_data(data); | |
364 | unsigned int reg = data->hwirq >> adnp->reg_shift; | |
365 | unsigned int pos = data->hwirq & 7; | |
366 | ||
367 | if (type & IRQ_TYPE_EDGE_RISING) | |
368 | adnp->irq_rise[reg] |= BIT(pos); | |
369 | else | |
370 | adnp->irq_rise[reg] &= ~BIT(pos); | |
371 | ||
372 | if (type & IRQ_TYPE_EDGE_FALLING) | |
373 | adnp->irq_fall[reg] |= BIT(pos); | |
374 | else | |
375 | adnp->irq_fall[reg] &= ~BIT(pos); | |
376 | ||
377 | if (type & IRQ_TYPE_LEVEL_HIGH) | |
378 | adnp->irq_high[reg] |= BIT(pos); | |
379 | else | |
380 | adnp->irq_high[reg] &= ~BIT(pos); | |
381 | ||
382 | if (type & IRQ_TYPE_LEVEL_LOW) | |
383 | adnp->irq_low[reg] |= BIT(pos); | |
384 | else | |
385 | adnp->irq_low[reg] &= ~BIT(pos); | |
386 | ||
387 | return 0; | |
388 | } | |
389 | ||
390 | static void adnp_irq_bus_lock(struct irq_data *data) | |
391 | { | |
392 | struct adnp *adnp = irq_data_get_irq_chip_data(data); | |
393 | ||
394 | mutex_lock(&adnp->irq_lock); | |
395 | } | |
396 | ||
397 | static void adnp_irq_bus_unlock(struct irq_data *data) | |
398 | { | |
399 | struct adnp *adnp = irq_data_get_irq_chip_data(data); | |
400 | unsigned int num_regs = 1 << adnp->reg_shift, i; | |
401 | ||
402 | mutex_lock(&adnp->i2c_lock); | |
403 | ||
404 | for (i = 0; i < num_regs; i++) | |
405 | adnp_write(adnp, GPIO_IER(adnp) + i, adnp->irq_enable[i]); | |
406 | ||
407 | mutex_unlock(&adnp->i2c_lock); | |
408 | mutex_unlock(&adnp->irq_lock); | |
409 | } | |
410 | ||
f41cd3c2 LW |
411 | static unsigned int adnp_irq_startup(struct irq_data *data) |
412 | { | |
413 | struct adnp *adnp = irq_data_get_irq_chip_data(data); | |
414 | ||
415 | if (gpio_lock_as_irq(&adnp->gpio, data->hwirq)) | |
416 | dev_err(adnp->gpio.dev, | |
417 | "unable to lock HW IRQ %lu for IRQ\n", | |
418 | data->hwirq); | |
419 | /* Satisfy the .enable semantics by unmasking the line */ | |
420 | adnp_irq_unmask(data); | |
421 | return 0; | |
422 | } | |
423 | ||
424 | static void adnp_irq_shutdown(struct irq_data *data) | |
425 | { | |
426 | struct adnp *adnp = irq_data_get_irq_chip_data(data); | |
427 | ||
428 | adnp_irq_mask(data); | |
429 | gpio_unlock_as_irq(&adnp->gpio, data->hwirq); | |
430 | } | |
431 | ||
5e969a40 TR |
432 | static struct irq_chip adnp_irq_chip = { |
433 | .name = "gpio-adnp", | |
434 | .irq_mask = adnp_irq_mask, | |
435 | .irq_unmask = adnp_irq_unmask, | |
436 | .irq_set_type = adnp_irq_set_type, | |
437 | .irq_bus_lock = adnp_irq_bus_lock, | |
438 | .irq_bus_sync_unlock = adnp_irq_bus_unlock, | |
f41cd3c2 LW |
439 | .irq_startup = adnp_irq_startup, |
440 | .irq_shutdown = adnp_irq_shutdown, | |
5e969a40 TR |
441 | }; |
442 | ||
443 | static int adnp_irq_map(struct irq_domain *domain, unsigned int irq, | |
444 | irq_hw_number_t hwirq) | |
445 | { | |
446 | irq_set_chip_data(irq, domain->host_data); | |
447 | irq_set_chip(irq, &adnp_irq_chip); | |
448 | irq_set_nested_thread(irq, true); | |
449 | ||
450 | #ifdef CONFIG_ARM | |
451 | set_irq_flags(irq, IRQF_VALID); | |
452 | #else | |
453 | irq_set_noprobe(irq); | |
454 | #endif | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
459 | static const struct irq_domain_ops adnp_irq_domain_ops = { | |
460 | .map = adnp_irq_map, | |
461 | .xlate = irq_domain_xlate_twocell, | |
462 | }; | |
463 | ||
464 | static int adnp_irq_setup(struct adnp *adnp) | |
465 | { | |
466 | unsigned int num_regs = 1 << adnp->reg_shift, i; | |
467 | struct gpio_chip *chip = &adnp->gpio; | |
468 | int err; | |
469 | ||
470 | mutex_init(&adnp->irq_lock); | |
471 | ||
472 | /* | |
473 | * Allocate memory to keep track of the current level and trigger | |
474 | * modes of the interrupts. To avoid multiple allocations, a single | |
475 | * large buffer is allocated and pointers are setup to point at the | |
476 | * corresponding offsets. For consistency, the layout of the buffer | |
477 | * is chosen to match the register layout of the hardware in that | |
478 | * each segment contains the corresponding bits for all interrupts. | |
479 | */ | |
480 | adnp->irq_enable = devm_kzalloc(chip->dev, num_regs * 6, GFP_KERNEL); | |
481 | if (!adnp->irq_enable) | |
482 | return -ENOMEM; | |
483 | ||
484 | adnp->irq_level = adnp->irq_enable + (num_regs * 1); | |
485 | adnp->irq_rise = adnp->irq_enable + (num_regs * 2); | |
486 | adnp->irq_fall = adnp->irq_enable + (num_regs * 3); | |
487 | adnp->irq_high = adnp->irq_enable + (num_regs * 4); | |
488 | adnp->irq_low = adnp->irq_enable + (num_regs * 5); | |
489 | ||
490 | for (i = 0; i < num_regs; i++) { | |
491 | /* | |
492 | * Read the initial level of all pins to allow the emulation | |
493 | * of edge triggered interrupts. | |
494 | */ | |
495 | err = adnp_read(adnp, GPIO_PLR(adnp) + i, &adnp->irq_level[i]); | |
496 | if (err < 0) | |
497 | return err; | |
498 | ||
499 | /* disable all interrupts */ | |
500 | err = adnp_write(adnp, GPIO_IER(adnp) + i, 0); | |
501 | if (err < 0) | |
502 | return err; | |
503 | ||
504 | adnp->irq_enable[i] = 0x00; | |
505 | } | |
506 | ||
507 | adnp->domain = irq_domain_add_linear(chip->of_node, chip->ngpio, | |
508 | &adnp_irq_domain_ops, adnp); | |
509 | ||
510 | err = request_threaded_irq(adnp->client->irq, NULL, adnp_irq, | |
511 | IRQF_TRIGGER_RISING | IRQF_ONESHOT, | |
512 | dev_name(chip->dev), adnp); | |
513 | if (err != 0) { | |
514 | dev_err(chip->dev, "can't request IRQ#%d: %d\n", | |
515 | adnp->client->irq, err); | |
5b21533b | 516 | return err; |
5e969a40 TR |
517 | } |
518 | ||
519 | chip->to_irq = adnp_gpio_to_irq; | |
520 | return 0; | |
5e969a40 TR |
521 | } |
522 | ||
523 | static void adnp_irq_teardown(struct adnp *adnp) | |
524 | { | |
525 | unsigned int irq, i; | |
526 | ||
527 | free_irq(adnp->client->irq, adnp); | |
528 | ||
529 | for (i = 0; i < adnp->gpio.ngpio; i++) { | |
530 | irq = irq_find_mapping(adnp->domain, i); | |
531 | if (irq > 0) | |
532 | irq_dispose_mapping(irq); | |
533 | } | |
534 | ||
535 | irq_domain_remove(adnp->domain); | |
536 | } | |
537 | ||
3836309d | 538 | static int adnp_i2c_probe(struct i2c_client *client, |
5e969a40 TR |
539 | const struct i2c_device_id *id) |
540 | { | |
541 | struct device_node *np = client->dev.of_node; | |
542 | struct adnp *adnp; | |
543 | u32 num_gpios; | |
544 | int err; | |
545 | ||
546 | err = of_property_read_u32(np, "nr-gpios", &num_gpios); | |
547 | if (err < 0) | |
548 | return err; | |
549 | ||
550 | client->irq = irq_of_parse_and_map(np, 0); | |
551 | if (!client->irq) | |
552 | return -EPROBE_DEFER; | |
553 | ||
554 | adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL); | |
555 | if (!adnp) | |
556 | return -ENOMEM; | |
557 | ||
558 | mutex_init(&adnp->i2c_lock); | |
559 | adnp->client = client; | |
560 | ||
561 | err = adnp_gpio_setup(adnp, num_gpios); | |
562 | if (err < 0) | |
563 | return err; | |
564 | ||
565 | if (of_find_property(np, "interrupt-controller", NULL)) { | |
566 | err = adnp_irq_setup(adnp); | |
567 | if (err < 0) | |
568 | goto teardown; | |
569 | } | |
570 | ||
571 | err = gpiochip_add(&adnp->gpio); | |
572 | if (err < 0) | |
573 | goto teardown; | |
574 | ||
575 | i2c_set_clientdata(client, adnp); | |
576 | return 0; | |
577 | ||
578 | teardown: | |
579 | if (of_find_property(np, "interrupt-controller", NULL)) | |
580 | adnp_irq_teardown(adnp); | |
581 | ||
582 | return err; | |
583 | } | |
584 | ||
206210ce | 585 | static int adnp_i2c_remove(struct i2c_client *client) |
5e969a40 TR |
586 | { |
587 | struct adnp *adnp = i2c_get_clientdata(client); | |
588 | struct device_node *np = client->dev.of_node; | |
589 | int err; | |
590 | ||
591 | err = gpiochip_remove(&adnp->gpio); | |
592 | if (err < 0) { | |
593 | dev_err(&client->dev, "%s failed: %d\n", "gpiochip_remove()", | |
594 | err); | |
595 | return err; | |
596 | } | |
597 | ||
598 | if (of_find_property(np, "interrupt-controller", NULL)) | |
599 | adnp_irq_teardown(adnp); | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
b5ba78de | 604 | static const struct i2c_device_id adnp_i2c_id[] = { |
5e969a40 TR |
605 | { "gpio-adnp" }, |
606 | { }, | |
607 | }; | |
608 | MODULE_DEVICE_TABLE(i2c, adnp_i2c_id); | |
609 | ||
b5ba78de | 610 | static const struct of_device_id adnp_of_match[] = { |
5e969a40 TR |
611 | { .compatible = "ad,gpio-adnp", }, |
612 | { }, | |
613 | }; | |
614 | MODULE_DEVICE_TABLE(of, adnp_of_match); | |
615 | ||
616 | static struct i2c_driver adnp_i2c_driver = { | |
617 | .driver = { | |
618 | .name = "gpio-adnp", | |
619 | .owner = THIS_MODULE, | |
83924fb3 | 620 | .of_match_table = adnp_of_match, |
5e969a40 TR |
621 | }, |
622 | .probe = adnp_i2c_probe, | |
8283c4ff | 623 | .remove = adnp_i2c_remove, |
5e969a40 TR |
624 | .id_table = adnp_i2c_id, |
625 | }; | |
626 | module_i2c_driver(adnp_i2c_driver); | |
627 | ||
628 | MODULE_DESCRIPTION("Avionic Design N-bit GPIO expander"); | |
629 | MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); | |
630 | MODULE_LICENSE("GPL"); |