Linux 4.15-rc1
[linux-block.git] / drivers / gpio / gpio-74x164.c
CommitLineData
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1/*
2 * 74Hx164 - Generic serial-in/parallel-out 8-bits shift register GPIO driver
3 *
4 * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Miguel Gaio <miguel.gaio@efixo.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
7ebc194d 12#include <linux/gpio/consumer.h>
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13#include <linux/init.h>
14#include <linux/mutex.h>
15#include <linux/spi/spi.h>
ead6db08 16#include <linux/gpio.h>
20bc4d5d 17#include <linux/of_gpio.h>
ead6db08 18#include <linux/slab.h>
bb207ef1 19#include <linux/module.h>
ead6db08 20
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21#define GEN_74X164_NUMBER_GPIOS 8
22
ead6db08 23struct gen_74x164_chip {
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24 struct gpio_chip gpio_chip;
25 struct mutex lock;
20bc4d5d 26 u32 registers;
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27 /*
28 * Since the registers are chained, every byte sent will make
29 * the previous byte shift to the next register in the
30 * chain. Thus, the first byte sent will end up in the last
31 * register at the end of the transfer. So, to have a logical
32 * numbering, store the bytes in reverse order.
33 */
410f4574 34 u8 buffer[0];
7ebc194d 35 struct gpio_desc *gpiod_oe;
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36};
37
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38static int __gen_74x164_write_config(struct gen_74x164_chip *chip)
39{
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40 return spi_write(to_spi_device(chip->gpio_chip.parent), chip->buffer,
41 chip->registers);
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42}
43
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44static int gen_74x164_get_value(struct gpio_chip *gc, unsigned offset)
45{
b2afc6f3 46 struct gen_74x164_chip *chip = gpiochip_get_data(gc);
902e7e60 47 u8 bank = chip->registers - 1 - offset / 8;
20bc4d5d 48 u8 pin = offset % 8;
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49 int ret;
50
51 mutex_lock(&chip->lock);
20bc4d5d 52 ret = (chip->buffer[bank] >> pin) & 0x1;
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53 mutex_unlock(&chip->lock);
54
55 return ret;
56}
57
58static void gen_74x164_set_value(struct gpio_chip *gc,
59 unsigned offset, int val)
60{
b2afc6f3 61 struct gen_74x164_chip *chip = gpiochip_get_data(gc);
902e7e60 62 u8 bank = chip->registers - 1 - offset / 8;
20bc4d5d 63 u8 pin = offset % 8;
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64
65 mutex_lock(&chip->lock);
66 if (val)
20bc4d5d 67 chip->buffer[bank] |= (1 << pin);
ead6db08 68 else
20bc4d5d 69 chip->buffer[bank] &= ~(1 << pin);
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70
71 __gen_74x164_write_config(chip);
72 mutex_unlock(&chip->lock);
73}
74
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75static void gen_74x164_set_multiple(struct gpio_chip *gc, unsigned long *mask,
76 unsigned long *bits)
77{
78 struct gen_74x164_chip *chip = gpiochip_get_data(gc);
79 unsigned int i, idx, shift;
80 u8 bank, bankmask;
81
82 mutex_lock(&chip->lock);
83 for (i = 0, bank = chip->registers - 1; i < chip->registers;
84 i++, bank--) {
85 idx = i / sizeof(*mask);
86 shift = i % sizeof(*mask) * BITS_PER_BYTE;
87 bankmask = mask[idx] >> shift;
88 if (!bankmask)
89 continue;
90
91 chip->buffer[bank] &= ~bankmask;
92 chip->buffer[bank] |= bankmask & (bits[idx] >> shift);
93 }
94 __gen_74x164_write_config(chip);
95 mutex_unlock(&chip->lock);
96}
97
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98static int gen_74x164_direction_output(struct gpio_chip *gc,
99 unsigned offset, int val)
100{
101 gen_74x164_set_value(gc, offset, val);
102 return 0;
103}
104
3836309d 105static int gen_74x164_probe(struct spi_device *spi)
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106{
107 struct gen_74x164_chip *chip;
410f4574 108 u32 nregs;
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109 int ret;
110
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111 /*
112 * bits_per_word cannot be configured in platform data
113 */
114 spi->bits_per_word = 8;
115
116 ret = spi_setup(spi);
117 if (ret < 0)
118 return ret;
119
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120 if (of_property_read_u32(spi->dev.of_node, "registers-number",
121 &nregs)) {
122 dev_err(&spi->dev,
123 "Missing registers-number property in the DT.\n");
124 return -EINVAL;
125 }
126
127 chip = devm_kzalloc(&spi->dev, sizeof(*chip) + nregs, GFP_KERNEL);
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128 if (!chip)
129 return -ENOMEM;
130
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131 chip->gpiod_oe = devm_gpiod_get_optional(&spi->dev, "enable",
132 GPIOD_OUT_LOW);
133 if (IS_ERR(chip->gpiod_oe))
134 return PTR_ERR(chip->gpiod_oe);
135
136 gpiod_set_value_cansleep(chip->gpiod_oe, 1);
137
6c0cf42b 138 spi_set_drvdata(spi, chip);
ead6db08 139
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140 chip->gpio_chip.label = spi->modalias;
141 chip->gpio_chip.direction_output = gen_74x164_direction_output;
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142 chip->gpio_chip.get = gen_74x164_get_value;
143 chip->gpio_chip.set = gen_74x164_set_value;
d46ab682 144 chip->gpio_chip.set_multiple = gen_74x164_set_multiple;
61e73804 145 chip->gpio_chip.base = -1;
20bc4d5d 146
410f4574 147 chip->registers = nregs;
20bc4d5d 148 chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers;
20bc4d5d 149
9fb1f39e 150 chip->gpio_chip.can_sleep = true;
58383c78 151 chip->gpio_chip.parent = &spi->dev;
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152 chip->gpio_chip.owner = THIS_MODULE;
153
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154 mutex_init(&chip->lock);
155
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156 ret = __gen_74x164_write_config(chip);
157 if (ret) {
158 dev_err(&spi->dev, "Failed writing: %d\n", ret);
159 goto exit_destroy;
160 }
161
b2afc6f3 162 ret = gpiochip_add_data(&chip->gpio_chip, chip);
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163 if (!ret)
164 return 0;
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165
166exit_destroy:
ead6db08 167 mutex_destroy(&chip->lock);
bcc0562c 168
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169 return ret;
170}
171
206210ce 172static int gen_74x164_remove(struct spi_device *spi)
ead6db08 173{
bcc0562c 174 struct gen_74x164_chip *chip = spi_get_drvdata(spi);
ead6db08 175
7ebc194d 176 gpiod_set_value_cansleep(chip->gpiod_oe, 0);
9f5132ae 177 gpiochip_remove(&chip->gpio_chip);
178 mutex_destroy(&chip->lock);
ead6db08 179
9f5132ae 180 return 0;
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181}
182
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183static const struct of_device_id gen_74x164_dt_ids[] = {
184 { .compatible = "fairchild,74hc595" },
80018bd9 185 { .compatible = "nxp,74lvc594" },
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186 {},
187};
188MODULE_DEVICE_TABLE(of, gen_74x164_dt_ids);
189
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190static struct spi_driver gen_74x164_driver = {
191 .driver = {
a3cc68c3 192 .name = "74x164",
187a53a5 193 .of_match_table = gen_74x164_dt_ids,
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194 },
195 .probe = gen_74x164_probe,
8283c4ff 196 .remove = gen_74x164_remove,
ead6db08 197};
ab3b8782 198module_spi_driver(gen_74x164_driver);
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199
200MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
201MODULE_AUTHOR("Miguel Gaio <miguel.gaio@efixo.com>");
202MODULE_DESCRIPTION("GPIO expander driver for 74X164 8-bits shift register");
203MODULE_LICENSE("GPL v2");