[linux-2.6-block.git] / drivers / gpio / gpio-74x164.c

/*
 *  74Hx164 - Generic serial-in/parallel-out 8-bits shift register GPIO driver
 *
 *  Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
 *  Copyright (C) 2010 Miguel Gaio <miguel.gaio@efixo.com>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/mutex.h>
#include <linux/spi/spi.h>
#include <linux/gpio/driver.h>
#include <linux/gpio/consumer.h>
#include <linux/slab.h>
#include <linux/module.h>

#define GEN_74X164_NUMBER_GPIOS	8

struct gen_74x164_chip {
	struct gpio_chip	gpio_chip;
	struct mutex		lock;
	struct gpio_desc	*gpiod_oe;
	u32			registers;
	/*
	 * Since the registers are chained, every byte sent will make
	 * the previous byte shift to the next register in the
	 * chain. Thus, the first byte sent will end up in the last
	 * register at the end of the transfer. So, to have a logical
	 * numbering, store the bytes in reverse order.
	 */
	u8			buffer[];
};

static int __gen_74x164_write_config(struct gen_74x164_chip *chip)
{
	return spi_write(to_spi_device(chip->gpio_chip.parent), chip->buffer,
			 chip->registers);
}

static int gen_74x164_get_value(struct gpio_chip *gc, unsigned offset)
{
	struct gen_74x164_chip *chip = gpiochip_get_data(gc);
	u8 bank = chip->registers - 1 - offset / 8;
	u8 pin = offset % 8;
	int ret;

	mutex_lock(&chip->lock);
	ret = (chip->buffer[bank] >> pin) & 0x1;
	mutex_unlock(&chip->lock);

	return ret;
}

static void gen_74x164_set_value(struct gpio_chip *gc,
		unsigned offset, int val)
{
	struct gen_74x164_chip *chip = gpiochip_get_data(gc);
	u8 bank = chip->registers - 1 - offset / 8;
	u8 pin = offset % 8;

	mutex_lock(&chip->lock);
	if (val)
		chip->buffer[bank] |= (1 << pin);
	else
		chip->buffer[bank] &= ~(1 << pin);

	__gen_74x164_write_config(chip);
	mutex_unlock(&chip->lock);
}

static void gen_74x164_set_multiple(struct gpio_chip *gc, unsigned long *mask,
				    unsigned long *bits)
{
	struct gen_74x164_chip *chip = gpiochip_get_data(gc);
	unsigned int i, idx, shift;
	u8 bank, bankmask;

	mutex_lock(&chip->lock);
	for (i = 0, bank = chip->registers - 1; i < chip->registers;
	     i++, bank--) {
		idx = i / sizeof(*mask);
		shift = i % sizeof(*mask) * BITS_PER_BYTE;
		bankmask = mask[idx] >> shift;
		if (!bankmask)
			continue;

		chip->buffer[bank] &= ~bankmask;
		chip->buffer[bank] |= bankmask & (bits[idx] >> shift);
	}
	__gen_74x164_write_config(chip);
	mutex_unlock(&chip->lock);
}

static int gen_74x164_direction_output(struct gpio_chip *gc,
		unsigned offset, int val)
{
	gen_74x164_set_value(gc, offset, val);
	return 0;
}

static int gen_74x164_probe(struct spi_device *spi)
{
	struct gen_74x164_chip *chip;
	u32 nregs;
	int ret;

	/*
	 * bits_per_word cannot be configured in platform data
	 */
	spi->bits_per_word = 8;

	ret = spi_setup(spi);
	if (ret < 0)
		return ret;

	if (of_property_read_u32(spi->dev.of_node, "registers-number",
				 &nregs)) {
		dev_err(&spi->dev,
			"Missing registers-number property in the DT.\n");
		return -EINVAL;
	}

	chip = devm_kzalloc(&spi->dev, sizeof(*chip) + nregs, GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	chip->gpiod_oe = devm_gpiod_get_optional(&spi->dev, "enable",
						 GPIOD_OUT_LOW);
	if (IS_ERR(chip->gpiod_oe))
		return PTR_ERR(chip->gpiod_oe);

	gpiod_set_value_cansleep(chip->gpiod_oe, 1);

	spi_set_drvdata(spi, chip);

	chip->gpio_chip.label = spi->modalias;
	chip->gpio_chip.direction_output = gen_74x164_direction_output;
	chip->gpio_chip.get = gen_74x164_get_value;
	chip->gpio_chip.set = gen_74x164_set_value;
	chip->gpio_chip.set_multiple = gen_74x164_set_multiple;
	chip->gpio_chip.base = -1;

	chip->registers = nregs;
	chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers;

	chip->gpio_chip.can_sleep = true;
	chip->gpio_chip.parent = &spi->dev;
	chip->gpio_chip.owner = THIS_MODULE;

	mutex_init(&chip->lock);

	ret = __gen_74x164_write_config(chip);
	if (ret) {
		dev_err(&spi->dev, "Failed writing: %d\n", ret);
		goto exit_destroy;
	}

	ret = gpiochip_add_data(&chip->gpio_chip, chip);
	if (!ret)
		return 0;

exit_destroy:
	mutex_destroy(&chip->lock);

	return ret;
}

static int gen_74x164_remove(struct spi_device *spi)
{
	struct gen_74x164_chip *chip = spi_get_drvdata(spi);

	gpiod_set_value_cansleep(chip->gpiod_oe, 0);
	gpiochip_remove(&chip->gpio_chip);
	mutex_destroy(&chip->lock);

	return 0;
}

static const struct of_device_id gen_74x164_dt_ids[] = {
	{ .compatible = "fairchild,74hc595" },
	{ .compatible = "nxp,74lvc594" },
	{},
};
MODULE_DEVICE_TABLE(of, gen_74x164_dt_ids);

static struct spi_driver gen_74x164_driver = {
	.driver = {
		.name		= "74x164",
		.of_match_table	= gen_74x164_dt_ids,
	},
	.probe		= gen_74x164_probe,
	.remove		= gen_74x164_remove,
};
module_spi_driver(gen_74x164_driver);

MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
MODULE_AUTHOR("Miguel Gaio <miguel.gaio@efixo.com>");
MODULE_DESCRIPTION("GPIO expander driver for 74X164 8-bits shift register");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
ead6db08 MG	1	/*
	2	* 74Hx164 - Generic serial-in/parallel-out 8-bits shift register GPIO driver
	3	*
	4	* Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
	5	* Copyright (C) 2010 Miguel Gaio <miguel.gaio@efixo.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/init.h>
	13	#include <linux/mutex.h>
	14	#include <linux/spi/spi.h>
91f6a4af LW	15	#include <linux/gpio/driver.h>
91f6a4af LW	16	#include <linux/gpio/consumer.h>
ead6db08	17	#include <linux/slab.h>
bb207ef1	18	#include <linux/module.h>
ead6db08	19
20bc4d5d MR	20	#define GEN_74X164_NUMBER_GPIOS 8
20bc4d5d MR	21
ead6db08	22	struct gen_74x164_chip {
ead6db08 MG	23	struct gpio_chip gpio_chip;
ead6db08 MG	24	struct mutex lock;
a158531f	25	struct gpio_desc *gpiod_oe;
20bc4d5d	26	u32 registers;
902e7e60 GU	27	/*
	28	* Since the registers are chained, every byte sent will make
	29	* the previous byte shift to the next register in the
	30	* chain. Thus, the first byte sent will end up in the last
	31	* register at the end of the transfer. So, to have a logical
	32	* numbering, store the bytes in reverse order.
	33	*/
a158531f	34	u8 buffer[];
ead6db08 MG	35	};
ead6db08 MG	36
ead6db08 MG	37	static int __gen_74x164_write_config(struct gen_74x164_chip *chip)
ead6db08 MG	38	{
771d899a GU	39	return spi_write(to_spi_device(chip->gpio_chip.parent), chip->buffer,
771d899a GU	40	chip->registers);
ead6db08 MG	41	}
ead6db08 MG	42
ead6db08 MG	43	static int gen_74x164_get_value(struct gpio_chip *gc, unsigned offset)
ead6db08 MG	44	{
b2afc6f3	45	struct gen_74x164_chip *chip = gpiochip_get_data(gc);
902e7e60	46	u8 bank = chip->registers - 1 - offset / 8;
20bc4d5d	47	u8 pin = offset % 8;
ead6db08 MG	48	int ret;
	49
	50	mutex_lock(&chip->lock);
20bc4d5d	51	ret = (chip->buffer[bank] >> pin) & 0x1;
ead6db08 MG	52	mutex_unlock(&chip->lock);
	53
	54	return ret;
	55	}
	56
	57	static void gen_74x164_set_value(struct gpio_chip *gc,
	58	unsigned offset, int val)
	59	{
b2afc6f3	60	struct gen_74x164_chip *chip = gpiochip_get_data(gc);
902e7e60	61	u8 bank = chip->registers - 1 - offset / 8;
20bc4d5d	62	u8 pin = offset % 8;
ead6db08 MG	63
	64	mutex_lock(&chip->lock);
	65	if (val)
20bc4d5d	66	chip->buffer[bank] \|= (1 << pin);
ead6db08	67	else
20bc4d5d	68	chip->buffer[bank] &= ~(1 << pin);
ead6db08 MG	69
	70	__gen_74x164_write_config(chip);
	71	mutex_unlock(&chip->lock);
	72	}
	73
d46ab682 GU	74	static void gen_74x164_set_multiple(struct gpio_chip gc, unsigned long mask,
	75	unsigned long *bits)
	76	{
	77	struct gen_74x164_chip *chip = gpiochip_get_data(gc);
	78	unsigned int i, idx, shift;
	79	u8 bank, bankmask;
	80
	81	mutex_lock(&chip->lock);
	82	for (i = 0, bank = chip->registers - 1; i < chip->registers;
	83	i++, bank--) {
	84	idx = i / sizeof(*mask);
	85	shift = i % sizeof(mask) BITS_PER_BYTE;
	86	bankmask = mask[idx] >> shift;
	87	if (!bankmask)
	88	continue;
	89
	90	chip->buffer[bank] &= ~bankmask;
	91	chip->buffer[bank] \|= bankmask & (bits[idx] >> shift);
	92	}
	93	__gen_74x164_write_config(chip);
	94	mutex_unlock(&chip->lock);
	95	}
	96
a3cc68c3 HS	97	static int gen_74x164_direction_output(struct gpio_chip *gc,
	98	unsigned offset, int val)
	99	{
	100	gen_74x164_set_value(gc, offset, val);
	101	return 0;
	102	}
	103
3836309d	104	static int gen_74x164_probe(struct spi_device *spi)
ead6db08 MG	105	{
ead6db08 MG	106	struct gen_74x164_chip *chip;
410f4574	107	u32 nregs;
ead6db08 MG	108	int ret;
ead6db08 MG	109
ead6db08 MG	110	/*
	111	* bits_per_word cannot be configured in platform data
	112	*/
	113	spi->bits_per_word = 8;
	114
	115	ret = spi_setup(spi);
	116	if (ret < 0)
	117	return ret;
	118
410f4574 GU	119	if (of_property_read_u32(spi->dev.of_node, "registers-number",
	120	&nregs)) {
	121	dev_err(&spi->dev,
	122	"Missing registers-number property in the DT.\n");
	123	return -EINVAL;
	124	}
	125
	126	chip = devm_kzalloc(&spi->dev, sizeof(*chip) + nregs, GFP_KERNEL);
ead6db08 MG	127	if (!chip)
	128	return -ENOMEM;
	129
7ebc194d FE	130	chip->gpiod_oe = devm_gpiod_get_optional(&spi->dev, "enable",
	131	GPIOD_OUT_LOW);
	132	if (IS_ERR(chip->gpiod_oe))
	133	return PTR_ERR(chip->gpiod_oe);
	134
	135	gpiod_set_value_cansleep(chip->gpiod_oe, 1);
	136
6c0cf42b	137	spi_set_drvdata(spi, chip);
ead6db08	138
a3cc68c3 HS	139	chip->gpio_chip.label = spi->modalias;
a3cc68c3 HS	140	chip->gpio_chip.direction_output = gen_74x164_direction_output;
ead6db08 MG	141	chip->gpio_chip.get = gen_74x164_get_value;
ead6db08 MG	142	chip->gpio_chip.set = gen_74x164_set_value;
d46ab682	143	chip->gpio_chip.set_multiple = gen_74x164_set_multiple;
61e73804	144	chip->gpio_chip.base = -1;
20bc4d5d	145
410f4574	146	chip->registers = nregs;
20bc4d5d	147	chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers;
20bc4d5d	148
9fb1f39e	149	chip->gpio_chip.can_sleep = true;
58383c78	150	chip->gpio_chip.parent = &spi->dev;
ead6db08 MG	151	chip->gpio_chip.owner = THIS_MODULE;
ead6db08 MG	152
bcc0562c AS	153	mutex_init(&chip->lock);
bcc0562c AS	154
ead6db08 MG	155	ret = __gen_74x164_write_config(chip);
	156	if (ret) {
	157	dev_err(&spi->dev, "Failed writing: %d\n", ret);
	158	goto exit_destroy;
	159	}
	160
b2afc6f3	161	ret = gpiochip_add_data(&chip->gpio_chip, chip);
bcc0562c AS	162	if (!ret)
bcc0562c AS	163	return 0;
ead6db08 MG	164
ead6db08 MG	165	exit_destroy:
ead6db08	166	mutex_destroy(&chip->lock);
bcc0562c	167
ead6db08 MG	168	return ret;
	169	}
	170
206210ce	171	static int gen_74x164_remove(struct spi_device *spi)
ead6db08	172	{
bcc0562c	173	struct gen_74x164_chip *chip = spi_get_drvdata(spi);
ead6db08	174
7ebc194d	175	gpiod_set_value_cansleep(chip->gpiod_oe, 0);
9f5132ae	176	gpiochip_remove(&chip->gpio_chip);
9f5132ae	177	mutex_destroy(&chip->lock);
ead6db08	178
9f5132ae	179	return 0;
ead6db08 MG	180	}
ead6db08 MG	181
0a90a9fb MR	182	static const struct of_device_id gen_74x164_dt_ids[] = {
0a90a9fb MR	183	{ .compatible = "fairchild,74hc595" },
80018bd9	184	{ .compatible = "nxp,74lvc594" },
0a90a9fb MR	185	{},
	186	};
	187	MODULE_DEVICE_TABLE(of, gen_74x164_dt_ids);
	188
ead6db08 MG	189	static struct spi_driver gen_74x164_driver = {
ead6db08 MG	190	.driver = {
a3cc68c3	191	.name = "74x164",
187a53a5	192	.of_match_table = gen_74x164_dt_ids,
ead6db08 MG	193	},
ead6db08 MG	194	.probe = gen_74x164_probe,
8283c4ff	195	.remove = gen_74x164_remove,
ead6db08	196	};
ab3b8782	197	module_spi_driver(gen_74x164_driver);
ead6db08 MG	198
	199	MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
	200	MODULE_AUTHOR("Miguel Gaio <miguel.gaio@efixo.com>");
	201	MODULE_DESCRIPTION("GPIO expander driver for 74X164 8-bits shift register");
	202	MODULE_LICENSE("GPL v2");