Commit | Line | Data |
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9a9982d4 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
ead6db08 MG |
2 | /* |
3 | * 74Hx164 - Generic serial-in/parallel-out 8-bits shift register GPIO driver | |
4 | * | |
5 | * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org> | |
6 | * Copyright (C) 2010 Miguel Gaio <miguel.gaio@efixo.com> | |
ead6db08 MG |
7 | */ |
8 | ||
b2ca9ebf | 9 | #include <linux/bitops.h> |
91f6a4af | 10 | #include <linux/gpio/consumer.h> |
517ec439 AS |
11 | #include <linux/gpio/driver.h> |
12 | #include <linux/module.h> | |
13 | #include <linux/mutex.h> | |
3c746951 | 14 | #include <linux/property.h> |
ead6db08 | 15 | #include <linux/slab.h> |
517ec439 | 16 | #include <linux/spi/spi.h> |
ead6db08 | 17 | |
20bc4d5d MR |
18 | #define GEN_74X164_NUMBER_GPIOS 8 |
19 | ||
ead6db08 | 20 | struct gen_74x164_chip { |
ead6db08 MG |
21 | struct gpio_chip gpio_chip; |
22 | struct mutex lock; | |
a158531f | 23 | struct gpio_desc *gpiod_oe; |
20bc4d5d | 24 | u32 registers; |
902e7e60 GU |
25 | /* |
26 | * Since the registers are chained, every byte sent will make | |
27 | * the previous byte shift to the next register in the | |
28 | * chain. Thus, the first byte sent will end up in the last | |
29 | * register at the end of the transfer. So, to have a logical | |
30 | * numbering, store the bytes in reverse order. | |
31 | */ | |
a158531f | 32 | u8 buffer[]; |
ead6db08 MG |
33 | }; |
34 | ||
ead6db08 MG |
35 | static int __gen_74x164_write_config(struct gen_74x164_chip *chip) |
36 | { | |
771d899a GU |
37 | return spi_write(to_spi_device(chip->gpio_chip.parent), chip->buffer, |
38 | chip->registers); | |
ead6db08 MG |
39 | } |
40 | ||
ead6db08 MG |
41 | static int gen_74x164_get_value(struct gpio_chip *gc, unsigned offset) |
42 | { | |
b2afc6f3 | 43 | struct gen_74x164_chip *chip = gpiochip_get_data(gc); |
902e7e60 | 44 | u8 bank = chip->registers - 1 - offset / 8; |
20bc4d5d | 45 | u8 pin = offset % 8; |
ead6db08 MG |
46 | int ret; |
47 | ||
48 | mutex_lock(&chip->lock); | |
20bc4d5d | 49 | ret = (chip->buffer[bank] >> pin) & 0x1; |
ead6db08 MG |
50 | mutex_unlock(&chip->lock); |
51 | ||
52 | return ret; | |
53 | } | |
54 | ||
55 | static void gen_74x164_set_value(struct gpio_chip *gc, | |
56 | unsigned offset, int val) | |
57 | { | |
b2afc6f3 | 58 | struct gen_74x164_chip *chip = gpiochip_get_data(gc); |
902e7e60 | 59 | u8 bank = chip->registers - 1 - offset / 8; |
20bc4d5d | 60 | u8 pin = offset % 8; |
ead6db08 MG |
61 | |
62 | mutex_lock(&chip->lock); | |
63 | if (val) | |
20bc4d5d | 64 | chip->buffer[bank] |= (1 << pin); |
ead6db08 | 65 | else |
20bc4d5d | 66 | chip->buffer[bank] &= ~(1 << pin); |
ead6db08 MG |
67 | |
68 | __gen_74x164_write_config(chip); | |
69 | mutex_unlock(&chip->lock); | |
70 | } | |
71 | ||
d46ab682 GU |
72 | static void gen_74x164_set_multiple(struct gpio_chip *gc, unsigned long *mask, |
73 | unsigned long *bits) | |
74 | { | |
75 | struct gen_74x164_chip *chip = gpiochip_get_data(gc); | |
b2ca9ebf WBG |
76 | unsigned long offset; |
77 | unsigned long bankmask; | |
78 | size_t bank; | |
79 | unsigned long bitmask; | |
d46ab682 GU |
80 | |
81 | mutex_lock(&chip->lock); | |
b2ca9ebf WBG |
82 | for_each_set_clump8(offset, bankmask, mask, chip->registers * 8) { |
83 | bank = chip->registers - 1 - offset / 8; | |
84 | bitmask = bitmap_get_value8(bits, offset) & bankmask; | |
d46ab682 GU |
85 | |
86 | chip->buffer[bank] &= ~bankmask; | |
b2ca9ebf | 87 | chip->buffer[bank] |= bitmask; |
d46ab682 GU |
88 | } |
89 | __gen_74x164_write_config(chip); | |
90 | mutex_unlock(&chip->lock); | |
91 | } | |
92 | ||
a3cc68c3 HS |
93 | static int gen_74x164_direction_output(struct gpio_chip *gc, |
94 | unsigned offset, int val) | |
95 | { | |
96 | gen_74x164_set_value(gc, offset, val); | |
97 | return 0; | |
98 | } | |
99 | ||
3836309d | 100 | static int gen_74x164_probe(struct spi_device *spi) |
ead6db08 MG |
101 | { |
102 | struct gen_74x164_chip *chip; | |
410f4574 | 103 | u32 nregs; |
ead6db08 MG |
104 | int ret; |
105 | ||
ead6db08 MG |
106 | /* |
107 | * bits_per_word cannot be configured in platform data | |
108 | */ | |
109 | spi->bits_per_word = 8; | |
110 | ||
111 | ret = spi_setup(spi); | |
112 | if (ret < 0) | |
113 | return ret; | |
114 | ||
3c746951 AS |
115 | ret = device_property_read_u32(&spi->dev, "registers-number", &nregs); |
116 | if (ret) { | |
117 | dev_err(&spi->dev, "Missing 'registers-number' property.\n"); | |
410f4574 GU |
118 | return -EINVAL; |
119 | } | |
120 | ||
121 | chip = devm_kzalloc(&spi->dev, sizeof(*chip) + nregs, GFP_KERNEL); | |
ead6db08 MG |
122 | if (!chip) |
123 | return -ENOMEM; | |
124 | ||
7ebc194d FE |
125 | chip->gpiod_oe = devm_gpiod_get_optional(&spi->dev, "enable", |
126 | GPIOD_OUT_LOW); | |
127 | if (IS_ERR(chip->gpiod_oe)) | |
128 | return PTR_ERR(chip->gpiod_oe); | |
129 | ||
130 | gpiod_set_value_cansleep(chip->gpiod_oe, 1); | |
131 | ||
6c0cf42b | 132 | spi_set_drvdata(spi, chip); |
ead6db08 | 133 | |
a3cc68c3 HS |
134 | chip->gpio_chip.label = spi->modalias; |
135 | chip->gpio_chip.direction_output = gen_74x164_direction_output; | |
ead6db08 MG |
136 | chip->gpio_chip.get = gen_74x164_get_value; |
137 | chip->gpio_chip.set = gen_74x164_set_value; | |
d46ab682 | 138 | chip->gpio_chip.set_multiple = gen_74x164_set_multiple; |
61e73804 | 139 | chip->gpio_chip.base = -1; |
20bc4d5d | 140 | |
410f4574 | 141 | chip->registers = nregs; |
20bc4d5d | 142 | chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers; |
20bc4d5d | 143 | |
9fb1f39e | 144 | chip->gpio_chip.can_sleep = true; |
58383c78 | 145 | chip->gpio_chip.parent = &spi->dev; |
ead6db08 MG |
146 | chip->gpio_chip.owner = THIS_MODULE; |
147 | ||
bcc0562c AS |
148 | mutex_init(&chip->lock); |
149 | ||
ead6db08 MG |
150 | ret = __gen_74x164_write_config(chip); |
151 | if (ret) { | |
152 | dev_err(&spi->dev, "Failed writing: %d\n", ret); | |
153 | goto exit_destroy; | |
154 | } | |
155 | ||
b2afc6f3 | 156 | ret = gpiochip_add_data(&chip->gpio_chip, chip); |
bcc0562c AS |
157 | if (!ret) |
158 | return 0; | |
ead6db08 MG |
159 | |
160 | exit_destroy: | |
ead6db08 | 161 | mutex_destroy(&chip->lock); |
bcc0562c | 162 | |
ead6db08 MG |
163 | return ret; |
164 | } | |
165 | ||
a0386bba | 166 | static void gen_74x164_remove(struct spi_device *spi) |
ead6db08 | 167 | { |
bcc0562c | 168 | struct gen_74x164_chip *chip = spi_get_drvdata(spi); |
ead6db08 | 169 | |
7ebc194d | 170 | gpiod_set_value_cansleep(chip->gpiod_oe, 0); |
9f5132ae | 171 | gpiochip_remove(&chip->gpio_chip); |
172 | mutex_destroy(&chip->lock); | |
ead6db08 MG |
173 | } |
174 | ||
be449183 MB |
175 | static const struct spi_device_id gen_74x164_spi_ids[] = { |
176 | { .name = "74hc595" }, | |
177 | { .name = "74lvc594" }, | |
178 | {}, | |
179 | }; | |
180 | MODULE_DEVICE_TABLE(spi, gen_74x164_spi_ids); | |
181 | ||
0a90a9fb MR |
182 | static const struct of_device_id gen_74x164_dt_ids[] = { |
183 | { .compatible = "fairchild,74hc595" }, | |
80018bd9 | 184 | { .compatible = "nxp,74lvc594" }, |
0a90a9fb MR |
185 | {}, |
186 | }; | |
187 | MODULE_DEVICE_TABLE(of, gen_74x164_dt_ids); | |
188 | ||
ead6db08 MG |
189 | static struct spi_driver gen_74x164_driver = { |
190 | .driver = { | |
a3cc68c3 | 191 | .name = "74x164", |
187a53a5 | 192 | .of_match_table = gen_74x164_dt_ids, |
ead6db08 MG |
193 | }, |
194 | .probe = gen_74x164_probe, | |
8283c4ff | 195 | .remove = gen_74x164_remove, |
be449183 | 196 | .id_table = gen_74x164_spi_ids, |
ead6db08 | 197 | }; |
ab3b8782 | 198 | module_spi_driver(gen_74x164_driver); |
ead6db08 MG |
199 | |
200 | MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); | |
201 | MODULE_AUTHOR("Miguel Gaio <miguel.gaio@efixo.com>"); | |
202 | MODULE_DESCRIPTION("GPIO expander driver for 74X164 8-bits shift register"); | |
203 | MODULE_LICENSE("GPL v2"); |