[linux-block.git] / drivers / gpio / gpio-104-idio-16.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * GPIO driver for the ACCES 104-IDIO-16 family
 * Copyright (C) 2015 William Breathitt Gray
 *
 * This driver supports the following ACCES devices: 104-IDIO-16,
 * 104-IDIO-16E, 104-IDO-16, 104-IDIO-8, 104-IDIO-8E, and 104-IDO-8.
 */
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/irqdesc.h>
#include <linux/isa.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/spinlock.h>

#define IDIO_16_EXTENT 8
#define MAX_NUM_IDIO_16 max_num_isa_dev(IDIO_16_EXTENT)

static unsigned int base[MAX_NUM_IDIO_16];
static unsigned int num_idio_16;
module_param_hw_array(base, uint, ioport, &num_idio_16, 0);
MODULE_PARM_DESC(base, "ACCES 104-IDIO-16 base addresses");

static unsigned int irq[MAX_NUM_IDIO_16];
module_param_hw_array(irq, uint, irq, NULL, 0);
MODULE_PARM_DESC(irq, "ACCES 104-IDIO-16 interrupt line numbers");

/**
 * struct idio_16_gpio - GPIO device private data structure
 * @chip:	instance of the gpio_chip
 * @lock:	synchronization lock to prevent I/O race conditions
 * @irq_mask:	I/O bits affected by interrupts
 * @base:	base port address of the GPIO device
 * @out_state:	output bits state
 */
struct idio_16_gpio {
	struct gpio_chip chip;
	raw_spinlock_t lock;
	unsigned long irq_mask;
	unsigned int base;
	unsigned int out_state;
};

static int idio_16_gpio_get_direction(struct gpio_chip *chip,
				      unsigned int offset)
{
	if (offset > 15)
		return GPIO_LINE_DIRECTION_IN;

	return GPIO_LINE_DIRECTION_OUT;
}

static int idio_16_gpio_direction_input(struct gpio_chip *chip,
					unsigned int offset)
{
	return 0;
}

static int idio_16_gpio_direction_output(struct gpio_chip *chip,
	unsigned int offset, int value)
{
	chip->set(chip, offset, value);
	return 0;
}

static int idio_16_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
	const unsigned int mask = BIT(offset-16);

	if (offset < 16)
		return -EINVAL;

	if (offset < 24)
		return !!(inb(idio16gpio->base + 1) & mask);

	return !!(inb(idio16gpio->base + 5) & (mask>>8));
}

static int idio_16_gpio_get_multiple(struct gpio_chip *chip,
	unsigned long *mask, unsigned long *bits)
{
	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);

	*bits = 0;
	if (*mask & GENMASK(23, 16))
		*bits |= (unsigned long)inb(idio16gpio->base + 1) << 16;
	if (*mask & GENMASK(31, 24))
		*bits |= (unsigned long)inb(idio16gpio->base + 5) << 24;

	return 0;
}

static void idio_16_gpio_set(struct gpio_chip *chip, unsigned int offset,
			     int value)
{
	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
	const unsigned int mask = BIT(offset);
	unsigned long flags;

	if (offset > 15)
		return;

	raw_spin_lock_irqsave(&idio16gpio->lock, flags);

	if (value)
		idio16gpio->out_state |= mask;
	else
		idio16gpio->out_state &= ~mask;

	if (offset > 7)
		outb(idio16gpio->out_state >> 8, idio16gpio->base + 4);
	else
		outb(idio16gpio->out_state, idio16gpio->base);

	raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
}

static void idio_16_gpio_set_multiple(struct gpio_chip *chip,
	unsigned long *mask, unsigned long *bits)
{
	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
	unsigned long flags;

	raw_spin_lock_irqsave(&idio16gpio->lock, flags);

	idio16gpio->out_state &= ~*mask;
	idio16gpio->out_state |= *mask & *bits;

	if (*mask & 0xFF)
		outb(idio16gpio->out_state, idio16gpio->base);
	if ((*mask >> 8) & 0xFF)
		outb(idio16gpio->out_state >> 8, idio16gpio->base + 4);

	raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
}

static void idio_16_irq_ack(struct irq_data *data)
{
}

static void idio_16_irq_mask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
	const unsigned long mask = BIT(irqd_to_hwirq(data));
	unsigned long flags;

	idio16gpio->irq_mask &= ~mask;

	if (!idio16gpio->irq_mask) {
		raw_spin_lock_irqsave(&idio16gpio->lock, flags);

		outb(0, idio16gpio->base + 2);

		raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
	}
}

static void idio_16_irq_unmask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
	const unsigned long mask = BIT(irqd_to_hwirq(data));
	const unsigned long prev_irq_mask = idio16gpio->irq_mask;
	unsigned long flags;

	idio16gpio->irq_mask |= mask;

	if (!prev_irq_mask) {
		raw_spin_lock_irqsave(&idio16gpio->lock, flags);

		inb(idio16gpio->base + 2);

		raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
	}
}

static int idio_16_irq_set_type(struct irq_data *data, unsigned int flow_type)
{
	/* The only valid irq types are none and both-edges */
	if (flow_type != IRQ_TYPE_NONE &&
		(flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
		return -EINVAL;

	return 0;
}

static struct irq_chip idio_16_irqchip = {
	.name = "104-idio-16",
	.irq_ack = idio_16_irq_ack,
	.irq_mask = idio_16_irq_mask,
	.irq_unmask = idio_16_irq_unmask,
	.irq_set_type = idio_16_irq_set_type
};

static irqreturn_t idio_16_irq_handler(int irq, void *dev_id)
{
	struct idio_16_gpio *const idio16gpio = dev_id;
	struct gpio_chip *const chip = &idio16gpio->chip;
	int gpio;

	for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
		generic_handle_domain_irq(chip->irq.domain, gpio);

	raw_spin_lock(&idio16gpio->lock);

	outb(0, idio16gpio->base + 1);

	raw_spin_unlock(&idio16gpio->lock);

	return IRQ_HANDLED;
}

#define IDIO_16_NGPIO 32
static const char *idio_16_names[IDIO_16_NGPIO] = {
	"OUT0", "OUT1", "OUT2", "OUT3", "OUT4", "OUT5", "OUT6", "OUT7",
	"OUT8", "OUT9", "OUT10", "OUT11", "OUT12", "OUT13", "OUT14", "OUT15",
	"IIN0", "IIN1", "IIN2", "IIN3", "IIN4", "IIN5", "IIN6", "IIN7",
	"IIN8", "IIN9", "IIN10", "IIN11", "IIN12", "IIN13", "IIN14", "IIN15"
};

static int idio_16_irq_init_hw(struct gpio_chip *gc)
{
	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(gc);

	/* Disable IRQ by default */
	outb(0, idio16gpio->base + 2);
	outb(0, idio16gpio->base + 1);

	return 0;
}

static int idio_16_probe(struct device *dev, unsigned int id)
{
	struct idio_16_gpio *idio16gpio;
	const char *const name = dev_name(dev);
	struct gpio_irq_chip *girq;
	int err;

	idio16gpio = devm_kzalloc(dev, sizeof(*idio16gpio), GFP_KERNEL);
	if (!idio16gpio)
		return -ENOMEM;

	if (!devm_request_region(dev, base[id], IDIO_16_EXTENT, name)) {
		dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
			base[id], base[id] + IDIO_16_EXTENT);
		return -EBUSY;
	}

	idio16gpio->chip.label = name;
	idio16gpio->chip.parent = dev;
	idio16gpio->chip.owner = THIS_MODULE;
	idio16gpio->chip.base = -1;
	idio16gpio->chip.ngpio = IDIO_16_NGPIO;
	idio16gpio->chip.names = idio_16_names;
	idio16gpio->chip.get_direction = idio_16_gpio_get_direction;
	idio16gpio->chip.direction_input = idio_16_gpio_direction_input;
	idio16gpio->chip.direction_output = idio_16_gpio_direction_output;
	idio16gpio->chip.get = idio_16_gpio_get;
	idio16gpio->chip.get_multiple = idio_16_gpio_get_multiple;
	idio16gpio->chip.set = idio_16_gpio_set;
	idio16gpio->chip.set_multiple = idio_16_gpio_set_multiple;
	idio16gpio->base = base[id];
	idio16gpio->out_state = 0xFFFF;

	girq = &idio16gpio->chip.irq;
	girq->chip = &idio_16_irqchip;
	/* This will let us handle the parent IRQ in the driver */
	girq->parent_handler = NULL;
	girq->num_parents = 0;
	girq->parents = NULL;
	girq->default_type = IRQ_TYPE_NONE;
	girq->handler = handle_edge_irq;
	girq->init_hw = idio_16_irq_init_hw;

	raw_spin_lock_init(&idio16gpio->lock);

	err = devm_gpiochip_add_data(dev, &idio16gpio->chip, idio16gpio);
	if (err) {
		dev_err(dev, "GPIO registering failed (%d)\n", err);
		return err;
	}

	err = devm_request_irq(dev, irq[id], idio_16_irq_handler, 0, name,
		idio16gpio);
	if (err) {
		dev_err(dev, "IRQ handler registering failed (%d)\n", err);
		return err;
	}

	return 0;
}

static struct isa_driver idio_16_driver = {
	.probe = idio_16_probe,
	.driver = {
		.name = "104-idio-16"
	},
};

module_isa_driver(idio_16_driver, num_idio_16);

MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
MODULE_DESCRIPTION("ACCES 104-IDIO-16 GPIO driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
1ceacea2 WBG	2	/*
	3	* GPIO driver for the ACCES 104-IDIO-16 family
	4	* Copyright (C) 2015 William Breathitt Gray
	5	*
86ea8a95 WBG	6	* This driver supports the following ACCES devices: 104-IDIO-16,
86ea8a95 WBG	7	* 104-IDIO-16E, 104-IDO-16, 104-IDIO-8, 104-IDIO-8E, and 104-IDO-8.
1ceacea2	8	*/
a1184147	9	#include <linux/bitops.h>
1ceacea2 WBG	10	#include <linux/device.h>
	11	#include <linux/errno.h>
	12	#include <linux/gpio/driver.h>
	13	#include <linux/io.h>
	14	#include <linux/ioport.h>
a1184147 WBG	15	#include <linux/interrupt.h>
a1184147 WBG	16	#include <linux/irqdesc.h>
86ea8a95	17	#include <linux/isa.h>
1ceacea2 WBG	18	#include <linux/kernel.h>
	19	#include <linux/module.h>
	20	#include <linux/moduleparam.h>
1ceacea2 WBG	21	#include <linux/spinlock.h>
1ceacea2 WBG	22
86ea8a95 WBG	23	#define IDIO_16_EXTENT 8
	24	#define MAX_NUM_IDIO_16 max_num_isa_dev(IDIO_16_EXTENT)
	25
	26	static unsigned int base[MAX_NUM_IDIO_16];
	27	static unsigned int num_idio_16;
d759f906	28	module_param_hw_array(base, uint, ioport, &num_idio_16, 0);
86ea8a95 WBG	29	MODULE_PARM_DESC(base, "ACCES 104-IDIO-16 base addresses");
	30
	31	static unsigned int irq[MAX_NUM_IDIO_16];
d759f906	32	module_param_hw_array(irq, uint, irq, NULL, 0);
86ea8a95	33	MODULE_PARM_DESC(irq, "ACCES 104-IDIO-16 interrupt line numbers");
1ceacea2 WBG	34
	35	/**
	36	* struct idio_16_gpio - GPIO device private data structure
	37	* @chip: instance of the gpio_chip
a1184147 WBG	38	* @lock: synchronization lock to prevent I/O race conditions
a1184147 WBG	39	* @irq_mask: I/O bits affected by interrupts
1ceacea2	40	* @base: base port address of the GPIO device
1ceacea2 WBG	41	* @out_state: output bits state
	42	*/
	43	struct idio_16_gpio {
	44	struct gpio_chip chip;
3906e808	45	raw_spinlock_t lock;
a1184147	46	unsigned long irq_mask;
cc0f53d2 NSV	47	unsigned int base;
cc0f53d2 NSV	48	unsigned int out_state;
1ceacea2 WBG	49	};
1ceacea2 WBG	50
cc0f53d2 NSV	51	static int idio_16_gpio_get_direction(struct gpio_chip *chip,
cc0f53d2 NSV	52	unsigned int offset)
1ceacea2 WBG	53	{
1ceacea2 WBG	54	if (offset > 15)
e42615ec	55	return GPIO_LINE_DIRECTION_IN;
1ceacea2	56
e42615ec	57	return GPIO_LINE_DIRECTION_OUT;
1ceacea2 WBG	58	}
1ceacea2 WBG	59
cc0f53d2 NSV	60	static int idio_16_gpio_direction_input(struct gpio_chip *chip,
cc0f53d2 NSV	61	unsigned int offset)
1ceacea2 WBG	62	{
	63	return 0;
	64	}
	65
	66	static int idio_16_gpio_direction_output(struct gpio_chip *chip,
cc0f53d2	67	unsigned int offset, int value)
1ceacea2 WBG	68	{
	69	chip->set(chip, offset, value);
	70	return 0;
	71	}
	72
cc0f53d2	73	static int idio_16_gpio_get(struct gpio_chip *chip, unsigned int offset)
1ceacea2	74	{
d602ae90	75	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
cc0f53d2	76	const unsigned int mask = BIT(offset-16);
1ceacea2 WBG	77
	78	if (offset < 16)
	79	return -EINVAL;
	80
	81	if (offset < 24)
6e0171b4	82	return !!(inb(idio16gpio->base + 1) & mask);
1ceacea2	83
6e0171b4	84	return !!(inb(idio16gpio->base + 5) & (mask>>8));
1ceacea2 WBG	85	}
1ceacea2 WBG	86
15f59cff WBG	87	static int idio_16_gpio_get_multiple(struct gpio_chip *chip,
	88	unsigned long mask, unsigned long bits)
	89	{
	90	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
	91
	92	*bits = 0;
	93	if (*mask & GENMASK(23, 16))
	94	*bits \|= (unsigned long)inb(idio16gpio->base + 1) << 16;
	95	if (*mask & GENMASK(31, 24))
	96	*bits \|= (unsigned long)inb(idio16gpio->base + 5) << 24;
	97
	98	return 0;
	99	}
	100
cc0f53d2 NSV	101	static void idio_16_gpio_set(struct gpio_chip *chip, unsigned int offset,
cc0f53d2 NSV	102	int value)
1ceacea2	103	{
d602ae90	104	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
cc0f53d2	105	const unsigned int mask = BIT(offset);
1ceacea2 WBG	106	unsigned long flags;
	107
	108	if (offset > 15)
	109	return;
	110
3906e808	111	raw_spin_lock_irqsave(&idio16gpio->lock, flags);
1ceacea2 WBG	112
1ceacea2 WBG	113	if (value)
6e0171b4	114	idio16gpio->out_state \|= mask;
1ceacea2	115	else
6e0171b4	116	idio16gpio->out_state &= ~mask;
1ceacea2 WBG	117
	118	if (offset > 7)
	119	outb(idio16gpio->out_state >> 8, idio16gpio->base + 4);
	120	else
	121	outb(idio16gpio->out_state, idio16gpio->base);
	122
3906e808	123	raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
1ceacea2 WBG	124	}
1ceacea2 WBG	125
9d7ae812 WBG	126	static void idio_16_gpio_set_multiple(struct gpio_chip *chip,
	127	unsigned long mask, unsigned long bits)
	128	{
	129	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
	130	unsigned long flags;
	131
3906e808	132	raw_spin_lock_irqsave(&idio16gpio->lock, flags);
9d7ae812 WBG	133
	134	idio16gpio->out_state &= ~*mask;
	135	idio16gpio->out_state \|= mask & bits;
	136
	137	if (*mask & 0xFF)
	138	outb(idio16gpio->out_state, idio16gpio->base);
	139	if ((*mask >> 8) & 0xFF)
	140	outb(idio16gpio->out_state >> 8, idio16gpio->base + 4);
	141
3906e808	142	raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
9d7ae812 WBG	143	}
9d7ae812 WBG	144
a1184147 WBG	145	static void idio_16_irq_ack(struct irq_data *data)
a1184147 WBG	146	{
a1184147 WBG	147	}
	148
	149	static void idio_16_irq_mask(struct irq_data *data)
	150	{
	151	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
d602ae90	152	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
a1184147 WBG	153	const unsigned long mask = BIT(irqd_to_hwirq(data));
	154	unsigned long flags;
	155
	156	idio16gpio->irq_mask &= ~mask;
	157
	158	if (!idio16gpio->irq_mask) {
3906e808	159	raw_spin_lock_irqsave(&idio16gpio->lock, flags);
a1184147 WBG	160
	161	outb(0, idio16gpio->base + 2);
	162
3906e808	163	raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
a1184147 WBG	164	}
	165	}
	166
	167	static void idio_16_irq_unmask(struct irq_data *data)
	168	{
	169	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
d602ae90	170	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
a1184147 WBG	171	const unsigned long mask = BIT(irqd_to_hwirq(data));
	172	const unsigned long prev_irq_mask = idio16gpio->irq_mask;
	173	unsigned long flags;
	174
	175	idio16gpio->irq_mask \|= mask;
	176
	177	if (!prev_irq_mask) {
3906e808	178	raw_spin_lock_irqsave(&idio16gpio->lock, flags);
a1184147	179
a1184147 WBG	180	inb(idio16gpio->base + 2);
a1184147 WBG	181
3906e808	182	raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
a1184147 WBG	183	}
	184	}
	185
cc0f53d2	186	static int idio_16_irq_set_type(struct irq_data *data, unsigned int flow_type)
a1184147 WBG	187	{
	188	/* The only valid irq types are none and both-edges */
	189	if (flow_type != IRQ_TYPE_NONE &&
	190	(flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
	191	return -EINVAL;
	192
	193	return 0;
	194	}
	195
	196	static struct irq_chip idio_16_irqchip = {
	197	.name = "104-idio-16",
	198	.irq_ack = idio_16_irq_ack,
	199	.irq_mask = idio_16_irq_mask,
	200	.irq_unmask = idio_16_irq_unmask,
	201	.irq_set_type = idio_16_irq_set_type
	202	};
	203
	204	static irqreturn_t idio_16_irq_handler(int irq, void *dev_id)
	205	{
	206	struct idio_16_gpio *const idio16gpio = dev_id;
	207	struct gpio_chip *const chip = &idio16gpio->chip;
	208	int gpio;
	209
	210	for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
dbd1c54f	211	generic_handle_domain_irq(chip->irq.domain, gpio);
a1184147	212
3906e808	213	raw_spin_lock(&idio16gpio->lock);
12b61c9d WBG	214
	215	outb(0, idio16gpio->base + 1);
	216
3906e808	217	raw_spin_unlock(&idio16gpio->lock);
12b61c9d	218
a1184147 WBG	219	return IRQ_HANDLED;
	220	}
	221
e0af4b5e WBG	222	#define IDIO_16_NGPIO 32
	223	static const char *idio_16_names[IDIO_16_NGPIO] = {
	224	"OUT0", "OUT1", "OUT2", "OUT3", "OUT4", "OUT5", "OUT6", "OUT7",
	225	"OUT8", "OUT9", "OUT10", "OUT11", "OUT12", "OUT13", "OUT14", "OUT15",
	226	"IIN0", "IIN1", "IIN2", "IIN3", "IIN4", "IIN5", "IIN6", "IIN7",
	227	"IIN8", "IIN9", "IIN10", "IIN11", "IIN12", "IIN13", "IIN14", "IIN15"
	228	};
	229
82e4613d LW	230	static int idio_16_irq_init_hw(struct gpio_chip *gc)
	231	{
	232	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(gc);
	233
	234	/* Disable IRQ by default */
	235	outb(0, idio16gpio->base + 2);
	236	outb(0, idio16gpio->base + 1);
	237
	238	return 0;
	239	}
	240
86ea8a95	241	static int idio_16_probe(struct device *dev, unsigned int id)
1ceacea2	242	{
1ceacea2	243	struct idio_16_gpio *idio16gpio;
6e0171b4	244	const char *const name = dev_name(dev);
82e4613d	245	struct gpio_irq_chip *girq;
1ceacea2	246	int err;
1ceacea2 WBG	247
	248	idio16gpio = devm_kzalloc(dev, sizeof(*idio16gpio), GFP_KERNEL);
	249	if (!idio16gpio)
	250	return -ENOMEM;
	251
86ea8a95	252	if (!devm_request_region(dev, base[id], IDIO_16_EXTENT, name)) {
cb32389c	253	dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
86ea8a95	254	base[id], base[id] + IDIO_16_EXTENT);
cb32389c	255	return -EBUSY;
1ceacea2 WBG	256	}
1ceacea2 WBG	257
6e0171b4	258	idio16gpio->chip.label = name;
58383c78	259	idio16gpio->chip.parent = dev;
1ceacea2 WBG	260	idio16gpio->chip.owner = THIS_MODULE;
1ceacea2 WBG	261	idio16gpio->chip.base = -1;
e0af4b5e WBG	262	idio16gpio->chip.ngpio = IDIO_16_NGPIO;
e0af4b5e WBG	263	idio16gpio->chip.names = idio_16_names;
1ceacea2 WBG	264	idio16gpio->chip.get_direction = idio_16_gpio_get_direction;
	265	idio16gpio->chip.direction_input = idio_16_gpio_direction_input;
	266	idio16gpio->chip.direction_output = idio_16_gpio_direction_output;
	267	idio16gpio->chip.get = idio_16_gpio_get;
15f59cff	268	idio16gpio->chip.get_multiple = idio_16_gpio_get_multiple;
1ceacea2	269	idio16gpio->chip.set = idio_16_gpio_set;
9d7ae812	270	idio16gpio->chip.set_multiple = idio_16_gpio_set_multiple;
86ea8a95	271	idio16gpio->base = base[id];
1ceacea2 WBG	272	idio16gpio->out_state = 0xFFFF;
1ceacea2 WBG	273
82e4613d LW	274	girq = &idio16gpio->chip.irq;
	275	girq->chip = &idio_16_irqchip;
	276	/* This will let us handle the parent IRQ in the driver */
	277	girq->parent_handler = NULL;
	278	girq->num_parents = 0;
	279	girq->parents = NULL;
	280	girq->default_type = IRQ_TYPE_NONE;
	281	girq->handler = handle_edge_irq;
	282	girq->init_hw = idio_16_irq_init_hw;
	283
3906e808	284	raw_spin_lock_init(&idio16gpio->lock);
1ceacea2	285
837143d3	286	err = devm_gpiochip_add_data(dev, &idio16gpio->chip, idio16gpio);
1ceacea2 WBG	287	if (err) {
1ceacea2 WBG	288	dev_err(dev, "GPIO registering failed (%d)\n", err);
cb32389c	289	return err;
1ceacea2 WBG	290	}
1ceacea2 WBG	291
837143d3 WBG	292	err = devm_request_irq(dev, irq[id], idio_16_irq_handler, 0, name,
837143d3 WBG	293	idio16gpio);
a1184147 WBG	294	if (err) {
a1184147 WBG	295	dev_err(dev, "IRQ handler registering failed (%d)\n", err);
837143d3	296	return err;
a1184147 WBG	297	}
a1184147 WBG	298
1ceacea2 WBG	299	return 0;
	300	}
	301
86ea8a95 WBG	302	static struct isa_driver idio_16_driver = {
86ea8a95 WBG	303	.probe = idio_16_probe,
1ceacea2 WBG	304	.driver = {
	305	.name = "104-idio-16"
	306	},
1ceacea2 WBG	307	};
1ceacea2 WBG	308
86ea8a95	309	module_isa_driver(idio_16_driver, num_idio_16);
1ceacea2 WBG	310
	311	MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
	312	MODULE_DESCRIPTION("ACCES 104-IDIO-16 GPIO driver");
22aeddb5	313	MODULE_LICENSE("GPL v2");