[linux-2.6-block.git] / drivers / gpio / gpio-104-idio-16.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * GPIO driver for the ACCES 104-IDIO-16 family
 * Copyright (C) 2015 William Breathitt Gray
 *
 * This driver supports the following ACCES devices: 104-IDIO-16,
 * 104-IDIO-16E, 104-IDO-16, 104-IDIO-8, 104-IDIO-8E, and 104-IDO-8.
 */
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/irqdesc.h>
#include <linux/isa.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/spinlock.h>

#define IDIO_16_EXTENT 8
#define MAX_NUM_IDIO_16 max_num_isa_dev(IDIO_16_EXTENT)

static unsigned int base[MAX_NUM_IDIO_16];
static unsigned int num_idio_16;
module_param_hw_array(base, uint, ioport, &num_idio_16, 0);
MODULE_PARM_DESC(base, "ACCES 104-IDIO-16 base addresses");

static unsigned int irq[MAX_NUM_IDIO_16];
module_param_hw_array(irq, uint, irq, NULL, 0);
MODULE_PARM_DESC(irq, "ACCES 104-IDIO-16 interrupt line numbers");

/**
 * struct idio_16_gpio - GPIO device private data structure
 * @chip:	instance of the gpio_chip
 * @lock:	synchronization lock to prevent I/O race conditions
 * @irq_mask:	I/O bits affected by interrupts
 * @base:	base port address of the GPIO device
 * @out_state:	output bits state
 */
struct idio_16_gpio {
	struct gpio_chip chip;
	raw_spinlock_t lock;
	unsigned long irq_mask;
	unsigned base;
	unsigned out_state;
};

static int idio_16_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
	if (offset > 15)
		return GPIO_LINE_DIRECTION_IN;

	return GPIO_LINE_DIRECTION_OUT;
}

static int idio_16_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	return 0;
}

static int idio_16_gpio_direction_output(struct gpio_chip *chip,
	unsigned offset, int value)
{
	chip->set(chip, offset, value);
	return 0;
}

static int idio_16_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
	const unsigned mask = BIT(offset-16);

	if (offset < 16)
		return -EINVAL;

	if (offset < 24)
		return !!(inb(idio16gpio->base + 1) & mask);

	return !!(inb(idio16gpio->base + 5) & (mask>>8));
}

static int idio_16_gpio_get_multiple(struct gpio_chip *chip,
	unsigned long *mask, unsigned long *bits)
{
	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);

	*bits = 0;
	if (*mask & GENMASK(23, 16))
		*bits |= (unsigned long)inb(idio16gpio->base + 1) << 16;
	if (*mask & GENMASK(31, 24))
		*bits |= (unsigned long)inb(idio16gpio->base + 5) << 24;

	return 0;
}

static void idio_16_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
	const unsigned mask = BIT(offset);
	unsigned long flags;

	if (offset > 15)
		return;

	raw_spin_lock_irqsave(&idio16gpio->lock, flags);

	if (value)
		idio16gpio->out_state |= mask;
	else
		idio16gpio->out_state &= ~mask;

	if (offset > 7)
		outb(idio16gpio->out_state >> 8, idio16gpio->base + 4);
	else
		outb(idio16gpio->out_state, idio16gpio->base);

	raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
}

static void idio_16_gpio_set_multiple(struct gpio_chip *chip,
	unsigned long *mask, unsigned long *bits)
{
	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
	unsigned long flags;

	raw_spin_lock_irqsave(&idio16gpio->lock, flags);

	idio16gpio->out_state &= ~*mask;
	idio16gpio->out_state |= *mask & *bits;

	if (*mask & 0xFF)
		outb(idio16gpio->out_state, idio16gpio->base);
	if ((*mask >> 8) & 0xFF)
		outb(idio16gpio->out_state >> 8, idio16gpio->base + 4);

	raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
}

static void idio_16_irq_ack(struct irq_data *data)
{
}

static void idio_16_irq_mask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
	const unsigned long mask = BIT(irqd_to_hwirq(data));
	unsigned long flags;

	idio16gpio->irq_mask &= ~mask;

	if (!idio16gpio->irq_mask) {
		raw_spin_lock_irqsave(&idio16gpio->lock, flags);

		outb(0, idio16gpio->base + 2);

		raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
	}
}

static void idio_16_irq_unmask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
	const unsigned long mask = BIT(irqd_to_hwirq(data));
	const unsigned long prev_irq_mask = idio16gpio->irq_mask;
	unsigned long flags;

	idio16gpio->irq_mask |= mask;

	if (!prev_irq_mask) {
		raw_spin_lock_irqsave(&idio16gpio->lock, flags);

		inb(idio16gpio->base + 2);

		raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
	}
}

static int idio_16_irq_set_type(struct irq_data *data, unsigned flow_type)
{
	/* The only valid irq types are none and both-edges */
	if (flow_type != IRQ_TYPE_NONE &&
		(flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
		return -EINVAL;

	return 0;
}

static struct irq_chip idio_16_irqchip = {
	.name = "104-idio-16",
	.irq_ack = idio_16_irq_ack,
	.irq_mask = idio_16_irq_mask,
	.irq_unmask = idio_16_irq_unmask,
	.irq_set_type = idio_16_irq_set_type
};

static irqreturn_t idio_16_irq_handler(int irq, void *dev_id)
{
	struct idio_16_gpio *const idio16gpio = dev_id;
	struct gpio_chip *const chip = &idio16gpio->chip;
	int gpio;

	for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
		generic_handle_irq(irq_find_mapping(chip->irq.domain, gpio));

	raw_spin_lock(&idio16gpio->lock);

	outb(0, idio16gpio->base + 1);

	raw_spin_unlock(&idio16gpio->lock);

	return IRQ_HANDLED;
}

#define IDIO_16_NGPIO 32
static const char *idio_16_names[IDIO_16_NGPIO] = {
	"OUT0", "OUT1", "OUT2", "OUT3", "OUT4", "OUT5", "OUT6", "OUT7",
	"OUT8", "OUT9", "OUT10", "OUT11", "OUT12", "OUT13", "OUT14", "OUT15",
	"IIN0", "IIN1", "IIN2", "IIN3", "IIN4", "IIN5", "IIN6", "IIN7",
	"IIN8", "IIN9", "IIN10", "IIN11", "IIN12", "IIN13", "IIN14", "IIN15"
};

static int idio_16_irq_init_hw(struct gpio_chip *gc)
{
	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(gc);

	/* Disable IRQ by default */
	outb(0, idio16gpio->base + 2);
	outb(0, idio16gpio->base + 1);

	return 0;
}

static int idio_16_probe(struct device *dev, unsigned int id)
{
	struct idio_16_gpio *idio16gpio;
	const char *const name = dev_name(dev);
	struct gpio_irq_chip *girq;
	int err;

	idio16gpio = devm_kzalloc(dev, sizeof(*idio16gpio), GFP_KERNEL);
	if (!idio16gpio)
		return -ENOMEM;

	if (!devm_request_region(dev, base[id], IDIO_16_EXTENT, name)) {
		dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
			base[id], base[id] + IDIO_16_EXTENT);
		return -EBUSY;
	}

	idio16gpio->chip.label = name;
	idio16gpio->chip.parent = dev;
	idio16gpio->chip.owner = THIS_MODULE;
	idio16gpio->chip.base = -1;
	idio16gpio->chip.ngpio = IDIO_16_NGPIO;
	idio16gpio->chip.names = idio_16_names;
	idio16gpio->chip.get_direction = idio_16_gpio_get_direction;
	idio16gpio->chip.direction_input = idio_16_gpio_direction_input;
	idio16gpio->chip.direction_output = idio_16_gpio_direction_output;
	idio16gpio->chip.get = idio_16_gpio_get;
	idio16gpio->chip.get_multiple = idio_16_gpio_get_multiple;
	idio16gpio->chip.set = idio_16_gpio_set;
	idio16gpio->chip.set_multiple = idio_16_gpio_set_multiple;
	idio16gpio->base = base[id];
	idio16gpio->out_state = 0xFFFF;

	girq = &idio16gpio->chip.irq;
	girq->chip = &idio_16_irqchip;
	/* This will let us handle the parent IRQ in the driver */
	girq->parent_handler = NULL;
	girq->num_parents = 0;
	girq->parents = NULL;
	girq->default_type = IRQ_TYPE_NONE;
	girq->handler = handle_edge_irq;
	girq->init_hw = idio_16_irq_init_hw;

	raw_spin_lock_init(&idio16gpio->lock);

	err = devm_gpiochip_add_data(dev, &idio16gpio->chip, idio16gpio);
	if (err) {
		dev_err(dev, "GPIO registering failed (%d)\n", err);
		return err;
	}

	err = devm_request_irq(dev, irq[id], idio_16_irq_handler, 0, name,
		idio16gpio);
	if (err) {
		dev_err(dev, "IRQ handler registering failed (%d)\n", err);
		return err;
	}

	return 0;
}

static struct isa_driver idio_16_driver = {
	.probe = idio_16_probe,
	.driver = {
		.name = "104-idio-16"
	},
};

module_isa_driver(idio_16_driver, num_idio_16);

MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
MODULE_DESCRIPTION("ACCES 104-IDIO-16 GPIO driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
1ceacea2 WBG	2	/*
	3	* GPIO driver for the ACCES 104-IDIO-16 family
	4	* Copyright (C) 2015 William Breathitt Gray
	5	*
86ea8a95 WBG	6	* This driver supports the following ACCES devices: 104-IDIO-16,
86ea8a95 WBG	7	* 104-IDIO-16E, 104-IDO-16, 104-IDIO-8, 104-IDIO-8E, and 104-IDO-8.
1ceacea2	8	*/
a1184147	9	#include <linux/bitops.h>
1ceacea2 WBG	10	#include <linux/device.h>
	11	#include <linux/errno.h>
	12	#include <linux/gpio/driver.h>
	13	#include <linux/io.h>
	14	#include <linux/ioport.h>
a1184147 WBG	15	#include <linux/interrupt.h>
a1184147 WBG	16	#include <linux/irqdesc.h>
86ea8a95	17	#include <linux/isa.h>
1ceacea2 WBG	18	#include <linux/kernel.h>
	19	#include <linux/module.h>
	20	#include <linux/moduleparam.h>
1ceacea2 WBG	21	#include <linux/spinlock.h>
1ceacea2 WBG	22
86ea8a95 WBG	23	#define IDIO_16_EXTENT 8
	24	#define MAX_NUM_IDIO_16 max_num_isa_dev(IDIO_16_EXTENT)
	25
	26	static unsigned int base[MAX_NUM_IDIO_16];
	27	static unsigned int num_idio_16;
d759f906	28	module_param_hw_array(base, uint, ioport, &num_idio_16, 0);
86ea8a95 WBG	29	MODULE_PARM_DESC(base, "ACCES 104-IDIO-16 base addresses");
	30
	31	static unsigned int irq[MAX_NUM_IDIO_16];
d759f906	32	module_param_hw_array(irq, uint, irq, NULL, 0);
86ea8a95	33	MODULE_PARM_DESC(irq, "ACCES 104-IDIO-16 interrupt line numbers");
1ceacea2 WBG	34
	35	/**
	36	* struct idio_16_gpio - GPIO device private data structure
	37	* @chip: instance of the gpio_chip
a1184147 WBG	38	* @lock: synchronization lock to prevent I/O race conditions
a1184147 WBG	39	* @irq_mask: I/O bits affected by interrupts
1ceacea2	40	* @base: base port address of the GPIO device
1ceacea2 WBG	41	* @out_state: output bits state
	42	*/
	43	struct idio_16_gpio {
	44	struct gpio_chip chip;
3906e808	45	raw_spinlock_t lock;
a1184147	46	unsigned long irq_mask;
1ceacea2	47	unsigned base;
1ceacea2 WBG	48	unsigned out_state;
	49	};
	50
	51	static int idio_16_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
	52	{
	53	if (offset > 15)
e42615ec	54	return GPIO_LINE_DIRECTION_IN;
1ceacea2	55
e42615ec	56	return GPIO_LINE_DIRECTION_OUT;
1ceacea2 WBG	57	}
	58
	59	static int idio_16_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	60	{
	61	return 0;
	62	}
	63
	64	static int idio_16_gpio_direction_output(struct gpio_chip *chip,
	65	unsigned offset, int value)
	66	{
	67	chip->set(chip, offset, value);
	68	return 0;
	69	}
	70
1ceacea2 WBG	71	static int idio_16_gpio_get(struct gpio_chip *chip, unsigned offset)
1ceacea2 WBG	72	{
d602ae90	73	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
6e0171b4	74	const unsigned mask = BIT(offset-16);
1ceacea2 WBG	75
	76	if (offset < 16)
	77	return -EINVAL;
	78
	79	if (offset < 24)
6e0171b4	80	return !!(inb(idio16gpio->base + 1) & mask);
1ceacea2	81
6e0171b4	82	return !!(inb(idio16gpio->base + 5) & (mask>>8));
1ceacea2 WBG	83	}
1ceacea2 WBG	84
15f59cff WBG	85	static int idio_16_gpio_get_multiple(struct gpio_chip *chip,
	86	unsigned long mask, unsigned long bits)
	87	{
	88	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
	89
	90	*bits = 0;
	91	if (*mask & GENMASK(23, 16))
	92	*bits \|= (unsigned long)inb(idio16gpio->base + 1) << 16;
	93	if (*mask & GENMASK(31, 24))
	94	*bits \|= (unsigned long)inb(idio16gpio->base + 5) << 24;
	95
	96	return 0;
	97	}
	98
1ceacea2 WBG	99	static void idio_16_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1ceacea2 WBG	100	{
d602ae90	101	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
6e0171b4	102	const unsigned mask = BIT(offset);
1ceacea2 WBG	103	unsigned long flags;
	104
	105	if (offset > 15)
	106	return;
	107
3906e808	108	raw_spin_lock_irqsave(&idio16gpio->lock, flags);
1ceacea2 WBG	109
1ceacea2 WBG	110	if (value)
6e0171b4	111	idio16gpio->out_state \|= mask;
1ceacea2	112	else
6e0171b4	113	idio16gpio->out_state &= ~mask;
1ceacea2 WBG	114
	115	if (offset > 7)
	116	outb(idio16gpio->out_state >> 8, idio16gpio->base + 4);
	117	else
	118	outb(idio16gpio->out_state, idio16gpio->base);
	119
3906e808	120	raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
1ceacea2 WBG	121	}
1ceacea2 WBG	122
9d7ae812 WBG	123	static void idio_16_gpio_set_multiple(struct gpio_chip *chip,
	124	unsigned long mask, unsigned long bits)
	125	{
	126	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
	127	unsigned long flags;
	128
3906e808	129	raw_spin_lock_irqsave(&idio16gpio->lock, flags);
9d7ae812 WBG	130
	131	idio16gpio->out_state &= ~*mask;
	132	idio16gpio->out_state \|= mask & bits;
	133
	134	if (*mask & 0xFF)
	135	outb(idio16gpio->out_state, idio16gpio->base);
	136	if ((*mask >> 8) & 0xFF)
	137	outb(idio16gpio->out_state >> 8, idio16gpio->base + 4);
	138
3906e808	139	raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
9d7ae812 WBG	140	}
9d7ae812 WBG	141
a1184147 WBG	142	static void idio_16_irq_ack(struct irq_data *data)
a1184147 WBG	143	{
a1184147 WBG	144	}
	145
	146	static void idio_16_irq_mask(struct irq_data *data)
	147	{
	148	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
d602ae90	149	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
a1184147 WBG	150	const unsigned long mask = BIT(irqd_to_hwirq(data));
	151	unsigned long flags;
	152
	153	idio16gpio->irq_mask &= ~mask;
	154
	155	if (!idio16gpio->irq_mask) {
3906e808	156	raw_spin_lock_irqsave(&idio16gpio->lock, flags);
a1184147 WBG	157
	158	outb(0, idio16gpio->base + 2);
	159
3906e808	160	raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
a1184147 WBG	161	}
	162	}
	163
	164	static void idio_16_irq_unmask(struct irq_data *data)
	165	{
	166	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
d602ae90	167	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
a1184147 WBG	168	const unsigned long mask = BIT(irqd_to_hwirq(data));
	169	const unsigned long prev_irq_mask = idio16gpio->irq_mask;
	170	unsigned long flags;
	171
	172	idio16gpio->irq_mask \|= mask;
	173
	174	if (!prev_irq_mask) {
3906e808	175	raw_spin_lock_irqsave(&idio16gpio->lock, flags);
a1184147	176
a1184147 WBG	177	inb(idio16gpio->base + 2);
a1184147 WBG	178
3906e808	179	raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
a1184147 WBG	180	}
	181	}
	182
	183	static int idio_16_irq_set_type(struct irq_data *data, unsigned flow_type)
	184	{
	185	/* The only valid irq types are none and both-edges */
	186	if (flow_type != IRQ_TYPE_NONE &&
	187	(flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
	188	return -EINVAL;
	189
	190	return 0;
	191	}
	192
	193	static struct irq_chip idio_16_irqchip = {
	194	.name = "104-idio-16",
	195	.irq_ack = idio_16_irq_ack,
	196	.irq_mask = idio_16_irq_mask,
	197	.irq_unmask = idio_16_irq_unmask,
	198	.irq_set_type = idio_16_irq_set_type
	199	};
	200
	201	static irqreturn_t idio_16_irq_handler(int irq, void *dev_id)
	202	{
	203	struct idio_16_gpio *const idio16gpio = dev_id;
	204	struct gpio_chip *const chip = &idio16gpio->chip;
	205	int gpio;
	206
	207	for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
f0fbe7bc	208	generic_handle_irq(irq_find_mapping(chip->irq.domain, gpio));
a1184147	209
3906e808	210	raw_spin_lock(&idio16gpio->lock);
12b61c9d WBG	211
	212	outb(0, idio16gpio->base + 1);
	213
3906e808	214	raw_spin_unlock(&idio16gpio->lock);
12b61c9d	215
a1184147 WBG	216	return IRQ_HANDLED;
	217	}
	218
e0af4b5e WBG	219	#define IDIO_16_NGPIO 32
	220	static const char *idio_16_names[IDIO_16_NGPIO] = {
	221	"OUT0", "OUT1", "OUT2", "OUT3", "OUT4", "OUT5", "OUT6", "OUT7",
	222	"OUT8", "OUT9", "OUT10", "OUT11", "OUT12", "OUT13", "OUT14", "OUT15",
	223	"IIN0", "IIN1", "IIN2", "IIN3", "IIN4", "IIN5", "IIN6", "IIN7",
	224	"IIN8", "IIN9", "IIN10", "IIN11", "IIN12", "IIN13", "IIN14", "IIN15"
	225	};
	226
82e4613d LW	227	static int idio_16_irq_init_hw(struct gpio_chip *gc)
	228	{
	229	struct idio_16_gpio *const idio16gpio = gpiochip_get_data(gc);
	230
	231	/* Disable IRQ by default */
	232	outb(0, idio16gpio->base + 2);
	233	outb(0, idio16gpio->base + 1);
	234
	235	return 0;
	236	}
	237
86ea8a95	238	static int idio_16_probe(struct device *dev, unsigned int id)
1ceacea2	239	{
1ceacea2	240	struct idio_16_gpio *idio16gpio;
6e0171b4	241	const char *const name = dev_name(dev);
82e4613d	242	struct gpio_irq_chip *girq;
1ceacea2	243	int err;
1ceacea2 WBG	244
	245	idio16gpio = devm_kzalloc(dev, sizeof(*idio16gpio), GFP_KERNEL);
	246	if (!idio16gpio)
	247	return -ENOMEM;
	248
86ea8a95	249	if (!devm_request_region(dev, base[id], IDIO_16_EXTENT, name)) {
cb32389c	250	dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
86ea8a95	251	base[id], base[id] + IDIO_16_EXTENT);
cb32389c	252	return -EBUSY;
1ceacea2 WBG	253	}
1ceacea2 WBG	254
6e0171b4	255	idio16gpio->chip.label = name;
58383c78	256	idio16gpio->chip.parent = dev;
1ceacea2 WBG	257	idio16gpio->chip.owner = THIS_MODULE;
1ceacea2 WBG	258	idio16gpio->chip.base = -1;
e0af4b5e WBG	259	idio16gpio->chip.ngpio = IDIO_16_NGPIO;
e0af4b5e WBG	260	idio16gpio->chip.names = idio_16_names;
1ceacea2 WBG	261	idio16gpio->chip.get_direction = idio_16_gpio_get_direction;
	262	idio16gpio->chip.direction_input = idio_16_gpio_direction_input;
	263	idio16gpio->chip.direction_output = idio_16_gpio_direction_output;
	264	idio16gpio->chip.get = idio_16_gpio_get;
15f59cff	265	idio16gpio->chip.get_multiple = idio_16_gpio_get_multiple;
1ceacea2	266	idio16gpio->chip.set = idio_16_gpio_set;
9d7ae812	267	idio16gpio->chip.set_multiple = idio_16_gpio_set_multiple;
86ea8a95	268	idio16gpio->base = base[id];
1ceacea2 WBG	269	idio16gpio->out_state = 0xFFFF;
1ceacea2 WBG	270
82e4613d LW	271	girq = &idio16gpio->chip.irq;
	272	girq->chip = &idio_16_irqchip;
	273	/* This will let us handle the parent IRQ in the driver */
	274	girq->parent_handler = NULL;
	275	girq->num_parents = 0;
	276	girq->parents = NULL;
	277	girq->default_type = IRQ_TYPE_NONE;
	278	girq->handler = handle_edge_irq;
	279	girq->init_hw = idio_16_irq_init_hw;
	280
3906e808	281	raw_spin_lock_init(&idio16gpio->lock);
1ceacea2	282
837143d3	283	err = devm_gpiochip_add_data(dev, &idio16gpio->chip, idio16gpio);
1ceacea2 WBG	284	if (err) {
1ceacea2 WBG	285	dev_err(dev, "GPIO registering failed (%d)\n", err);
cb32389c	286	return err;
1ceacea2 WBG	287	}
1ceacea2 WBG	288
837143d3 WBG	289	err = devm_request_irq(dev, irq[id], idio_16_irq_handler, 0, name,
837143d3 WBG	290	idio16gpio);
a1184147 WBG	291	if (err) {
a1184147 WBG	292	dev_err(dev, "IRQ handler registering failed (%d)\n", err);
837143d3	293	return err;
a1184147 WBG	294	}
a1184147 WBG	295
1ceacea2 WBG	296	return 0;
	297	}
	298
86ea8a95 WBG	299	static struct isa_driver idio_16_driver = {
86ea8a95 WBG	300	.probe = idio_16_probe,
1ceacea2 WBG	301	.driver = {
	302	.name = "104-idio-16"
	303	},
1ceacea2 WBG	304	};
1ceacea2 WBG	305
86ea8a95	306	module_isa_driver(idio_16_driver, num_idio_16);
1ceacea2 WBG	307
	308	MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
	309	MODULE_DESCRIPTION("ACCES 104-IDIO-16 GPIO driver");
22aeddb5	310	MODULE_LICENSE("GPL v2");