[linux-2.6-block.git] / drivers / gpio / gpio-104-idi-48.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * GPIO driver for the ACCES 104-IDI-48 family
 * Copyright (C) 2015 William Breathitt Gray
 *
 * This driver supports the following ACCES devices: 104-IDI-48A,
 * 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
 */
#include <linux/bitmap.h>
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/irqdesc.h>
#include <linux/isa.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/spinlock.h>

#define IDI_48_EXTENT 8
#define MAX_NUM_IDI_48 max_num_isa_dev(IDI_48_EXTENT)

static unsigned int base[MAX_NUM_IDI_48];
static unsigned int num_idi_48;
module_param_hw_array(base, uint, ioport, &num_idi_48, 0);
MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");

static unsigned int irq[MAX_NUM_IDI_48];
module_param_hw_array(irq, uint, irq, NULL, 0);
MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");

/**
 * struct idi_48_gpio - GPIO device private data structure
 * @chip:	instance of the gpio_chip
 * @lock:	synchronization lock to prevent I/O race conditions
 * @ack_lock:	synchronization lock to prevent IRQ handler race conditions
 * @irq_mask:	input bits affected by interrupts
 * @base:	base port address of the GPIO device
 * @cos_enb:	Change-Of-State IRQ enable boundaries mask
 */
struct idi_48_gpio {
	struct gpio_chip chip;
	raw_spinlock_t lock;
	spinlock_t ack_lock;
	unsigned char irq_mask[6];
	unsigned base;
	unsigned char cos_enb;
};

static int idi_48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
	return 1;
}

static int idi_48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	return 0;
}

static int idi_48_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
	unsigned i;
	const unsigned register_offset[6] = { 0, 1, 2, 4, 5, 6 };
	unsigned base_offset;
	unsigned mask;

	for (i = 0; i < 48; i += 8)
		if (offset < i + 8) {
			base_offset = register_offset[i / 8];
			mask = BIT(offset - i);

			return !!(inb(idi48gpio->base + base_offset) & mask);
		}

	/* The following line should never execute since offset < 48 */
	return 0;
}

static int idi_48_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
	unsigned long *bits)
{
	struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
	size_t i;
	static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };
	const unsigned int gpio_reg_size = 8;
	unsigned int bits_offset;
	size_t word_index;
	unsigned int word_offset;
	unsigned long word_mask;
	const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
	unsigned long port_state;

	/* clear bits array to a clean slate */
	bitmap_zero(bits, chip->ngpio);

	/* get bits are evaluated a gpio port register at a time */
	for (i = 0; i < ARRAY_SIZE(ports); i++) {
		/* gpio offset in bits array */
		bits_offset = i * gpio_reg_size;

		/* word index for bits array */
		word_index = BIT_WORD(bits_offset);

		/* gpio offset within current word of bits array */
		word_offset = bits_offset % BITS_PER_LONG;

		/* mask of get bits for current gpio within current word */
		word_mask = mask[word_index] & (port_mask << word_offset);
		if (!word_mask) {
			/* no get bits in this port so skip to next one */
			continue;
		}

		/* read bits from current gpio port */
		port_state = inb(idi48gpio->base + ports[i]);

		/* store acquired bits at respective bits array offset */
		bits[word_index] |= (port_state << word_offset) & word_mask;
	}

	return 0;
}

static void idi_48_irq_ack(struct irq_data *data)
{
}

static void idi_48_irq_mask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
	const unsigned offset = irqd_to_hwirq(data);
	unsigned i;
	unsigned mask;
	unsigned boundary;
	unsigned long flags;

	for (i = 0; i < 48; i += 8)
		if (offset < i + 8) {
			mask = BIT(offset - i);
			boundary = i / 8;

			idi48gpio->irq_mask[boundary] &= ~mask;

			if (!idi48gpio->irq_mask[boundary]) {
				idi48gpio->cos_enb &= ~BIT(boundary);

				raw_spin_lock_irqsave(&idi48gpio->lock, flags);

				outb(idi48gpio->cos_enb, idi48gpio->base + 7);

				raw_spin_unlock_irqrestore(&idi48gpio->lock,
						           flags);
			}

			return;
		}
}

static void idi_48_irq_unmask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
	const unsigned offset = irqd_to_hwirq(data);
	unsigned i;
	unsigned mask;
	unsigned boundary;
	unsigned prev_irq_mask;
	unsigned long flags;

	for (i = 0; i < 48; i += 8)
		if (offset < i + 8) {
			mask = BIT(offset - i);
			boundary = i / 8;
			prev_irq_mask = idi48gpio->irq_mask[boundary];

			idi48gpio->irq_mask[boundary] |= mask;

			if (!prev_irq_mask) {
				idi48gpio->cos_enb |= BIT(boundary);

				raw_spin_lock_irqsave(&idi48gpio->lock, flags);

				outb(idi48gpio->cos_enb, idi48gpio->base + 7);

				raw_spin_unlock_irqrestore(&idi48gpio->lock,
						           flags);
			}

			return;
		}
}

static int idi_48_irq_set_type(struct irq_data *data, unsigned flow_type)
{
	/* The only valid irq types are none and both-edges */
	if (flow_type != IRQ_TYPE_NONE &&
		(flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
		return -EINVAL;

	return 0;
}

static struct irq_chip idi_48_irqchip = {
	.name = "104-idi-48",
	.irq_ack = idi_48_irq_ack,
	.irq_mask = idi_48_irq_mask,
	.irq_unmask = idi_48_irq_unmask,
	.irq_set_type = idi_48_irq_set_type
};

static irqreturn_t idi_48_irq_handler(int irq, void *dev_id)
{
	struct idi_48_gpio *const idi48gpio = dev_id;
	unsigned long cos_status;
	unsigned long boundary;
	unsigned long irq_mask;
	unsigned long bit_num;
	unsigned long gpio;
	struct gpio_chip *const chip = &idi48gpio->chip;

	spin_lock(&idi48gpio->ack_lock);

	raw_spin_lock(&idi48gpio->lock);

	cos_status = inb(idi48gpio->base + 7);

	raw_spin_unlock(&idi48gpio->lock);

	/* IRQ Status (bit 6) is active low (0 = IRQ generated by device) */
	if (cos_status & BIT(6)) {
		spin_unlock(&idi48gpio->ack_lock);
		return IRQ_NONE;
	}

	/* Bit 0-5 indicate which Change-Of-State boundary triggered the IRQ */
	cos_status &= 0x3F;

	for_each_set_bit(boundary, &cos_status, 6) {
		irq_mask = idi48gpio->irq_mask[boundary];

		for_each_set_bit(bit_num, &irq_mask, 8) {
			gpio = bit_num + boundary * 8;

			generic_handle_irq(irq_find_mapping(chip->irq.domain,
				gpio));
		}
	}

	spin_unlock(&idi48gpio->ack_lock);

	return IRQ_HANDLED;
}

#define IDI48_NGPIO 48
static const char *idi48_names[IDI48_NGPIO] = {
	"Bit 0 A", "Bit 1 A", "Bit 2 A", "Bit 3 A", "Bit 4 A", "Bit 5 A",
	"Bit 6 A", "Bit 7 A", "Bit 8 A", "Bit 9 A", "Bit 10 A", "Bit 11 A",
	"Bit 12 A", "Bit 13 A", "Bit 14 A", "Bit 15 A",	"Bit 16 A", "Bit 17 A",
	"Bit 18 A", "Bit 19 A", "Bit 20 A", "Bit 21 A", "Bit 22 A", "Bit 23 A",
	"Bit 0 B", "Bit 1 B", "Bit 2 B", "Bit 3 B", "Bit 4 B", "Bit 5 B",
	"Bit 6 B", "Bit 7 B", "Bit 8 B", "Bit 9 B", "Bit 10 B", "Bit 11 B",
	"Bit 12 B", "Bit 13 B", "Bit 14 B", "Bit 15 B",	"Bit 16 B", "Bit 17 B",
	"Bit 18 B", "Bit 19 B", "Bit 20 B", "Bit 21 B", "Bit 22 B", "Bit 23 B"
};

static int idi_48_probe(struct device *dev, unsigned int id)
{
	struct idi_48_gpio *idi48gpio;
	const char *const name = dev_name(dev);
	int err;

	idi48gpio = devm_kzalloc(dev, sizeof(*idi48gpio), GFP_KERNEL);
	if (!idi48gpio)
		return -ENOMEM;

	if (!devm_request_region(dev, base[id], IDI_48_EXTENT, name)) {
		dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
			base[id], base[id] + IDI_48_EXTENT);
		return -EBUSY;
	}

	idi48gpio->chip.label = name;
	idi48gpio->chip.parent = dev;
	idi48gpio->chip.owner = THIS_MODULE;
	idi48gpio->chip.base = -1;
	idi48gpio->chip.ngpio = IDI48_NGPIO;
	idi48gpio->chip.names = idi48_names;
	idi48gpio->chip.get_direction = idi_48_gpio_get_direction;
	idi48gpio->chip.direction_input = idi_48_gpio_direction_input;
	idi48gpio->chip.get = idi_48_gpio_get;
	idi48gpio->chip.get_multiple = idi_48_gpio_get_multiple;
	idi48gpio->base = base[id];

	raw_spin_lock_init(&idi48gpio->lock);
	spin_lock_init(&idi48gpio->ack_lock);

	err = devm_gpiochip_add_data(dev, &idi48gpio->chip, idi48gpio);
	if (err) {
		dev_err(dev, "GPIO registering failed (%d)\n", err);
		return err;
	}

	/* Disable IRQ by default */
	outb(0, base[id] + 7);
	inb(base[id] + 7);

	err = gpiochip_irqchip_add(&idi48gpio->chip, &idi_48_irqchip, 0,
		handle_edge_irq, IRQ_TYPE_NONE);
	if (err) {
		dev_err(dev, "Could not add irqchip (%d)\n", err);
		return err;
	}

	err = devm_request_irq(dev, irq[id], idi_48_irq_handler, IRQF_SHARED,
		name, idi48gpio);
	if (err) {
		dev_err(dev, "IRQ handler registering failed (%d)\n", err);
		return err;
	}

	return 0;
}

static struct isa_driver idi_48_driver = {
	.probe = idi_48_probe,
	.driver = {
		.name = "104-idi-48"
	},
};
module_isa_driver(idi_48_driver, num_idi_48);

MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
MODULE_DESCRIPTION("ACCES 104-IDI-48 GPIO driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
6ddcf9b4 WBG	2	/*
	3	* GPIO driver for the ACCES 104-IDI-48 family
	4	* Copyright (C) 2015 William Breathitt Gray
	5	*
72bf7443 WBG	6	* This driver supports the following ACCES devices: 104-IDI-48A,
72bf7443 WBG	7	* 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
6ddcf9b4	8	*/
f72b1071	9	#include <linux/bitmap.h>
6ddcf9b4 WBG	10	#include <linux/bitops.h>
	11	#include <linux/device.h>
	12	#include <linux/errno.h>
	13	#include <linux/gpio/driver.h>
	14	#include <linux/io.h>
	15	#include <linux/ioport.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/irqdesc.h>
72bf7443	18	#include <linux/isa.h>
6ddcf9b4 WBG	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/moduleparam.h>
6ddcf9b4 WBG	22	#include <linux/spinlock.h>
6ddcf9b4 WBG	23
72bf7443 WBG	24	#define IDI_48_EXTENT 8
	25	#define MAX_NUM_IDI_48 max_num_isa_dev(IDI_48_EXTENT)
	26
	27	static unsigned int base[MAX_NUM_IDI_48];
	28	static unsigned int num_idi_48;
d759f906	29	module_param_hw_array(base, uint, ioport, &num_idi_48, 0);
72bf7443 WBG	30	MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");
	31
	32	static unsigned int irq[MAX_NUM_IDI_48];
d759f906	33	module_param_hw_array(irq, uint, irq, NULL, 0);
72bf7443	34	MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
6ddcf9b4 WBG	35
	36	/**
	37	* struct idi_48_gpio - GPIO device private data structure
	38	* @chip: instance of the gpio_chip
	39	* @lock: synchronization lock to prevent I/O race conditions
9ae48210	40	* @ack_lock: synchronization lock to prevent IRQ handler race conditions
6ddcf9b4 WBG	41	* @irq_mask: input bits affected by interrupts
6ddcf9b4 WBG	42	* @base: base port address of the GPIO device
6ddcf9b4 WBG	43	* @cos_enb: Change-Of-State IRQ enable boundaries mask
	44	*/
	45	struct idi_48_gpio {
	46	struct gpio_chip chip;
e1e37d6c	47	raw_spinlock_t lock;
9ae48210	48	spinlock_t ack_lock;
6ddcf9b4 WBG	49	unsigned char irq_mask[6];
6ddcf9b4 WBG	50	unsigned base;
6ddcf9b4 WBG	51	unsigned char cos_enb;
	52	};
	53
	54	static int idi_48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
	55	{
	56	return 1;
	57	}
	58
	59	static int idi_48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	60	{
	61	return 0;
	62	}
	63
6ddcf9b4 WBG	64	static int idi_48_gpio_get(struct gpio_chip *chip, unsigned offset)
6ddcf9b4 WBG	65	{
1f36bec5	66	struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
6ddcf9b4 WBG	67	unsigned i;
	68	const unsigned register_offset[6] = { 0, 1, 2, 4, 5, 6 };
	69	unsigned base_offset;
	70	unsigned mask;
	71
	72	for (i = 0; i < 48; i += 8)
	73	if (offset < i + 8) {
	74	base_offset = register_offset[i / 8];
	75	mask = BIT(offset - i);
	76
	77	return !!(inb(idi48gpio->base + base_offset) & mask);
	78	}
	79
	80	/* The following line should never execute since offset < 48 */
	81	return 0;
	82	}
	83
f72b1071 WBG	84	static int idi_48_gpio_get_multiple(struct gpio_chip chip, unsigned long mask,
	85	unsigned long *bits)
	86	{
	87	struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
	88	size_t i;
413f9e99	89	static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };
f72b1071 WBG	90	const unsigned int gpio_reg_size = 8;
	91	unsigned int bits_offset;
	92	size_t word_index;
	93	unsigned int word_offset;
	94	unsigned long word_mask;
	95	const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
	96	unsigned long port_state;
	97
	98	/* clear bits array to a clean slate */
	99	bitmap_zero(bits, chip->ngpio);
	100
	101	/* get bits are evaluated a gpio port register at a time */
	102	for (i = 0; i < ARRAY_SIZE(ports); i++) {
	103	/* gpio offset in bits array */
	104	bits_offset = i * gpio_reg_size;
	105
	106	/* word index for bits array */
	107	word_index = BIT_WORD(bits_offset);
	108
	109	/* gpio offset within current word of bits array */
	110	word_offset = bits_offset % BITS_PER_LONG;
	111
	112	/* mask of get bits for current gpio within current word */
	113	word_mask = mask[word_index] & (port_mask << word_offset);
	114	if (!word_mask) {
	115	/* no get bits in this port so skip to next one */
	116	continue;
	117	}
	118
	119	/* read bits from current gpio port */
	120	port_state = inb(idi48gpio->base + ports[i]);
	121
	122	/* store acquired bits at respective bits array offset */
b7f53f67	123	bits[word_index] \|= (port_state << word_offset) & word_mask;
f72b1071 WBG	124	}
	125
	126	return 0;
	127	}
	128
6ddcf9b4 WBG	129	static void idi_48_irq_ack(struct irq_data *data)
6ddcf9b4 WBG	130	{
6ddcf9b4 WBG	131	}
	132
	133	static void idi_48_irq_mask(struct irq_data *data)
	134	{
	135	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1f36bec5	136	struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
6ddcf9b4 WBG	137	const unsigned offset = irqd_to_hwirq(data);
	138	unsigned i;
	139	unsigned mask;
	140	unsigned boundary;
	141	unsigned long flags;
	142
	143	for (i = 0; i < 48; i += 8)
	144	if (offset < i + 8) {
	145	mask = BIT(offset - i);
	146	boundary = i / 8;
	147
	148	idi48gpio->irq_mask[boundary] &= ~mask;
	149
	150	if (!idi48gpio->irq_mask[boundary]) {
	151	idi48gpio->cos_enb &= ~BIT(boundary);
	152
e1e37d6c	153	raw_spin_lock_irqsave(&idi48gpio->lock, flags);
6ddcf9b4 WBG	154
	155	outb(idi48gpio->cos_enb, idi48gpio->base + 7);
	156
e1e37d6c JC	157	raw_spin_unlock_irqrestore(&idi48gpio->lock,
e1e37d6c JC	158	flags);
6ddcf9b4 WBG	159	}
	160
	161	return;
	162	}
	163	}
	164
	165	static void idi_48_irq_unmask(struct irq_data *data)
	166	{
	167	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1f36bec5	168	struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
6ddcf9b4 WBG	169	const unsigned offset = irqd_to_hwirq(data);
	170	unsigned i;
	171	unsigned mask;
	172	unsigned boundary;
	173	unsigned prev_irq_mask;
	174	unsigned long flags;
	175
	176	for (i = 0; i < 48; i += 8)
	177	if (offset < i + 8) {
	178	mask = BIT(offset - i);
	179	boundary = i / 8;
	180	prev_irq_mask = idi48gpio->irq_mask[boundary];
	181
	182	idi48gpio->irq_mask[boundary] \|= mask;
	183
	184	if (!prev_irq_mask) {
	185	idi48gpio->cos_enb \|= BIT(boundary);
	186
e1e37d6c	187	raw_spin_lock_irqsave(&idi48gpio->lock, flags);
6ddcf9b4 WBG	188
	189	outb(idi48gpio->cos_enb, idi48gpio->base + 7);
	190
e1e37d6c JC	191	raw_spin_unlock_irqrestore(&idi48gpio->lock,
e1e37d6c JC	192	flags);
6ddcf9b4 WBG	193	}
	194
	195	return;
	196	}
	197	}
	198
	199	static int idi_48_irq_set_type(struct irq_data *data, unsigned flow_type)
	200	{
	201	/* The only valid irq types are none and both-edges */
	202	if (flow_type != IRQ_TYPE_NONE &&
	203	(flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
	204	return -EINVAL;
	205
	206	return 0;
	207	}
	208
	209	static struct irq_chip idi_48_irqchip = {
	210	.name = "104-idi-48",
	211	.irq_ack = idi_48_irq_ack,
	212	.irq_mask = idi_48_irq_mask,
	213	.irq_unmask = idi_48_irq_unmask,
	214	.irq_set_type = idi_48_irq_set_type
	215	};
	216
	217	static irqreturn_t idi_48_irq_handler(int irq, void *dev_id)
	218	{
	219	struct idi_48_gpio *const idi48gpio = dev_id;
	220	unsigned long cos_status;
	221	unsigned long boundary;
	222	unsigned long irq_mask;
	223	unsigned long bit_num;
	224	unsigned long gpio;
	225	struct gpio_chip *const chip = &idi48gpio->chip;
	226
9ae48210 WBG	227	spin_lock(&idi48gpio->ack_lock);
9ae48210 WBG	228
e1e37d6c	229	raw_spin_lock(&idi48gpio->lock);
6ddcf9b4 WBG	230
	231	cos_status = inb(idi48gpio->base + 7);
	232
e1e37d6c	233	raw_spin_unlock(&idi48gpio->lock);
6ddcf9b4 WBG	234
6ddcf9b4 WBG	235	/* IRQ Status (bit 6) is active low (0 = IRQ generated by device) */
9ae48210 WBG	236	if (cos_status & BIT(6)) {
9ae48210 WBG	237	spin_unlock(&idi48gpio->ack_lock);
6ddcf9b4	238	return IRQ_NONE;
9ae48210	239	}
6ddcf9b4 WBG	240
	241	/* Bit 0-5 indicate which Change-Of-State boundary triggered the IRQ */
	242	cos_status &= 0x3F;
	243
	244	for_each_set_bit(boundary, &cos_status, 6) {
	245	irq_mask = idi48gpio->irq_mask[boundary];
	246
	247	for_each_set_bit(bit_num, &irq_mask, 8) {
	248	gpio = bit_num + boundary * 8;
	249
f0fbe7bc	250	generic_handle_irq(irq_find_mapping(chip->irq.domain,
6ddcf9b4 WBG	251	gpio));
	252	}
	253	}
	254
9ae48210 WBG	255	spin_unlock(&idi48gpio->ack_lock);
9ae48210 WBG	256
6ddcf9b4 WBG	257	return IRQ_HANDLED;
	258	}
	259
a71dc253 WBG	260	#define IDI48_NGPIO 48
	261	static const char *idi48_names[IDI48_NGPIO] = {
	262	"Bit 0 A", "Bit 1 A", "Bit 2 A", "Bit 3 A", "Bit 4 A", "Bit 5 A",
	263	"Bit 6 A", "Bit 7 A", "Bit 8 A", "Bit 9 A", "Bit 10 A", "Bit 11 A",
	264	"Bit 12 A", "Bit 13 A", "Bit 14 A", "Bit 15 A", "Bit 16 A", "Bit 17 A",
	265	"Bit 18 A", "Bit 19 A", "Bit 20 A", "Bit 21 A", "Bit 22 A", "Bit 23 A",
	266	"Bit 0 B", "Bit 1 B", "Bit 2 B", "Bit 3 B", "Bit 4 B", "Bit 5 B",
	267	"Bit 6 B", "Bit 7 B", "Bit 8 B", "Bit 9 B", "Bit 10 B", "Bit 11 B",
	268	"Bit 12 B", "Bit 13 B", "Bit 14 B", "Bit 15 B", "Bit 16 B", "Bit 17 B",
	269	"Bit 18 B", "Bit 19 B", "Bit 20 B", "Bit 21 B", "Bit 22 B", "Bit 23 B"
	270	};
	271
72bf7443	272	static int idi_48_probe(struct device *dev, unsigned int id)
6ddcf9b4	273	{
6ddcf9b4	274	struct idi_48_gpio *idi48gpio;
6ddcf9b4 WBG	275	const char *const name = dev_name(dev);
6ddcf9b4 WBG	276	int err;
6ddcf9b4 WBG	277
	278	idi48gpio = devm_kzalloc(dev, sizeof(*idi48gpio), GFP_KERNEL);
	279	if (!idi48gpio)
	280	return -ENOMEM;
	281
72bf7443	282	if (!devm_request_region(dev, base[id], IDI_48_EXTENT, name)) {
5cfc0576	283	dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
72bf7443	284	base[id], base[id] + IDI_48_EXTENT);
5cfc0576	285	return -EBUSY;
6ddcf9b4 WBG	286	}
	287
	288	idi48gpio->chip.label = name;
	289	idi48gpio->chip.parent = dev;
	290	idi48gpio->chip.owner = THIS_MODULE;
	291	idi48gpio->chip.base = -1;
a71dc253 WBG	292	idi48gpio->chip.ngpio = IDI48_NGPIO;
a71dc253 WBG	293	idi48gpio->chip.names = idi48_names;
6ddcf9b4 WBG	294	idi48gpio->chip.get_direction = idi_48_gpio_get_direction;
	295	idi48gpio->chip.direction_input = idi_48_gpio_direction_input;
	296	idi48gpio->chip.get = idi_48_gpio_get;
f72b1071	297	idi48gpio->chip.get_multiple = idi_48_gpio_get_multiple;
72bf7443	298	idi48gpio->base = base[id];
6ddcf9b4	299
e1e37d6c	300	raw_spin_lock_init(&idi48gpio->lock);
053ae649	301	spin_lock_init(&idi48gpio->ack_lock);
6ddcf9b4	302
e43fee60	303	err = devm_gpiochip_add_data(dev, &idi48gpio->chip, idi48gpio);
6ddcf9b4 WBG	304	if (err) {
6ddcf9b4 WBG	305	dev_err(dev, "GPIO registering failed (%d)\n", err);
5cfc0576	306	return err;
6ddcf9b4 WBG	307	}
	308
	309	/* Disable IRQ by default */
72bf7443 WBG	310	outb(0, base[id] + 7);
72bf7443 WBG	311	inb(base[id] + 7);
6ddcf9b4 WBG	312
	313	err = gpiochip_irqchip_add(&idi48gpio->chip, &idi_48_irqchip, 0,
	314	handle_edge_irq, IRQ_TYPE_NONE);
	315	if (err) {
	316	dev_err(dev, "Could not add irqchip (%d)\n", err);
e43fee60	317	return err;
6ddcf9b4 WBG	318	}
6ddcf9b4 WBG	319
e43fee60 WBG	320	err = devm_request_irq(dev, irq[id], idi_48_irq_handler, IRQF_SHARED,
e43fee60 WBG	321	name, idi48gpio);
6ddcf9b4 WBG	322	if (err) {
6ddcf9b4 WBG	323	dev_err(dev, "IRQ handler registering failed (%d)\n", err);
e43fee60	324	return err;
6ddcf9b4 WBG	325	}
6ddcf9b4 WBG	326
6ddcf9b4 WBG	327	return 0;
	328	}
	329
72bf7443 WBG	330	static struct isa_driver idi_48_driver = {
72bf7443 WBG	331	.probe = idi_48_probe,
6ddcf9b4 WBG	332	.driver = {
	333	.name = "104-idi-48"
	334	},
6ddcf9b4	335	};
72bf7443	336	module_isa_driver(idi_48_driver, num_idi_48);
6ddcf9b4 WBG	337
	338	MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
	339	MODULE_DESCRIPTION("ACCES 104-IDI-48 GPIO driver");
22aeddb5	340	MODULE_LICENSE("GPL v2");