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6ddcf9b4 WBG |
1 | /* |
2 | * GPIO driver for the ACCES 104-IDI-48 family | |
3 | * Copyright (C) 2015 William Breathitt Gray | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License, version 2, as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
12 | * General Public License for more details. | |
13 | */ | |
14 | #include <linux/bitops.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/gpio/driver.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/irqdesc.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/moduleparam.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/spinlock.h> | |
27 | ||
28 | static unsigned idi_48_base; | |
29 | module_param(idi_48_base, uint, 0); | |
30 | MODULE_PARM_DESC(idi_48_base, "ACCES 104-IDI-48 base address"); | |
31 | static unsigned idi_48_irq; | |
32 | module_param(idi_48_irq, uint, 0); | |
33 | MODULE_PARM_DESC(idi_48_irq, "ACCES 104-IDI-48 interrupt line number"); | |
34 | ||
35 | /** | |
36 | * struct idi_48_gpio - GPIO device private data structure | |
37 | * @chip: instance of the gpio_chip | |
38 | * @lock: synchronization lock to prevent I/O race conditions | |
9ae48210 | 39 | * @ack_lock: synchronization lock to prevent IRQ handler race conditions |
6ddcf9b4 WBG |
40 | * @irq_mask: input bits affected by interrupts |
41 | * @base: base port address of the GPIO device | |
6ddcf9b4 WBG |
42 | * @irq: Interrupt line number |
43 | * @cos_enb: Change-Of-State IRQ enable boundaries mask | |
44 | */ | |
45 | struct idi_48_gpio { | |
46 | struct gpio_chip chip; | |
47 | spinlock_t lock; | |
9ae48210 | 48 | spinlock_t ack_lock; |
6ddcf9b4 WBG |
49 | unsigned char irq_mask[6]; |
50 | unsigned base; | |
6ddcf9b4 WBG |
51 | unsigned irq; |
52 | unsigned char cos_enb; | |
53 | }; | |
54 | ||
55 | static int idi_48_gpio_get_direction(struct gpio_chip *chip, unsigned offset) | |
56 | { | |
57 | return 1; | |
58 | } | |
59 | ||
60 | static int idi_48_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
61 | { | |
62 | return 0; | |
63 | } | |
64 | ||
6ddcf9b4 WBG |
65 | static int idi_48_gpio_get(struct gpio_chip *chip, unsigned offset) |
66 | { | |
1f36bec5 | 67 | struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip); |
6ddcf9b4 WBG |
68 | unsigned i; |
69 | const unsigned register_offset[6] = { 0, 1, 2, 4, 5, 6 }; | |
70 | unsigned base_offset; | |
71 | unsigned mask; | |
72 | ||
73 | for (i = 0; i < 48; i += 8) | |
74 | if (offset < i + 8) { | |
75 | base_offset = register_offset[i / 8]; | |
76 | mask = BIT(offset - i); | |
77 | ||
78 | return !!(inb(idi48gpio->base + base_offset) & mask); | |
79 | } | |
80 | ||
81 | /* The following line should never execute since offset < 48 */ | |
82 | return 0; | |
83 | } | |
84 | ||
85 | static void idi_48_irq_ack(struct irq_data *data) | |
86 | { | |
6ddcf9b4 WBG |
87 | } |
88 | ||
89 | static void idi_48_irq_mask(struct irq_data *data) | |
90 | { | |
91 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
1f36bec5 | 92 | struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip); |
6ddcf9b4 WBG |
93 | const unsigned offset = irqd_to_hwirq(data); |
94 | unsigned i; | |
95 | unsigned mask; | |
96 | unsigned boundary; | |
97 | unsigned long flags; | |
98 | ||
99 | for (i = 0; i < 48; i += 8) | |
100 | if (offset < i + 8) { | |
101 | mask = BIT(offset - i); | |
102 | boundary = i / 8; | |
103 | ||
104 | idi48gpio->irq_mask[boundary] &= ~mask; | |
105 | ||
106 | if (!idi48gpio->irq_mask[boundary]) { | |
107 | idi48gpio->cos_enb &= ~BIT(boundary); | |
108 | ||
109 | spin_lock_irqsave(&idi48gpio->lock, flags); | |
110 | ||
111 | outb(idi48gpio->cos_enb, idi48gpio->base + 7); | |
112 | ||
113 | spin_unlock_irqrestore(&idi48gpio->lock, flags); | |
114 | } | |
115 | ||
116 | return; | |
117 | } | |
118 | } | |
119 | ||
120 | static void idi_48_irq_unmask(struct irq_data *data) | |
121 | { | |
122 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
1f36bec5 | 123 | struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip); |
6ddcf9b4 WBG |
124 | const unsigned offset = irqd_to_hwirq(data); |
125 | unsigned i; | |
126 | unsigned mask; | |
127 | unsigned boundary; | |
128 | unsigned prev_irq_mask; | |
129 | unsigned long flags; | |
130 | ||
131 | for (i = 0; i < 48; i += 8) | |
132 | if (offset < i + 8) { | |
133 | mask = BIT(offset - i); | |
134 | boundary = i / 8; | |
135 | prev_irq_mask = idi48gpio->irq_mask[boundary]; | |
136 | ||
137 | idi48gpio->irq_mask[boundary] |= mask; | |
138 | ||
139 | if (!prev_irq_mask) { | |
140 | idi48gpio->cos_enb |= BIT(boundary); | |
141 | ||
142 | spin_lock_irqsave(&idi48gpio->lock, flags); | |
143 | ||
144 | outb(idi48gpio->cos_enb, idi48gpio->base + 7); | |
145 | ||
146 | spin_unlock_irqrestore(&idi48gpio->lock, flags); | |
147 | } | |
148 | ||
149 | return; | |
150 | } | |
151 | } | |
152 | ||
153 | static int idi_48_irq_set_type(struct irq_data *data, unsigned flow_type) | |
154 | { | |
155 | /* The only valid irq types are none and both-edges */ | |
156 | if (flow_type != IRQ_TYPE_NONE && | |
157 | (flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH) | |
158 | return -EINVAL; | |
159 | ||
160 | return 0; | |
161 | } | |
162 | ||
163 | static struct irq_chip idi_48_irqchip = { | |
164 | .name = "104-idi-48", | |
165 | .irq_ack = idi_48_irq_ack, | |
166 | .irq_mask = idi_48_irq_mask, | |
167 | .irq_unmask = idi_48_irq_unmask, | |
168 | .irq_set_type = idi_48_irq_set_type | |
169 | }; | |
170 | ||
171 | static irqreturn_t idi_48_irq_handler(int irq, void *dev_id) | |
172 | { | |
173 | struct idi_48_gpio *const idi48gpio = dev_id; | |
174 | unsigned long cos_status; | |
175 | unsigned long boundary; | |
176 | unsigned long irq_mask; | |
177 | unsigned long bit_num; | |
178 | unsigned long gpio; | |
179 | struct gpio_chip *const chip = &idi48gpio->chip; | |
180 | ||
9ae48210 WBG |
181 | spin_lock(&idi48gpio->ack_lock); |
182 | ||
6ddcf9b4 WBG |
183 | spin_lock(&idi48gpio->lock); |
184 | ||
185 | cos_status = inb(idi48gpio->base + 7); | |
186 | ||
187 | spin_unlock(&idi48gpio->lock); | |
188 | ||
189 | /* IRQ Status (bit 6) is active low (0 = IRQ generated by device) */ | |
9ae48210 WBG |
190 | if (cos_status & BIT(6)) { |
191 | spin_unlock(&idi48gpio->ack_lock); | |
6ddcf9b4 | 192 | return IRQ_NONE; |
9ae48210 | 193 | } |
6ddcf9b4 WBG |
194 | |
195 | /* Bit 0-5 indicate which Change-Of-State boundary triggered the IRQ */ | |
196 | cos_status &= 0x3F; | |
197 | ||
198 | for_each_set_bit(boundary, &cos_status, 6) { | |
199 | irq_mask = idi48gpio->irq_mask[boundary]; | |
200 | ||
201 | for_each_set_bit(bit_num, &irq_mask, 8) { | |
202 | gpio = bit_num + boundary * 8; | |
203 | ||
204 | generic_handle_irq(irq_find_mapping(chip->irqdomain, | |
205 | gpio)); | |
206 | } | |
207 | } | |
208 | ||
9ae48210 WBG |
209 | spin_unlock(&idi48gpio->ack_lock); |
210 | ||
6ddcf9b4 WBG |
211 | return IRQ_HANDLED; |
212 | } | |
213 | ||
214 | static int __init idi_48_probe(struct platform_device *pdev) | |
215 | { | |
216 | struct device *dev = &pdev->dev; | |
217 | struct idi_48_gpio *idi48gpio; | |
218 | const unsigned base = idi_48_base; | |
219 | const unsigned extent = 8; | |
220 | const char *const name = dev_name(dev); | |
221 | int err; | |
222 | const unsigned irq = idi_48_irq; | |
223 | ||
224 | idi48gpio = devm_kzalloc(dev, sizeof(*idi48gpio), GFP_KERNEL); | |
225 | if (!idi48gpio) | |
226 | return -ENOMEM; | |
227 | ||
5cfc0576 WBG |
228 | if (!devm_request_region(dev, base, extent, name)) { |
229 | dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n", | |
230 | base, base + extent); | |
231 | return -EBUSY; | |
6ddcf9b4 WBG |
232 | } |
233 | ||
234 | idi48gpio->chip.label = name; | |
235 | idi48gpio->chip.parent = dev; | |
236 | idi48gpio->chip.owner = THIS_MODULE; | |
237 | idi48gpio->chip.base = -1; | |
238 | idi48gpio->chip.ngpio = 48; | |
239 | idi48gpio->chip.get_direction = idi_48_gpio_get_direction; | |
240 | idi48gpio->chip.direction_input = idi_48_gpio_direction_input; | |
241 | idi48gpio->chip.get = idi_48_gpio_get; | |
242 | idi48gpio->base = base; | |
6ddcf9b4 WBG |
243 | idi48gpio->irq = irq; |
244 | ||
245 | spin_lock_init(&idi48gpio->lock); | |
246 | ||
247 | dev_set_drvdata(dev, idi48gpio); | |
248 | ||
1f36bec5 | 249 | err = gpiochip_add_data(&idi48gpio->chip, idi48gpio); |
6ddcf9b4 WBG |
250 | if (err) { |
251 | dev_err(dev, "GPIO registering failed (%d)\n", err); | |
5cfc0576 | 252 | return err; |
6ddcf9b4 WBG |
253 | } |
254 | ||
255 | /* Disable IRQ by default */ | |
256 | outb(0, base + 7); | |
257 | inb(base + 7); | |
258 | ||
259 | err = gpiochip_irqchip_add(&idi48gpio->chip, &idi_48_irqchip, 0, | |
260 | handle_edge_irq, IRQ_TYPE_NONE); | |
261 | if (err) { | |
262 | dev_err(dev, "Could not add irqchip (%d)\n", err); | |
5cfc0576 | 263 | goto err_gpiochip_remove; |
6ddcf9b4 WBG |
264 | } |
265 | ||
4332e014 WBG |
266 | err = request_irq(irq, idi_48_irq_handler, IRQF_SHARED, name, |
267 | idi48gpio); | |
6ddcf9b4 WBG |
268 | if (err) { |
269 | dev_err(dev, "IRQ handler registering failed (%d)\n", err); | |
5cfc0576 | 270 | goto err_gpiochip_remove; |
6ddcf9b4 WBG |
271 | } |
272 | ||
273 | return 0; | |
274 | ||
5cfc0576 | 275 | err_gpiochip_remove: |
6ddcf9b4 | 276 | gpiochip_remove(&idi48gpio->chip); |
6ddcf9b4 WBG |
277 | return err; |
278 | } | |
279 | ||
280 | static int idi_48_remove(struct platform_device *pdev) | |
281 | { | |
282 | struct idi_48_gpio *const idi48gpio = platform_get_drvdata(pdev); | |
283 | ||
284 | free_irq(idi48gpio->irq, idi48gpio); | |
285 | gpiochip_remove(&idi48gpio->chip); | |
6ddcf9b4 WBG |
286 | |
287 | return 0; | |
288 | } | |
289 | ||
290 | static struct platform_device *idi_48_device; | |
291 | ||
292 | static struct platform_driver idi_48_driver = { | |
293 | .driver = { | |
294 | .name = "104-idi-48" | |
295 | }, | |
296 | .remove = idi_48_remove | |
297 | }; | |
298 | ||
299 | static void __exit idi_48_exit(void) | |
300 | { | |
301 | platform_device_unregister(idi_48_device); | |
302 | platform_driver_unregister(&idi_48_driver); | |
303 | } | |
304 | ||
305 | static int __init idi_48_init(void) | |
306 | { | |
307 | int err; | |
308 | ||
309 | idi_48_device = platform_device_alloc(idi_48_driver.driver.name, -1); | |
310 | if (!idi_48_device) | |
311 | return -ENOMEM; | |
312 | ||
313 | err = platform_device_add(idi_48_device); | |
314 | if (err) | |
315 | goto err_platform_device; | |
316 | ||
317 | err = platform_driver_probe(&idi_48_driver, idi_48_probe); | |
318 | if (err) | |
319 | goto err_platform_driver; | |
320 | ||
321 | return 0; | |
322 | ||
323 | err_platform_driver: | |
324 | platform_device_del(idi_48_device); | |
325 | err_platform_device: | |
326 | platform_device_put(idi_48_device); | |
327 | return err; | |
328 | } | |
329 | ||
330 | module_init(idi_48_init); | |
331 | module_exit(idi_48_exit); | |
332 | ||
333 | MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>"); | |
334 | MODULE_DESCRIPTION("ACCES 104-IDI-48 GPIO driver"); | |
22aeddb5 | 335 | MODULE_LICENSE("GPL v2"); |