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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1b06d64f | 2 | /* |
4c23db0f | 3 | * GPIO driver for the ACCES 104-DIO-48E series |
1b06d64f WBG |
4 | * Copyright (C) 2016 William Breathitt Gray |
5 | * | |
4c23db0f WBG |
6 | * This driver supports the following ACCES devices: 104-DIO-48E and |
7 | * 104-DIO-24E. | |
1b06d64f | 8 | */ |
d2d02bcd | 9 | #include <linux/bitmap.h> |
1b06d64f WBG |
10 | #include <linux/bitops.h> |
11 | #include <linux/device.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/gpio/driver.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/ioport.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/irqdesc.h> | |
4c23db0f | 18 | #include <linux/isa.h> |
1b06d64f WBG |
19 | #include <linux/kernel.h> |
20 | #include <linux/module.h> | |
21 | #include <linux/moduleparam.h> | |
1b06d64f WBG |
22 | #include <linux/spinlock.h> |
23 | ||
4c23db0f WBG |
24 | #define DIO48E_EXTENT 16 |
25 | #define MAX_NUM_DIO48E max_num_isa_dev(DIO48E_EXTENT) | |
26 | ||
27 | static unsigned int base[MAX_NUM_DIO48E]; | |
28 | static unsigned int num_dio48e; | |
d759f906 | 29 | module_param_hw_array(base, uint, ioport, &num_dio48e, 0); |
4c23db0f WBG |
30 | MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses"); |
31 | ||
32 | static unsigned int irq[MAX_NUM_DIO48E]; | |
d759f906 | 33 | module_param_hw_array(irq, uint, irq, NULL, 0); |
4c23db0f | 34 | MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers"); |
1b06d64f WBG |
35 | |
36 | /** | |
37 | * struct dio48e_gpio - GPIO device private data structure | |
38 | * @chip: instance of the gpio_chip | |
39 | * @io_state: bit I/O state (whether bit is set to input or output) | |
40 | * @out_state: output bits state | |
41 | * @control: Control registers state | |
42 | * @lock: synchronization lock to prevent I/O race conditions | |
43 | * @base: base port address of the GPIO device | |
1b06d64f WBG |
44 | * @irq_mask: I/O bits affected by interrupts |
45 | */ | |
46 | struct dio48e_gpio { | |
47 | struct gpio_chip chip; | |
48 | unsigned char io_state[6]; | |
49 | unsigned char out_state[6]; | |
50 | unsigned char control[2]; | |
45897809 | 51 | raw_spinlock_t lock; |
e993e236 | 52 | void __iomem *base; |
1b06d64f WBG |
53 | unsigned char irq_mask; |
54 | }; | |
55 | ||
abd7a8ea | 56 | static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) |
1b06d64f WBG |
57 | { |
58 | struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); | |
abd7a8ea BG |
59 | const unsigned int port = offset / 8; |
60 | const unsigned int mask = BIT(offset % 8); | |
1b06d64f | 61 | |
e42615ec MV |
62 | if (dio48egpio->io_state[port] & mask) |
63 | return GPIO_LINE_DIRECTION_IN; | |
64 | ||
65 | return GPIO_LINE_DIRECTION_OUT; | |
1b06d64f WBG |
66 | } |
67 | ||
abd7a8ea | 68 | static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) |
1b06d64f WBG |
69 | { |
70 | struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); | |
abd7a8ea | 71 | const unsigned int io_port = offset / 8; |
d15d6cf9 | 72 | const unsigned int control_port = io_port / 3; |
e993e236 | 73 | void __iomem *const control_addr = dio48egpio->base + 3 + control_port * 4; |
1b06d64f | 74 | unsigned long flags; |
abd7a8ea | 75 | unsigned int control; |
1b06d64f | 76 | |
45897809 | 77 | raw_spin_lock_irqsave(&dio48egpio->lock, flags); |
1b06d64f WBG |
78 | |
79 | /* Check if configuring Port C */ | |
80 | if (io_port == 2 || io_port == 5) { | |
81 | /* Port C can be configured by nibble */ | |
82 | if (offset % 8 > 3) { | |
83 | dio48egpio->io_state[io_port] |= 0xF0; | |
84 | dio48egpio->control[control_port] |= BIT(3); | |
85 | } else { | |
86 | dio48egpio->io_state[io_port] |= 0x0F; | |
87 | dio48egpio->control[control_port] |= BIT(0); | |
88 | } | |
89 | } else { | |
90 | dio48egpio->io_state[io_port] |= 0xFF; | |
91 | if (io_port == 0 || io_port == 3) | |
92 | dio48egpio->control[control_port] |= BIT(4); | |
93 | else | |
94 | dio48egpio->control[control_port] |= BIT(1); | |
95 | } | |
96 | ||
97 | control = BIT(7) | dio48egpio->control[control_port]; | |
e993e236 | 98 | iowrite8(control, control_addr); |
1b06d64f | 99 | control &= ~BIT(7); |
e993e236 | 100 | iowrite8(control, control_addr); |
1b06d64f | 101 | |
45897809 | 102 | raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); |
1b06d64f WBG |
103 | |
104 | return 0; | |
105 | } | |
106 | ||
abd7a8ea BG |
107 | static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, |
108 | int value) | |
1b06d64f WBG |
109 | { |
110 | struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); | |
abd7a8ea | 111 | const unsigned int io_port = offset / 8; |
d15d6cf9 | 112 | const unsigned int control_port = io_port / 3; |
abd7a8ea | 113 | const unsigned int mask = BIT(offset % 8); |
e993e236 | 114 | void __iomem *const control_addr = dio48egpio->base + 3 + control_port * 4; |
abd7a8ea | 115 | const unsigned int out_port = (io_port > 2) ? io_port + 1 : io_port; |
1b06d64f | 116 | unsigned long flags; |
abd7a8ea | 117 | unsigned int control; |
1b06d64f | 118 | |
45897809 | 119 | raw_spin_lock_irqsave(&dio48egpio->lock, flags); |
1b06d64f WBG |
120 | |
121 | /* Check if configuring Port C */ | |
122 | if (io_port == 2 || io_port == 5) { | |
123 | /* Port C can be configured by nibble */ | |
124 | if (offset % 8 > 3) { | |
125 | dio48egpio->io_state[io_port] &= 0x0F; | |
126 | dio48egpio->control[control_port] &= ~BIT(3); | |
127 | } else { | |
128 | dio48egpio->io_state[io_port] &= 0xF0; | |
129 | dio48egpio->control[control_port] &= ~BIT(0); | |
130 | } | |
131 | } else { | |
132 | dio48egpio->io_state[io_port] &= 0x00; | |
133 | if (io_port == 0 || io_port == 3) | |
134 | dio48egpio->control[control_port] &= ~BIT(4); | |
135 | else | |
136 | dio48egpio->control[control_port] &= ~BIT(1); | |
137 | } | |
138 | ||
139 | if (value) | |
140 | dio48egpio->out_state[io_port] |= mask; | |
141 | else | |
142 | dio48egpio->out_state[io_port] &= ~mask; | |
143 | ||
144 | control = BIT(7) | dio48egpio->control[control_port]; | |
e993e236 | 145 | iowrite8(control, control_addr); |
1b06d64f | 146 | |
e993e236 | 147 | iowrite8(dio48egpio->out_state[io_port], dio48egpio->base + out_port); |
1b06d64f WBG |
148 | |
149 | control &= ~BIT(7); | |
e993e236 | 150 | iowrite8(control, control_addr); |
1b06d64f | 151 | |
45897809 | 152 | raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); |
1b06d64f WBG |
153 | |
154 | return 0; | |
155 | } | |
156 | ||
abd7a8ea | 157 | static int dio48e_gpio_get(struct gpio_chip *chip, unsigned int offset) |
1b06d64f WBG |
158 | { |
159 | struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); | |
abd7a8ea BG |
160 | const unsigned int port = offset / 8; |
161 | const unsigned int mask = BIT(offset % 8); | |
162 | const unsigned int in_port = (port > 2) ? port + 1 : port; | |
1b06d64f | 163 | unsigned long flags; |
abd7a8ea | 164 | unsigned int port_state; |
1b06d64f | 165 | |
45897809 | 166 | raw_spin_lock_irqsave(&dio48egpio->lock, flags); |
1b06d64f WBG |
167 | |
168 | /* ensure that GPIO is set for input */ | |
169 | if (!(dio48egpio->io_state[port] & mask)) { | |
45897809 | 170 | raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); |
1b06d64f WBG |
171 | return -EINVAL; |
172 | } | |
173 | ||
e993e236 | 174 | port_state = ioread8(dio48egpio->base + in_port); |
1b06d64f | 175 | |
45897809 | 176 | raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); |
1b06d64f WBG |
177 | |
178 | return !!(port_state & mask); | |
179 | } | |
180 | ||
f70dad5d WBG |
181 | static const size_t ports[] = { 0, 1, 2, 4, 5, 6 }; |
182 | ||
d2d02bcd WBG |
183 | static int dio48e_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, |
184 | unsigned long *bits) | |
185 | { | |
186 | struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); | |
f70dad5d WBG |
187 | unsigned long offset; |
188 | unsigned long gpio_mask; | |
e993e236 | 189 | void __iomem *port_addr; |
d2d02bcd WBG |
190 | unsigned long port_state; |
191 | ||
192 | /* clear bits array to a clean slate */ | |
193 | bitmap_zero(bits, chip->ngpio); | |
194 | ||
f70dad5d WBG |
195 | for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { |
196 | port_addr = dio48egpio->base + ports[offset / 8]; | |
e993e236 | 197 | port_state = ioread8(port_addr) & gpio_mask; |
d2d02bcd | 198 | |
f70dad5d | 199 | bitmap_set_value8(bits, port_state, offset); |
d2d02bcd WBG |
200 | } |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
abd7a8ea | 205 | static void dio48e_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) |
1b06d64f WBG |
206 | { |
207 | struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); | |
abd7a8ea BG |
208 | const unsigned int port = offset / 8; |
209 | const unsigned int mask = BIT(offset % 8); | |
210 | const unsigned int out_port = (port > 2) ? port + 1 : port; | |
1b06d64f WBG |
211 | unsigned long flags; |
212 | ||
45897809 | 213 | raw_spin_lock_irqsave(&dio48egpio->lock, flags); |
1b06d64f WBG |
214 | |
215 | if (value) | |
216 | dio48egpio->out_state[port] |= mask; | |
217 | else | |
218 | dio48egpio->out_state[port] &= ~mask; | |
219 | ||
e993e236 | 220 | iowrite8(dio48egpio->out_state[port], dio48egpio->base + out_port); |
1b06d64f | 221 | |
45897809 | 222 | raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); |
1b06d64f WBG |
223 | } |
224 | ||
be183202 WBG |
225 | static void dio48e_gpio_set_multiple(struct gpio_chip *chip, |
226 | unsigned long *mask, unsigned long *bits) | |
227 | { | |
228 | struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); | |
f70dad5d WBG |
229 | unsigned long offset; |
230 | unsigned long gpio_mask; | |
231 | size_t index; | |
e993e236 | 232 | void __iomem *port_addr; |
f70dad5d | 233 | unsigned long bitmask; |
be183202 WBG |
234 | unsigned long flags; |
235 | ||
f70dad5d WBG |
236 | for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { |
237 | index = offset / 8; | |
238 | port_addr = dio48egpio->base + ports[index]; | |
be183202 | 239 | |
f70dad5d | 240 | bitmask = bitmap_get_value8(bits, offset) & gpio_mask; |
be183202 | 241 | |
45897809 | 242 | raw_spin_lock_irqsave(&dio48egpio->lock, flags); |
be183202 WBG |
243 | |
244 | /* update output state data and set device gpio register */ | |
f70dad5d WBG |
245 | dio48egpio->out_state[index] &= ~gpio_mask; |
246 | dio48egpio->out_state[index] |= bitmask; | |
e993e236 | 247 | iowrite8(dio48egpio->out_state[index], port_addr); |
be183202 | 248 | |
45897809 | 249 | raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); |
be183202 WBG |
250 | } |
251 | } | |
252 | ||
1b06d64f WBG |
253 | static void dio48e_irq_ack(struct irq_data *data) |
254 | { | |
255 | } | |
256 | ||
257 | static void dio48e_irq_mask(struct irq_data *data) | |
258 | { | |
259 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
260 | struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); | |
261 | const unsigned long offset = irqd_to_hwirq(data); | |
262 | unsigned long flags; | |
263 | ||
264 | /* only bit 3 on each respective Port C supports interrupts */ | |
265 | if (offset != 19 && offset != 43) | |
266 | return; | |
267 | ||
45897809 | 268 | raw_spin_lock_irqsave(&dio48egpio->lock, flags); |
1b06d64f WBG |
269 | |
270 | if (offset == 19) | |
271 | dio48egpio->irq_mask &= ~BIT(0); | |
272 | else | |
273 | dio48egpio->irq_mask &= ~BIT(1); | |
274 | ||
275 | if (!dio48egpio->irq_mask) | |
276 | /* disable interrupts */ | |
e993e236 | 277 | ioread8(dio48egpio->base + 0xB); |
1b06d64f | 278 | |
45897809 | 279 | raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); |
1b06d64f WBG |
280 | } |
281 | ||
282 | static void dio48e_irq_unmask(struct irq_data *data) | |
283 | { | |
284 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
285 | struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); | |
286 | const unsigned long offset = irqd_to_hwirq(data); | |
287 | unsigned long flags; | |
288 | ||
289 | /* only bit 3 on each respective Port C supports interrupts */ | |
290 | if (offset != 19 && offset != 43) | |
291 | return; | |
292 | ||
45897809 | 293 | raw_spin_lock_irqsave(&dio48egpio->lock, flags); |
1b06d64f WBG |
294 | |
295 | if (!dio48egpio->irq_mask) { | |
296 | /* enable interrupts */ | |
e993e236 WBG |
297 | iowrite8(0x00, dio48egpio->base + 0xF); |
298 | iowrite8(0x00, dio48egpio->base + 0xB); | |
1b06d64f WBG |
299 | } |
300 | ||
301 | if (offset == 19) | |
302 | dio48egpio->irq_mask |= BIT(0); | |
303 | else | |
304 | dio48egpio->irq_mask |= BIT(1); | |
305 | ||
45897809 | 306 | raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); |
1b06d64f WBG |
307 | } |
308 | ||
abd7a8ea | 309 | static int dio48e_irq_set_type(struct irq_data *data, unsigned int flow_type) |
1b06d64f WBG |
310 | { |
311 | const unsigned long offset = irqd_to_hwirq(data); | |
312 | ||
313 | /* only bit 3 on each respective Port C supports interrupts */ | |
314 | if (offset != 19 && offset != 43) | |
315 | return -EINVAL; | |
316 | ||
317 | if (flow_type != IRQ_TYPE_NONE && flow_type != IRQ_TYPE_EDGE_RISING) | |
318 | return -EINVAL; | |
319 | ||
320 | return 0; | |
321 | } | |
322 | ||
323 | static struct irq_chip dio48e_irqchip = { | |
324 | .name = "104-dio-48e", | |
325 | .irq_ack = dio48e_irq_ack, | |
326 | .irq_mask = dio48e_irq_mask, | |
327 | .irq_unmask = dio48e_irq_unmask, | |
328 | .irq_set_type = dio48e_irq_set_type | |
329 | }; | |
330 | ||
331 | static irqreturn_t dio48e_irq_handler(int irq, void *dev_id) | |
332 | { | |
333 | struct dio48e_gpio *const dio48egpio = dev_id; | |
334 | struct gpio_chip *const chip = &dio48egpio->chip; | |
335 | const unsigned long irq_mask = dio48egpio->irq_mask; | |
336 | unsigned long gpio; | |
337 | ||
338 | for_each_set_bit(gpio, &irq_mask, 2) | |
dbd1c54f MZ |
339 | generic_handle_domain_irq(chip->irq.domain, |
340 | 19 + gpio*24); | |
1b06d64f | 341 | |
45897809 | 342 | raw_spin_lock(&dio48egpio->lock); |
1b06d64f | 343 | |
e993e236 | 344 | iowrite8(0x00, dio48egpio->base + 0xF); |
1b06d64f | 345 | |
45897809 | 346 | raw_spin_unlock(&dio48egpio->lock); |
1b06d64f WBG |
347 | |
348 | return IRQ_HANDLED; | |
349 | } | |
350 | ||
7bdba73e WBG |
351 | #define DIO48E_NGPIO 48 |
352 | static const char *dio48e_names[DIO48E_NGPIO] = { | |
353 | "PPI Group 0 Port A 0", "PPI Group 0 Port A 1", "PPI Group 0 Port A 2", | |
354 | "PPI Group 0 Port A 3", "PPI Group 0 Port A 4", "PPI Group 0 Port A 5", | |
355 | "PPI Group 0 Port A 6", "PPI Group 0 Port A 7", "PPI Group 0 Port B 0", | |
356 | "PPI Group 0 Port B 1", "PPI Group 0 Port B 2", "PPI Group 0 Port B 3", | |
357 | "PPI Group 0 Port B 4", "PPI Group 0 Port B 5", "PPI Group 0 Port B 6", | |
358 | "PPI Group 0 Port B 7", "PPI Group 0 Port C 0", "PPI Group 0 Port C 1", | |
359 | "PPI Group 0 Port C 2", "PPI Group 0 Port C 3", "PPI Group 0 Port C 4", | |
360 | "PPI Group 0 Port C 5", "PPI Group 0 Port C 6", "PPI Group 0 Port C 7", | |
361 | "PPI Group 1 Port A 0", "PPI Group 1 Port A 1", "PPI Group 1 Port A 2", | |
362 | "PPI Group 1 Port A 3", "PPI Group 1 Port A 4", "PPI Group 1 Port A 5", | |
363 | "PPI Group 1 Port A 6", "PPI Group 1 Port A 7", "PPI Group 1 Port B 0", | |
364 | "PPI Group 1 Port B 1", "PPI Group 1 Port B 2", "PPI Group 1 Port B 3", | |
365 | "PPI Group 1 Port B 4", "PPI Group 1 Port B 5", "PPI Group 1 Port B 6", | |
366 | "PPI Group 1 Port B 7", "PPI Group 1 Port C 0", "PPI Group 1 Port C 1", | |
367 | "PPI Group 1 Port C 2", "PPI Group 1 Port C 3", "PPI Group 1 Port C 4", | |
368 | "PPI Group 1 Port C 5", "PPI Group 1 Port C 6", "PPI Group 1 Port C 7" | |
369 | }; | |
370 | ||
2fa1d392 LW |
371 | static int dio48e_irq_init_hw(struct gpio_chip *gc) |
372 | { | |
373 | struct dio48e_gpio *const dio48egpio = gpiochip_get_data(gc); | |
374 | ||
375 | /* Disable IRQ by default */ | |
e993e236 | 376 | ioread8(dio48egpio->base + 0xB); |
2fa1d392 LW |
377 | |
378 | return 0; | |
379 | } | |
380 | ||
4c23db0f | 381 | static int dio48e_probe(struct device *dev, unsigned int id) |
1b06d64f | 382 | { |
1b06d64f | 383 | struct dio48e_gpio *dio48egpio; |
1b06d64f | 384 | const char *const name = dev_name(dev); |
2fa1d392 | 385 | struct gpio_irq_chip *girq; |
1b06d64f | 386 | int err; |
1b06d64f WBG |
387 | |
388 | dio48egpio = devm_kzalloc(dev, sizeof(*dio48egpio), GFP_KERNEL); | |
389 | if (!dio48egpio) | |
390 | return -ENOMEM; | |
391 | ||
4c23db0f | 392 | if (!devm_request_region(dev, base[id], DIO48E_EXTENT, name)) { |
aa6c3602 | 393 | dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n", |
4c23db0f | 394 | base[id], base[id] + DIO48E_EXTENT); |
aa6c3602 | 395 | return -EBUSY; |
1b06d64f WBG |
396 | } |
397 | ||
e993e236 WBG |
398 | dio48egpio->base = devm_ioport_map(dev, base[id], DIO48E_EXTENT); |
399 | if (!dio48egpio->base) | |
400 | return -ENOMEM; | |
401 | ||
1b06d64f WBG |
402 | dio48egpio->chip.label = name; |
403 | dio48egpio->chip.parent = dev; | |
404 | dio48egpio->chip.owner = THIS_MODULE; | |
405 | dio48egpio->chip.base = -1; | |
7bdba73e WBG |
406 | dio48egpio->chip.ngpio = DIO48E_NGPIO; |
407 | dio48egpio->chip.names = dio48e_names; | |
1b06d64f WBG |
408 | dio48egpio->chip.get_direction = dio48e_gpio_get_direction; |
409 | dio48egpio->chip.direction_input = dio48e_gpio_direction_input; | |
410 | dio48egpio->chip.direction_output = dio48e_gpio_direction_output; | |
411 | dio48egpio->chip.get = dio48e_gpio_get; | |
d2d02bcd | 412 | dio48egpio->chip.get_multiple = dio48e_gpio_get_multiple; |
1b06d64f | 413 | dio48egpio->chip.set = dio48e_gpio_set; |
be183202 | 414 | dio48egpio->chip.set_multiple = dio48e_gpio_set_multiple; |
1b06d64f | 415 | |
2fa1d392 LW |
416 | girq = &dio48egpio->chip.irq; |
417 | girq->chip = &dio48e_irqchip; | |
418 | /* This will let us handle the parent IRQ in the driver */ | |
419 | girq->parent_handler = NULL; | |
420 | girq->num_parents = 0; | |
421 | girq->parents = NULL; | |
422 | girq->default_type = IRQ_TYPE_NONE; | |
423 | girq->handler = handle_edge_irq; | |
424 | girq->init_hw = dio48e_irq_init_hw; | |
1b06d64f | 425 | |
2fa1d392 | 426 | raw_spin_lock_init(&dio48egpio->lock); |
1b06d64f WBG |
427 | |
428 | /* initialize all GPIO as output */ | |
e993e236 WBG |
429 | iowrite8(0x80, dio48egpio->base + 3); |
430 | iowrite8(0x00, dio48egpio->base); | |
431 | iowrite8(0x00, dio48egpio->base + 1); | |
432 | iowrite8(0x00, dio48egpio->base + 2); | |
433 | iowrite8(0x00, dio48egpio->base + 3); | |
434 | iowrite8(0x80, dio48egpio->base + 7); | |
435 | iowrite8(0x00, dio48egpio->base + 4); | |
436 | iowrite8(0x00, dio48egpio->base + 5); | |
437 | iowrite8(0x00, dio48egpio->base + 6); | |
438 | iowrite8(0x00, dio48egpio->base + 7); | |
1b06d64f | 439 | |
2fa1d392 | 440 | err = devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio); |
1b06d64f | 441 | if (err) { |
2fa1d392 | 442 | dev_err(dev, "GPIO registering failed (%d)\n", err); |
00de1a51 | 443 | return err; |
1b06d64f WBG |
444 | } |
445 | ||
00de1a51 WBG |
446 | err = devm_request_irq(dev, irq[id], dio48e_irq_handler, 0, name, |
447 | dio48egpio); | |
1b06d64f WBG |
448 | if (err) { |
449 | dev_err(dev, "IRQ handler registering failed (%d)\n", err); | |
00de1a51 | 450 | return err; |
1b06d64f WBG |
451 | } |
452 | ||
1b06d64f WBG |
453 | return 0; |
454 | } | |
455 | ||
4c23db0f WBG |
456 | static struct isa_driver dio48e_driver = { |
457 | .probe = dio48e_probe, | |
1b06d64f WBG |
458 | .driver = { |
459 | .name = "104-dio-48e" | |
460 | }, | |
1b06d64f | 461 | }; |
4c23db0f | 462 | module_isa_driver(dio48e_driver, num_dio48e); |
1b06d64f WBG |
463 | |
464 | MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>"); | |
465 | MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver"); | |
22aeddb5 | 466 | MODULE_LICENSE("GPL v2"); |