[linux-block.git] / drivers / genpd / mediatek / mtk-pm-domains.h

/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef __SOC_MEDIATEK_MTK_PM_DOMAINS_H
#define __SOC_MEDIATEK_MTK_PM_DOMAINS_H

#define MTK_SCPD_ACTIVE_WAKEUP		BIT(0)
#define MTK_SCPD_FWAIT_SRAM		BIT(1)
#define MTK_SCPD_SRAM_ISO		BIT(2)
#define MTK_SCPD_KEEP_DEFAULT_OFF	BIT(3)
#define MTK_SCPD_DOMAIN_SUPPLY		BIT(4)
/* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */
#define MTK_SCPD_ALWAYS_ON		BIT(5)
#define MTK_SCPD_EXT_BUCK_ISO		BIT(6)
#define MTK_SCPD_CAPS(_scpd, _x)	((_scpd)->data->caps & (_x))

#define SPM_VDE_PWR_CON			0x0210
#define SPM_MFG_PWR_CON			0x0214
#define SPM_VEN_PWR_CON			0x0230
#define SPM_ISP_PWR_CON			0x0238
#define SPM_DIS_PWR_CON			0x023c
#define SPM_CONN_PWR_CON		0x0280
#define SPM_VEN2_PWR_CON		0x0298
#define SPM_AUDIO_PWR_CON		0x029c
#define SPM_MFG_2D_PWR_CON		0x02c0
#define SPM_MFG_ASYNC_PWR_CON		0x02c4
#define SPM_USB_PWR_CON			0x02cc

#define SPM_PWR_STATUS			0x060c
#define SPM_PWR_STATUS_2ND		0x0610

#define PWR_STATUS_CONN			BIT(1)
#define PWR_STATUS_DISP			BIT(3)
#define PWR_STATUS_MFG			BIT(4)
#define PWR_STATUS_ISP			BIT(5)
#define PWR_STATUS_VDEC			BIT(7)
#define PWR_STATUS_VENC_LT		BIT(20)
#define PWR_STATUS_VENC			BIT(21)
#define PWR_STATUS_MFG_2D		BIT(22)
#define PWR_STATUS_MFG_ASYNC		BIT(23)
#define PWR_STATUS_AUDIO		BIT(24)
#define PWR_STATUS_USB			BIT(25)

#define SPM_MAX_BUS_PROT_DATA		6

#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) {	\
		.bus_prot_mask = (_mask),			\
		.bus_prot_set = _set,				\
		.bus_prot_clr = _clr,				\
		.bus_prot_sta = _sta,				\
		.bus_prot_reg_update = _update,			\
		.ignore_clr_ack = _ignore,			\
	}

#define BUS_PROT_WR(_mask, _set, _clr, _sta)			\
		_BUS_PROT(_mask, _set, _clr, _sta, false, false)

#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta)		\
		_BUS_PROT(_mask, _set, _clr, _sta, false, true)

#define BUS_PROT_UPDATE(_mask, _set, _clr, _sta)		\
		_BUS_PROT(_mask, _set, _clr, _sta, true, false)

#define BUS_PROT_UPDATE_TOPAXI(_mask)				\
		BUS_PROT_UPDATE(_mask,				\
				INFRA_TOPAXI_PROTECTEN,		\
				INFRA_TOPAXI_PROTECTEN,		\
				INFRA_TOPAXI_PROTECTSTA1)

struct scpsys_bus_prot_data {
	u32 bus_prot_mask;
	u32 bus_prot_set;
	u32 bus_prot_clr;
	u32 bus_prot_sta;
	bool bus_prot_reg_update;
	bool ignore_clr_ack;
};

/**
 * struct scpsys_domain_data - scp domain data for power on/off flow
 * @name: The name of the power domain.
 * @sta_mask: The mask for power on/off status bit.
 * @ctl_offs: The offset for main power control register.
 * @sram_pdn_bits: The mask for sram power control bits.
 * @sram_pdn_ack_bits: The mask for sram power control acked bits.
 * @ext_buck_iso_offs: The offset for external buck isolation
 * @ext_buck_iso_mask: The mask for external buck isolation
 * @caps: The flag for active wake-up action.
 * @bp_infracfg: bus protection for infracfg subsystem
 * @bp_smi: bus protection for smi subsystem
 */
struct scpsys_domain_data {
	const char *name;
	u32 sta_mask;
	int ctl_offs;
	u32 sram_pdn_bits;
	u32 sram_pdn_ack_bits;
	int ext_buck_iso_offs;
	u32 ext_buck_iso_mask;
	u8 caps;
	const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA];
	const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA];
	int pwr_sta_offs;
	int pwr_sta2nd_offs;
};

struct scpsys_soc_data {
	const struct scpsys_domain_data *domains_data;
	int num_domains;
};

#endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */
Commit	Line	Data
59b644b0 EBS	1	/* SPDX-License-Identifier: GPL-2.0-only */
	2
	3	#ifndef __SOC_MEDIATEK_MTK_PM_DOMAINS_H
	4	#define __SOC_MEDIATEK_MTK_PM_DOMAINS_H
	5
	6	#define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
	7	#define MTK_SCPD_FWAIT_SRAM BIT(1)
58a17e31	8	#define MTK_SCPD_SRAM_ISO BIT(2)
c1f3163d	9	#define MTK_SCPD_KEEP_DEFAULT_OFF BIT(3)
1b18c055	10	#define MTK_SCPD_DOMAIN_SUPPLY BIT(4)
72be1e7a CY	11	/* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */
72be1e7a CY	12	#define MTK_SCPD_ALWAYS_ON BIT(5)
7d1ae592	13	#define MTK_SCPD_EXT_BUCK_ISO BIT(6)
59b644b0 EBS	14	#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
	15
	16	#define SPM_VDE_PWR_CON 0x0210
	17	#define SPM_MFG_PWR_CON 0x0214
	18	#define SPM_VEN_PWR_CON 0x0230
	19	#define SPM_ISP_PWR_CON 0x0238
	20	#define SPM_DIS_PWR_CON 0x023c
207f13b4	21	#define SPM_CONN_PWR_CON 0x0280
59b644b0 EBS	22	#define SPM_VEN2_PWR_CON 0x0298
	23	#define SPM_AUDIO_PWR_CON 0x029c
	24	#define SPM_MFG_2D_PWR_CON 0x02c0
	25	#define SPM_MFG_ASYNC_PWR_CON 0x02c4
	26	#define SPM_USB_PWR_CON 0x02cc
	27
	28	#define SPM_PWR_STATUS 0x060c
	29	#define SPM_PWR_STATUS_2ND 0x0610
	30
eb9fa767	31	#define PWR_STATUS_CONN BIT(1)
59b644b0 EBS	32	#define PWR_STATUS_DISP BIT(3)
	33	#define PWR_STATUS_MFG BIT(4)
	34	#define PWR_STATUS_ISP BIT(5)
	35	#define PWR_STATUS_VDEC BIT(7)
	36	#define PWR_STATUS_VENC_LT BIT(20)
	37	#define PWR_STATUS_VENC BIT(21)
	38	#define PWR_STATUS_MFG_2D BIT(22)
	39	#define PWR_STATUS_MFG_ASYNC BIT(23)
	40	#define PWR_STATUS_AUDIO BIT(24)
	41	#define PWR_STATUS_USB BIT(25)
	42
342479c8	43	#define SPM_MAX_BUS_PROT_DATA 6
916d6d71	44
1d4597fa MB	45	#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \
	46	.bus_prot_mask = (_mask), \
	47	.bus_prot_set = _set, \
	48	.bus_prot_clr = _clr, \
	49	.bus_prot_sta = _sta, \
	50	.bus_prot_reg_update = _update, \
	51	.ignore_clr_ack = _ignore, \
f414854c MB	52	}
f414854c MB	53
1d4597fa MB	54	#define BUS_PROT_WR(_mask, _set, _clr, _sta) \
	55	_BUS_PROT(_mask, _set, _clr, _sta, false, false)
	56
	57	#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \
	58	_BUS_PROT(_mask, _set, _clr, _sta, false, true)
f414854c MB	59
f414854c MB	60	#define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \
1d4597fa	61	_BUS_PROT(_mask, _set, _clr, _sta, true, false)
f414854c MB	62
	63	#define BUS_PROT_UPDATE_TOPAXI(_mask) \
	64	BUS_PROT_UPDATE(_mask, \
	65	INFRA_TOPAXI_PROTECTEN, \
fb6d1d3b	66	INFRA_TOPAXI_PROTECTEN, \
f414854c MB	67	INFRA_TOPAXI_PROTECTSTA1)
f414854c MB	68
59b644b0 EBS	69	struct scpsys_bus_prot_data {
59b644b0 EBS	70	u32 bus_prot_mask;
f414854c MB	71	u32 bus_prot_set;
	72	u32 bus_prot_clr;
	73	u32 bus_prot_sta;
59b644b0	74	bool bus_prot_reg_update;
1d4597fa	75	bool ignore_clr_ack;
59b644b0 EBS	76	};
	77
	78	/**
	79	* struct scpsys_domain_data - scp domain data for power on/off flow
022b02b4	80	* @name: The name of the power domain.
59b644b0 EBS	81	* @sta_mask: The mask for power on/off status bit.
	82	* @ctl_offs: The offset for main power control register.
	83	* @sram_pdn_bits: The mask for sram power control bits.
	84	* @sram_pdn_ack_bits: The mask for sram power control acked bits.
1e28f6a3 AKC	85	* @ext_buck_iso_offs: The offset for external buck isolation
1e28f6a3 AKC	86	* @ext_buck_iso_mask: The mask for external buck isolation
59b644b0 EBS	87	* @caps: The flag for active wake-up action.
59b644b0 EBS	88	* @bp_infracfg: bus protection for infracfg subsystem
f414854c	89	* @bp_smi: bus protection for smi subsystem
59b644b0 EBS	90	*/
59b644b0 EBS	91	struct scpsys_domain_data {
022b02b4	92	const char *name;
59b644b0 EBS	93	u32 sta_mask;
	94	int ctl_offs;
	95	u32 sram_pdn_bits;
	96	u32 sram_pdn_ack_bits;
1e28f6a3 AKC	97	int ext_buck_iso_offs;
1e28f6a3 AKC	98	u32 ext_buck_iso_mask;
59b644b0	99	u8 caps;
916d6d71	100	const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA];
f414854c	101	const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA];
db2ca860 CJC	102	int pwr_sta_offs;
db2ca860 CJC	103	int pwr_sta2nd_offs;
59b644b0 EBS	104	};
	105
	106	struct scpsys_soc_data {
	107	const struct scpsys_domain_data *domains_data;
	108	int num_domains;
59b644b0 EBS	109	};
	110
	111	#endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */