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ASoc: Another series to convert to struct
[linux-block.git] / drivers / genpd / mediatek / mt8188-pm-domains.h
CommitLineData
e610e814
GC		 1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Garmin Chang <garmin.chang@mediatek.com>
5 */
6
7#ifndef __SOC_MEDIATEK_MT8188_PM_DOMAINS_H
8#define __SOC_MEDIATEK_MT8188_PM_DOMAINS_H
9
10#include "mtk-pm-domains.h"
11#include <dt-bindings/power/mediatek,mt8188-power.h>
12
13/*
14 * MT8188 power domain support
15 */
16
17static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
18 [MT8188_POWER_DOMAIN_MFG0] = {
19 .name = "mfg0",
20 .sta_mask = BIT(1),
21 .ctl_offs = 0x300,
22 .pwr_sta_offs = 0x174,
23 .pwr_sta2nd_offs = 0x178,
24 .sram_pdn_bits = BIT(8),
25 .sram_pdn_ack_bits = BIT(12),
26 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
27 },
28 [MT8188_POWER_DOMAIN_MFG1] = {
29 .name = "mfg1",
30 .sta_mask = BIT(2),
31 .ctl_offs = 0x304,
32 .pwr_sta_offs = 0x174,
33 .pwr_sta2nd_offs = 0x178,
34 .sram_pdn_bits = BIT(8),
35 .sram_pdn_ack_bits = BIT(12),
36 .bp_infracfg = {
37 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP1,
38 MT8188_TOP_AXI_PROT_EN_SET,
39 MT8188_TOP_AXI_PROT_EN_CLR,
40 MT8188_TOP_AXI_PROT_EN_STA),
41 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2,
42 MT8188_TOP_AXI_PROT_EN_2_SET,
43 MT8188_TOP_AXI_PROT_EN_2_CLR,
44 MT8188_TOP_AXI_PROT_EN_2_STA),
45 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3,
46 MT8188_TOP_AXI_PROT_EN_1_SET,
47 MT8188_TOP_AXI_PROT_EN_1_CLR,
48 MT8188_TOP_AXI_PROT_EN_1_STA),
49 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4,
50 MT8188_TOP_AXI_PROT_EN_2_SET,
51 MT8188_TOP_AXI_PROT_EN_2_CLR,
52 MT8188_TOP_AXI_PROT_EN_2_STA),
53 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP5,
54 MT8188_TOP_AXI_PROT_EN_SET,
55 MT8188_TOP_AXI_PROT_EN_CLR,
56 MT8188_TOP_AXI_PROT_EN_STA),
57 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6,
58 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
59 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
60 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
61 },
62 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
63 },
64 [MT8188_POWER_DOMAIN_MFG2] = {
65 .name = "mfg2",
66 .sta_mask = BIT(3),
67 .ctl_offs = 0x308,
68 .pwr_sta_offs = 0x174,
69 .pwr_sta2nd_offs = 0x178,
70 .sram_pdn_bits = BIT(8),
71 .sram_pdn_ack_bits = BIT(12),
72 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
73 },
74 [MT8188_POWER_DOMAIN_MFG3] = {
75 .name = "mfg3",
76 .sta_mask = BIT(4),
77 .ctl_offs = 0x30C,
78 .pwr_sta_offs = 0x174,
79 .pwr_sta2nd_offs = 0x178,
80 .sram_pdn_bits = BIT(8),
81 .sram_pdn_ack_bits = BIT(12),
82 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
83 },
84 [MT8188_POWER_DOMAIN_MFG4] = {
85 .name = "mfg4",
86 .sta_mask = BIT(5),
87 .ctl_offs = 0x310,
88 .pwr_sta_offs = 0x174,
89 .pwr_sta2nd_offs = 0x178,
90 .sram_pdn_bits = BIT(8),
91 .sram_pdn_ack_bits = BIT(12),
92 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
93 },
94 [MT8188_POWER_DOMAIN_PEXTP_MAC_P0] = {
95 .name = "pextp_mac_p0",
96 .sta_mask = BIT(10),
97 .ctl_offs = 0x324,
98 .pwr_sta_offs = 0x174,
99 .pwr_sta2nd_offs = 0x178,
100 .sram_pdn_bits = BIT(8),
101 .sram_pdn_ack_bits = BIT(12),
102 .bp_infracfg = {
103 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1,
104 MT8188_TOP_AXI_PROT_EN_SET,
105 MT8188_TOP_AXI_PROT_EN_CLR,
106 MT8188_TOP_AXI_PROT_EN_STA),
107 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2,
108 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
109 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
110 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
111 },
112 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
113 },
114 [MT8188_POWER_DOMAIN_PEXTP_PHY_TOP] = {
115 .name = "pextp_phy_top",
116 .sta_mask = BIT(12),
117 .ctl_offs = 0x328,
118 .pwr_sta_offs = 0x174,
119 .pwr_sta2nd_offs = 0x178,
120 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
121 },
122 [MT8188_POWER_DOMAIN_CSIRX_TOP] = {
123 .name = "pextp_csirx_top",
124 .sta_mask = BIT(17),
125 .ctl_offs = 0x3C4,
126 .pwr_sta_offs = 0x174,
127 .pwr_sta2nd_offs = 0x178,
128 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
129 },
130 [MT8188_POWER_DOMAIN_ETHER] = {
131 .name = "ether",
132 .sta_mask = BIT(1),
133 .ctl_offs = 0x338,
134 .pwr_sta_offs = 0x16C,
135 .pwr_sta2nd_offs = 0x170,
136 .sram_pdn_bits = BIT(8),
137 .sram_pdn_ack_bits = BIT(12),
138 .bp_infracfg = {
139 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1,
140 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
141 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
142 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
143 },
144 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
145 },
146 [MT8188_POWER_DOMAIN_HDMI_TX] = {
147 .name = "hdmi_tx",
148 .sta_mask = BIT(18),
149 .ctl_offs = 0x37C,
150 .pwr_sta_offs = 0x16C,
151 .pwr_sta2nd_offs = 0x170,
152 .sram_pdn_bits = BIT(8),
153 .sram_pdn_ack_bits = BIT(12),
154 .bp_infracfg = {
155 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1,
156 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
157 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
158 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
159 },
160 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
161 },
162 [MT8188_POWER_DOMAIN_ADSP_AO] = {
163 .name = "adsp_ao",
164 .sta_mask = BIT(10),
165 .ctl_offs = 0x35C,
166 .pwr_sta_offs = 0x16C,
167 .pwr_sta2nd_offs = 0x170,
168 .bp_infracfg = {
169 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1,
170 MT8188_TOP_AXI_PROT_EN_2_SET,
171 MT8188_TOP_AXI_PROT_EN_2_CLR,
172 MT8188_TOP_AXI_PROT_EN_2_STA),
173 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2,
174 MT8188_TOP_AXI_PROT_EN_2_SET,
175 MT8188_TOP_AXI_PROT_EN_2_CLR,
176 MT8188_TOP_AXI_PROT_EN_2_STA),
177 },
178 .caps = MTK_SCPD_ALWAYS_ON,
179 },
180 [MT8188_POWER_DOMAIN_ADSP_INFRA] = {
181 .name = "adsp_infra",
182 .sta_mask = BIT(9),
183 .ctl_offs = 0x358,
184 .pwr_sta_offs = 0x16C,
185 .pwr_sta2nd_offs = 0x170,
186 .sram_pdn_bits = BIT(8),
187 .sram_pdn_ack_bits = BIT(12),
188 .bp_infracfg = {
189 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1,
190 MT8188_TOP_AXI_PROT_EN_2_SET,
191 MT8188_TOP_AXI_PROT_EN_2_CLR,
192 MT8188_TOP_AXI_PROT_EN_2_STA),
193 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2,
194 MT8188_TOP_AXI_PROT_EN_2_SET,
195 MT8188_TOP_AXI_PROT_EN_2_CLR,
196 MT8188_TOP_AXI_PROT_EN_2_STA),
197 },
198 .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ALWAYS_ON,
199 },
200 [MT8188_POWER_DOMAIN_ADSP] = {
201 .name = "adsp",
202 .sta_mask = BIT(8),
203 .ctl_offs = 0x354,
204 .pwr_sta_offs = 0x16C,
205 .pwr_sta2nd_offs = 0x170,
206 .sram_pdn_bits = BIT(8),
207 .sram_pdn_ack_bits = BIT(12),
208 .bp_infracfg = {
209 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1,
210 MT8188_TOP_AXI_PROT_EN_2_SET,
211 MT8188_TOP_AXI_PROT_EN_2_CLR,
212 MT8188_TOP_AXI_PROT_EN_2_STA),
213 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2,
214 MT8188_TOP_AXI_PROT_EN_2_SET,
215 MT8188_TOP_AXI_PROT_EN_2_CLR,
216 MT8188_TOP_AXI_PROT_EN_2_STA),
217 },
218 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP,
219 },
220 [MT8188_POWER_DOMAIN_AUDIO] = {
221 .name = "audio",
222 .sta_mask = BIT(6),
223 .ctl_offs = 0x34C,
224 .pwr_sta_offs = 0x16C,
225 .pwr_sta2nd_offs = 0x170,
226 .sram_pdn_bits = BIT(8),
227 .sram_pdn_ack_bits = BIT(12),
228 .bp_infracfg = {
229 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1,
230 MT8188_TOP_AXI_PROT_EN_2_SET,
231 MT8188_TOP_AXI_PROT_EN_2_CLR,
232 MT8188_TOP_AXI_PROT_EN_2_STA),
233 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2,
234 MT8188_TOP_AXI_PROT_EN_2_SET,
235 MT8188_TOP_AXI_PROT_EN_2_CLR,
236 MT8188_TOP_AXI_PROT_EN_2_STA),
237 },
238 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
239 },
240 [MT8188_POWER_DOMAIN_AUDIO_ASRC] = {
241 .name = "audio_asrc",
242 .sta_mask = BIT(7),
243 .ctl_offs = 0x350,
244 .pwr_sta_offs = 0x16C,
245 .pwr_sta2nd_offs = 0x170,
246 .sram_pdn_bits = BIT(8),
247 .sram_pdn_ack_bits = BIT(12),
248 .bp_infracfg = {
249 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1,
250 MT8188_TOP_AXI_PROT_EN_2_SET,
251 MT8188_TOP_AXI_PROT_EN_2_CLR,
252 MT8188_TOP_AXI_PROT_EN_2_STA),
253 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2,
254 MT8188_TOP_AXI_PROT_EN_2_SET,
255 MT8188_TOP_AXI_PROT_EN_2_CLR,
256 MT8188_TOP_AXI_PROT_EN_2_STA),
257 },
258 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
259 },
260 [MT8188_POWER_DOMAIN_VPPSYS0] = {
261 .name = "vppsys0",
262 .sta_mask = BIT(11),
263 .ctl_offs = 0x360,
264 .pwr_sta_offs = 0x16C,
265 .pwr_sta2nd_offs = 0x170,
266 .sram_pdn_bits = BIT(8),
267 .sram_pdn_ack_bits = BIT(12),
268 .bp_infracfg = {
269 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1,
270 MT8188_TOP_AXI_PROT_EN_SET,
271 MT8188_TOP_AXI_PROT_EN_CLR,
272 MT8188_TOP_AXI_PROT_EN_STA),
273 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2,
274 MT8188_TOP_AXI_PROT_EN_MM_2_SET,
275 MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
276 MT8188_TOP_AXI_PROT_EN_MM_2_STA),
277 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3,
278 MT8188_TOP_AXI_PROT_EN_SET,
279 MT8188_TOP_AXI_PROT_EN_CLR,
280 MT8188_TOP_AXI_PROT_EN_STA),
281 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4,
282 MT8188_TOP_AXI_PROT_EN_MM_2_SET,
283 MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
284 MT8188_TOP_AXI_PROT_EN_MM_2_STA),
285 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5,
286 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
287 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
288 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
289 },
290 },
291 [MT8188_POWER_DOMAIN_VDOSYS0] = {
292 .name = "vdosys0",
293 .sta_mask = BIT(13),
294 .ctl_offs = 0x368,
295 .pwr_sta_offs = 0x16C,
296 .pwr_sta2nd_offs = 0x170,
297 .sram_pdn_bits = BIT(8),
298 .sram_pdn_ack_bits = BIT(12),
299 .bp_infracfg = {
300 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1,
301 MT8188_TOP_AXI_PROT_EN_MM_SET,
302 MT8188_TOP_AXI_PROT_EN_MM_CLR,
303 MT8188_TOP_AXI_PROT_EN_MM_STA),
304 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2,
305 MT8188_TOP_AXI_PROT_EN_SET,
306 MT8188_TOP_AXI_PROT_EN_CLR,
307 MT8188_TOP_AXI_PROT_EN_STA),
308 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3,
309 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
310 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
311 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
312 },
313 },
314 [MT8188_POWER_DOMAIN_VDOSYS1] = {
315 .name = "vdosys1",
316 .sta_mask = BIT(14),
317 .ctl_offs = 0x36C,
318 .pwr_sta_offs = 0x16C,
319 .pwr_sta2nd_offs = 0x170,
320 .sram_pdn_bits = BIT(8),
321 .sram_pdn_ack_bits = BIT(12),
322 .bp_infracfg = {
323 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1,
324 MT8188_TOP_AXI_PROT_EN_MM_SET,
325 MT8188_TOP_AXI_PROT_EN_MM_CLR,
326 MT8188_TOP_AXI_PROT_EN_MM_STA),
327 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2,
328 MT8188_TOP_AXI_PROT_EN_MM_SET,
329 MT8188_TOP_AXI_PROT_EN_MM_CLR,
330 MT8188_TOP_AXI_PROT_EN_MM_STA),
331 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3,
332 MT8188_TOP_AXI_PROT_EN_MM_2_SET,
333 MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
334 MT8188_TOP_AXI_PROT_EN_MM_2_STA),
335 },
336 },
337 [MT8188_POWER_DOMAIN_DP_TX] = {
338 .name = "dp_tx",
339 .sta_mask = BIT(16),
340 .ctl_offs = 0x374,
341 .pwr_sta_offs = 0x16C,
342 .pwr_sta2nd_offs = 0x170,
343 .sram_pdn_bits = BIT(8),
344 .sram_pdn_ack_bits = BIT(12),
345 .bp_infracfg = {
346 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1,
347 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
348 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
349 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
350 },
351 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
352 },
353 [MT8188_POWER_DOMAIN_EDP_TX] = {
354 .name = "edp_tx",
355 .sta_mask = BIT(17),
356 .ctl_offs = 0x378,
357 .pwr_sta_offs = 0x16C,
358 .pwr_sta2nd_offs = 0x170,
359 .sram_pdn_bits = BIT(8),
360 .sram_pdn_ack_bits = BIT(12),
361 .bp_infracfg = {
362 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1,
363 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
364 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
365 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
366 },
367 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
368 },
369 [MT8188_POWER_DOMAIN_VPPSYS1] = {
370 .name = "vppsys1",
371 .sta_mask = BIT(12),
372 .ctl_offs = 0x364,
373 .pwr_sta_offs = 0x16C,
374 .pwr_sta2nd_offs = 0x170,
375 .sram_pdn_bits = BIT(8),
376 .sram_pdn_ack_bits = BIT(12),
377 .bp_infracfg = {
378 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1,
379 MT8188_TOP_AXI_PROT_EN_MM_SET,
380 MT8188_TOP_AXI_PROT_EN_MM_CLR,
381 MT8188_TOP_AXI_PROT_EN_MM_STA),
382 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2,
383 MT8188_TOP_AXI_PROT_EN_MM_SET,
384 MT8188_TOP_AXI_PROT_EN_MM_CLR,
385 MT8188_TOP_AXI_PROT_EN_MM_STA),
386 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3,
387 MT8188_TOP_AXI_PROT_EN_MM_2_SET,
388 MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
389 MT8188_TOP_AXI_PROT_EN_MM_2_STA),
390 },
391 },
392 [MT8188_POWER_DOMAIN_WPE] = {
393 .name = "wpe",
394 .sta_mask = BIT(15),
395 .ctl_offs = 0x370,
396 .pwr_sta_offs = 0x16C,
397 .pwr_sta2nd_offs = 0x170,
398 .sram_pdn_bits = BIT(8),
399 .sram_pdn_ack_bits = BIT(12),
400 .bp_infracfg = {
401 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1,
402 MT8188_TOP_AXI_PROT_EN_MM_2_SET,
403 MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
404 MT8188_TOP_AXI_PROT_EN_MM_2_STA),
405 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2,
406 MT8188_TOP_AXI_PROT_EN_MM_2_SET,
407 MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
408 MT8188_TOP_AXI_PROT_EN_MM_2_STA),
409 },
410 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
411 },
412 [MT8188_POWER_DOMAIN_VDEC0] = {
413 .name = "vdec0",
414 .sta_mask = BIT(19),
415 .ctl_offs = 0x380,
416 .pwr_sta_offs = 0x16C,
417 .pwr_sta2nd_offs = 0x170,
418 .sram_pdn_bits = BIT(8),
419 .sram_pdn_ack_bits = BIT(12),
420 .bp_infracfg = {
421 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1,
422 MT8188_TOP_AXI_PROT_EN_MM_SET,
423 MT8188_TOP_AXI_PROT_EN_MM_CLR,
424 MT8188_TOP_AXI_PROT_EN_MM_STA),
425 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2,
426 MT8188_TOP_AXI_PROT_EN_MM_2_SET,
427 MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
428 MT8188_TOP_AXI_PROT_EN_MM_2_STA),
429 },
430 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
431 },
432 [MT8188_POWER_DOMAIN_VDEC1] = {
433 .name = "vdec1",
434 .sta_mask = BIT(20),
435 .ctl_offs = 0x384,
436 .pwr_sta_offs = 0x16C,
437 .pwr_sta2nd_offs = 0x170,
438 .sram_pdn_bits = BIT(8),
439 .sram_pdn_ack_bits = BIT(12),
440 .bp_infracfg = {
441 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1,
442 MT8188_TOP_AXI_PROT_EN_MM_SET,
443 MT8188_TOP_AXI_PROT_EN_MM_CLR,
444 MT8188_TOP_AXI_PROT_EN_MM_STA),
445 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2,
446 MT8188_TOP_AXI_PROT_EN_MM_SET,
447 MT8188_TOP_AXI_PROT_EN_MM_CLR,
448 MT8188_TOP_AXI_PROT_EN_MM_STA),
449 },
450 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
451 },
452 [MT8188_POWER_DOMAIN_VENC] = {
453 .name = "venc",
454 .sta_mask = BIT(22),
455 .ctl_offs = 0x38C,
456 .pwr_sta_offs = 0x16C,
457 .pwr_sta2nd_offs = 0x170,
458 .sram_pdn_bits = BIT(8),
459 .sram_pdn_ack_bits = BIT(12),
460 .bp_infracfg = {
461 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1,
462 MT8188_TOP_AXI_PROT_EN_MM_SET,
463 MT8188_TOP_AXI_PROT_EN_MM_CLR,
464 MT8188_TOP_AXI_PROT_EN_MM_STA),
465 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2,
466 MT8188_TOP_AXI_PROT_EN_MM_SET,
467 MT8188_TOP_AXI_PROT_EN_MM_CLR,
468 MT8188_TOP_AXI_PROT_EN_MM_STA),
469 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3,
470 MT8188_TOP_AXI_PROT_EN_MM_2_SET,
471 MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
472 MT8188_TOP_AXI_PROT_EN_MM_2_STA),
473 },
474 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
475 },
476 [MT8188_POWER_DOMAIN_IMG_VCORE] = {
477 .name = "vcore",
478 .sta_mask = BIT(28),
479 .ctl_offs = 0x3A4,
480 .pwr_sta_offs = 0x16C,
481 .pwr_sta2nd_offs = 0x170,
482 .bp_infracfg = {
483 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1,
484 MT8188_TOP_AXI_PROT_EN_MM_SET,
485 MT8188_TOP_AXI_PROT_EN_MM_CLR,
486 MT8188_TOP_AXI_PROT_EN_MM_STA),
487 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2,
488 MT8188_TOP_AXI_PROT_EN_MM_SET,
489 MT8188_TOP_AXI_PROT_EN_MM_CLR,
490 MT8188_TOP_AXI_PROT_EN_MM_STA),
491 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3,
492 MT8188_TOP_AXI_PROT_EN_MM_2_SET,
493 MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
494 MT8188_TOP_AXI_PROT_EN_MM_2_STA),
495 },
496 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
497 },
498 [MT8188_POWER_DOMAIN_IMG_MAIN] = {
499 .name = "img_main",
500 .sta_mask = BIT(29),
501 .ctl_offs = 0x3A8,
502 .pwr_sta_offs = 0x16C,
503 .pwr_sta2nd_offs = 0x170,
504 .sram_pdn_bits = BIT(8),
505 .sram_pdn_ack_bits = BIT(12),
506 .bp_infracfg = {
507 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1,
508 MT8188_TOP_AXI_PROT_EN_MM_2_SET,
509 MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
510 MT8188_TOP_AXI_PROT_EN_MM_2_STA),
511 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2,
512 MT8188_TOP_AXI_PROT_EN_MM_2_SET,
513 MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
514 MT8188_TOP_AXI_PROT_EN_MM_2_STA),
515 },
516 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
517 },
518 [MT8188_POWER_DOMAIN_DIP] = {
519 .name = "dip",
520 .sta_mask = BIT(30),
521 .ctl_offs = 0x3AC,
522 .pwr_sta_offs = 0x16C,
523 .pwr_sta2nd_offs = 0x170,
524 .sram_pdn_bits = BIT(8),
525 .sram_pdn_ack_bits = BIT(12),
526 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
527 },
528 [MT8188_POWER_DOMAIN_IPE] = {
529 .name = "ipe",
530 .sta_mask = BIT(31),
531 .ctl_offs = 0x3B0,
532 .pwr_sta_offs = 0x16C,
533 .pwr_sta2nd_offs = 0x170,
534 .sram_pdn_bits = BIT(8),
535 .sram_pdn_ack_bits = BIT(12),
536 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
537 },
538 [MT8188_POWER_DOMAIN_CAM_VCORE] = {
539 .name = "cam_vcore",
540 .sta_mask = BIT(27),
541 .ctl_offs = 0x3A0,
542 .pwr_sta_offs = 0x16C,
543 .pwr_sta2nd_offs = 0x170,
544 .bp_infracfg = {
545 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1,
546 MT8188_TOP_AXI_PROT_EN_MM_SET,
547 MT8188_TOP_AXI_PROT_EN_MM_CLR,
548 MT8188_TOP_AXI_PROT_EN_MM_STA),
549 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2,
550 MT8188_TOP_AXI_PROT_EN_2_SET,
551 MT8188_TOP_AXI_PROT_EN_2_CLR,
552 MT8188_TOP_AXI_PROT_EN_2_STA),
553 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3,
554 MT8188_TOP_AXI_PROT_EN_1_SET,
555 MT8188_TOP_AXI_PROT_EN_1_CLR,
556 MT8188_TOP_AXI_PROT_EN_1_STA),
557 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4,
558 MT8188_TOP_AXI_PROT_EN_MM_SET,
559 MT8188_TOP_AXI_PROT_EN_MM_CLR,
560 MT8188_TOP_AXI_PROT_EN_MM_STA),
561 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5,
562 MT8188_TOP_AXI_PROT_EN_MM_2_SET,
563 MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
564 MT8188_TOP_AXI_PROT_EN_MM_2_STA),
565 },
566 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
567 },
568 [MT8188_POWER_DOMAIN_CAM_MAIN] = {
569 .name = "cam_main",
570 .sta_mask = BIT(24),
571 .ctl_offs = 0x394,
572 .pwr_sta_offs = 0x16C,
573 .pwr_sta2nd_offs = 0x170,
574 .sram_pdn_bits = BIT(8),
575 .sram_pdn_ack_bits = BIT(12),
576 .bp_infracfg = {
577 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1,
578 MT8188_TOP_AXI_PROT_EN_MM_2_SET,
579 MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
580 MT8188_TOP_AXI_PROT_EN_MM_2_STA),
581 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2,
582 MT8188_TOP_AXI_PROT_EN_2_SET,
583 MT8188_TOP_AXI_PROT_EN_2_CLR,
584 MT8188_TOP_AXI_PROT_EN_2_STA),
585 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3,
586 MT8188_TOP_AXI_PROT_EN_MM_2_SET,
587 MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
588 MT8188_TOP_AXI_PROT_EN_MM_2_STA),
589 BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4,
590 MT8188_TOP_AXI_PROT_EN_2_SET,
591 MT8188_TOP_AXI_PROT_EN_2_CLR,
592 MT8188_TOP_AXI_PROT_EN_2_STA),
593 },
594 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
595 },
596 [MT8188_POWER_DOMAIN_CAM_SUBA] = {
597 .name = "cam_suba",
598 .sta_mask = BIT(25),
599 .ctl_offs = 0x398,
600 .pwr_sta_offs = 0x16C,
601 .pwr_sta2nd_offs = 0x170,
602 .sram_pdn_bits = BIT(8),
603 .sram_pdn_ack_bits = BIT(12),
604 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
605 },
606 [MT8188_POWER_DOMAIN_CAM_SUBB] = {
607 .name = "cam_subb",
608 .sta_mask = BIT(26),
609 .ctl_offs = 0x39C,
610 .pwr_sta_offs = 0x16C,
611 .pwr_sta2nd_offs = 0x170,
612 .sram_pdn_bits = BIT(8),
613 .sram_pdn_ack_bits = BIT(12),
614 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
615 },
616};
617
618static const struct scpsys_soc_data mt8188_scpsys_data = {
619 .domains_data = scpsys_domain_data_mt8188,
620 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8188),
621};
622
623#endif /* __SOC_MEDIATEK_MT8188_PM_DOMAINS_H */
Linux 6.x block layer and io_uring tree(s)