[linux-block.git] / drivers / fpga / zynq-fpga.c

/*
 * Copyright (c) 2011-2015 Xilinx Inc.
 * Copyright (c) 2015, National Instruments Corp.
 *
 * FPGA Manager Driver for Xilinx Zynq, heavily based on xdevcfg driver
 * in their vendor tree.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/fpga/fpga-mgr.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/pm.h>
#include <linux/regmap.h>
#include <linux/string.h>

/* Offsets into SLCR regmap */

/* FPGA Software Reset Control */
#define SLCR_FPGA_RST_CTRL_OFFSET	0x240
/* Level Shifters Enable */
#define SLCR_LVL_SHFTR_EN_OFFSET	0x900

/* Constant Definitions */

/* Control Register */
#define CTRL_OFFSET			0x00
/* Lock Register */
#define LOCK_OFFSET			0x04
/* Interrupt Status Register */
#define INT_STS_OFFSET			0x0c
/* Interrupt Mask Register */
#define INT_MASK_OFFSET			0x10
/* Status Register */
#define STATUS_OFFSET			0x14
/* DMA Source Address Register */
#define DMA_SRC_ADDR_OFFSET		0x18
/* DMA Destination Address Reg */
#define DMA_DST_ADDR_OFFSET		0x1c
/* DMA Source Transfer Length */
#define DMA_SRC_LEN_OFFSET		0x20
/* DMA Destination Transfer */
#define DMA_DEST_LEN_OFFSET		0x24
/* Unlock Register */
#define UNLOCK_OFFSET			0x34
/* Misc. Control Register */
#define MCTRL_OFFSET			0x80

/* Control Register Bit definitions */

/* Signal to reset FPGA */
#define CTRL_PCFG_PROG_B_MASK		BIT(30)
/* Enable PCAP for PR */
#define CTRL_PCAP_PR_MASK		BIT(27)
/* Enable PCAP */
#define CTRL_PCAP_MODE_MASK		BIT(26)

/* Miscellaneous Control Register bit definitions */
/* Internal PCAP loopback */
#define MCTRL_PCAP_LPBK_MASK		BIT(4)

/* Status register bit definitions */

/* FPGA init status */
#define STATUS_DMA_Q_F			BIT(31)
#define STATUS_PCFG_INIT_MASK		BIT(4)

/* Interrupt Status/Mask Register Bit definitions */
/* DMA command done */
#define IXR_DMA_DONE_MASK		BIT(13)
/* DMA and PCAP cmd done */
#define IXR_D_P_DONE_MASK		BIT(12)
 /* FPGA programmed */
#define IXR_PCFG_DONE_MASK		BIT(2)
#define IXR_ERROR_FLAGS_MASK		0x00F0C860
#define IXR_ALL_MASK			0xF8F7F87F

/* Miscellaneous constant values */

/* Invalid DMA addr */
#define DMA_INVALID_ADDRESS		GENMASK(31, 0)
/* Used to unlock the dev */
#define UNLOCK_MASK			0x757bdf0d
/* Timeout for DMA to complete */
#define DMA_DONE_TIMEOUT		msecs_to_jiffies(1000)
/* Timeout for polling reset bits */
#define INIT_POLL_TIMEOUT		2500000
/* Delay for polling reset bits */
#define INIT_POLL_DELAY			20

/* Masks for controlling stuff in SLCR */
/* Disable all Level shifters */
#define LVL_SHFTR_DISABLE_ALL_MASK	0x0
/* Enable Level shifters from PS to PL */
#define LVL_SHFTR_ENABLE_PS_TO_PL	0xa
/* Enable Level shifters from PL to PS */
#define LVL_SHFTR_ENABLE_PL_TO_PS	0xf
/* Enable global resets */
#define FPGA_RST_ALL_MASK		0xf
/* Disable global resets */
#define FPGA_RST_NONE_MASK		0x0

struct zynq_fpga_priv {
	int irq;
	struct clk *clk;

	void __iomem *io_base;
	struct regmap *slcr;

	struct completion dma_done;
};

static inline void zynq_fpga_write(struct zynq_fpga_priv *priv, u32 offset,
				   u32 val)
{
	writel(val, priv->io_base + offset);
}

static inline u32 zynq_fpga_read(const struct zynq_fpga_priv *priv,
				 u32 offset)
{
	return readl(priv->io_base + offset);
}

#define zynq_fpga_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \
	readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
			   timeout_us)

/* Cause the specified irq mask bits to generate IRQs */
static inline void zynq_fpga_set_irq(struct zynq_fpga_priv *priv, u32 enable)
{
	zynq_fpga_write(priv, INT_MASK_OFFSET, ~enable);
}

static irqreturn_t zynq_fpga_isr(int irq, void *data)
{
	struct zynq_fpga_priv *priv = data;

	/* disable DMA and error IRQs */
	zynq_fpga_set_irq(priv, 0);

	complete(&priv->dma_done);

	return IRQ_HANDLED;
}

/* Sanity check the proposed bitstream. It must start with the sync word in
 * the correct byte order, and be dword aligned. The input is a Xilinx .bin
 * file with every 32 bit quantity swapped.
 */
static bool zynq_fpga_has_sync(const u8 *buf, size_t count)
{
	for (; count >= 4; buf += 4, count -= 4)
		if (buf[0] == 0x66 && buf[1] == 0x55 && buf[2] == 0x99 &&
		    buf[3] == 0xaa)
			return true;
	return false;
}

static int zynq_fpga_ops_write_init(struct fpga_manager *mgr,
				    struct fpga_image_info *info,
				    const char *buf, size_t count)
{
	struct zynq_fpga_priv *priv;
	u32 ctrl, status;
	int err;

	priv = mgr->priv;

	err = clk_enable(priv->clk);
	if (err)
		return err;

	/* don't globally reset PL if we're doing partial reconfig */
	if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
		if (!zynq_fpga_has_sync(buf, count)) {
			dev_err(&mgr->dev,
				"Invalid bitstream, could not find a sync word. Bitstream must be a byte swapped .bin file\n");
			err = -EINVAL;
			goto out_err;
		}

		/* assert AXI interface resets */
		regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,
			     FPGA_RST_ALL_MASK);

		/* disable all level shifters */
		regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
			     LVL_SHFTR_DISABLE_ALL_MASK);
		/* enable level shifters from PS to PL */
		regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
			     LVL_SHFTR_ENABLE_PS_TO_PL);

		/* create a rising edge on PCFG_INIT. PCFG_INIT follows
		 * PCFG_PROG_B, so we need to poll it after setting PCFG_PROG_B
		 * to make sure the rising edge actually happens.
		 * Note: PCFG_PROG_B is low active, sequence as described in
		 * UG585 v1.10 page 211
		 */
		ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
		ctrl |= CTRL_PCFG_PROG_B_MASK;

		zynq_fpga_write(priv, CTRL_OFFSET, ctrl);

		err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
					     status & STATUS_PCFG_INIT_MASK,
					     INIT_POLL_DELAY,
					     INIT_POLL_TIMEOUT);
		if (err) {
			dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");
			goto out_err;
		}

		ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
		ctrl &= ~CTRL_PCFG_PROG_B_MASK;

		zynq_fpga_write(priv, CTRL_OFFSET, ctrl);

		err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
					     !(status & STATUS_PCFG_INIT_MASK),
					     INIT_POLL_DELAY,
					     INIT_POLL_TIMEOUT);
		if (err) {
			dev_err(&mgr->dev, "Timeout waiting for !PCFG_INIT\n");
			goto out_err;
		}

		ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
		ctrl |= CTRL_PCFG_PROG_B_MASK;

		zynq_fpga_write(priv, CTRL_OFFSET, ctrl);

		err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
					     status & STATUS_PCFG_INIT_MASK,
					     INIT_POLL_DELAY,
					     INIT_POLL_TIMEOUT);
		if (err) {
			dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");
			goto out_err;
		}
	}

	/* set configuration register with following options:
	 * - enable PCAP interface
	 * - set throughput for maximum speed
	 * - set CPU in user mode
	 */
	ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
	zynq_fpga_write(priv, CTRL_OFFSET,
			(CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK | ctrl));

	/* check that we have room in the command queue */
	status = zynq_fpga_read(priv, STATUS_OFFSET);
	if (status & STATUS_DMA_Q_F) {
		dev_err(&mgr->dev, "DMA command queue full\n");
		err = -EBUSY;
		goto out_err;
	}

	/* ensure internal PCAP loopback is disabled */
	ctrl = zynq_fpga_read(priv, MCTRL_OFFSET);
	zynq_fpga_write(priv, MCTRL_OFFSET, (~MCTRL_PCAP_LPBK_MASK & ctrl));

	clk_disable(priv->clk);

	return 0;

out_err:
	clk_disable(priv->clk);

	return err;
}

static int zynq_fpga_ops_write(struct fpga_manager *mgr,
			       const char *buf, size_t count)
{
	struct zynq_fpga_priv *priv;
	const char *why;
	int err;
	char *kbuf;
	size_t in_count;
	dma_addr_t dma_addr;
	u32 transfer_length;
	u32 intr_status;

	in_count = count;
	priv = mgr->priv;

	kbuf =
	    dma_alloc_coherent(mgr->dev.parent, count, &dma_addr, GFP_KERNEL);
	if (!kbuf)
		return -ENOMEM;

	memcpy(kbuf, buf, count);

	/* enable clock */
	err = clk_enable(priv->clk);
	if (err)
		goto out_free;

	zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);

	reinit_completion(&priv->dma_done);

	/* enable DMA and error IRQs */
	zynq_fpga_set_irq(priv, IXR_D_P_DONE_MASK | IXR_ERROR_FLAGS_MASK);

	/* the +1 in the src addr is used to hold off on DMA_DONE IRQ
	 * until both AXI and PCAP are done ...
	 */
	zynq_fpga_write(priv, DMA_SRC_ADDR_OFFSET, (u32)(dma_addr) + 1);
	zynq_fpga_write(priv, DMA_DST_ADDR_OFFSET, (u32)DMA_INVALID_ADDRESS);

	/* convert #bytes to #words */
	transfer_length = (count + 3) / 4;

	zynq_fpga_write(priv, DMA_SRC_LEN_OFFSET, transfer_length);
	zynq_fpga_write(priv, DMA_DEST_LEN_OFFSET, 0);

	wait_for_completion(&priv->dma_done);

	intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
	zynq_fpga_write(priv, INT_STS_OFFSET, intr_status);

	if (intr_status & IXR_ERROR_FLAGS_MASK) {
		why = "DMA reported error";
		err = -EIO;
		goto out_report;
	}

	if (!((intr_status & IXR_D_P_DONE_MASK) == IXR_D_P_DONE_MASK)) {
		why = "DMA did not complete";
		err = -EIO;
		goto out_report;
	}

	err = 0;
	goto out_clk;

out_report:
	dev_err(&mgr->dev,
		"%s: INT_STS:0x%x CTRL:0x%x LOCK:0x%x INT_MASK:0x%x STATUS:0x%x MCTRL:0x%x\n",
		why,
		intr_status,
		zynq_fpga_read(priv, CTRL_OFFSET),
		zynq_fpga_read(priv, LOCK_OFFSET),
		zynq_fpga_read(priv, INT_MASK_OFFSET),
		zynq_fpga_read(priv, STATUS_OFFSET),
		zynq_fpga_read(priv, MCTRL_OFFSET));

out_clk:
	clk_disable(priv->clk);

out_free:
	dma_free_coherent(mgr->dev.parent, count, kbuf, dma_addr);
	return err;
}

static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr,
					struct fpga_image_info *info)
{
	struct zynq_fpga_priv *priv = mgr->priv;
	int err;
	u32 intr_status;

	err = clk_enable(priv->clk);
	if (err)
		return err;

	err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status,
				     intr_status & IXR_PCFG_DONE_MASK,
				     INIT_POLL_DELAY,
				     INIT_POLL_TIMEOUT);

	clk_disable(priv->clk);

	if (err)
		return err;

	/* for the partial reconfig case we didn't touch the level shifters */
	if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
		/* enable level shifters from PL to PS */
		regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
			     LVL_SHFTR_ENABLE_PL_TO_PS);

		/* deassert AXI interface resets */
		regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,
			     FPGA_RST_NONE_MASK);
	}

	return 0;
}

static enum fpga_mgr_states zynq_fpga_ops_state(struct fpga_manager *mgr)
{
	int err;
	u32 intr_status;
	struct zynq_fpga_priv *priv;

	priv = mgr->priv;

	err = clk_enable(priv->clk);
	if (err)
		return FPGA_MGR_STATE_UNKNOWN;

	intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
	clk_disable(priv->clk);

	if (intr_status & IXR_PCFG_DONE_MASK)
		return FPGA_MGR_STATE_OPERATING;

	return FPGA_MGR_STATE_UNKNOWN;
}

static const struct fpga_manager_ops zynq_fpga_ops = {
	.initial_header_size = 128,
	.state = zynq_fpga_ops_state,
	.write_init = zynq_fpga_ops_write_init,
	.write = zynq_fpga_ops_write,
	.write_complete = zynq_fpga_ops_write_complete,
};

static int zynq_fpga_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct zynq_fpga_priv *priv;
	struct resource *res;
	int err;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->io_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(priv->io_base))
		return PTR_ERR(priv->io_base);

	priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node,
		"syscon");
	if (IS_ERR(priv->slcr)) {
		dev_err(dev, "unable to get zynq-slcr regmap\n");
		return PTR_ERR(priv->slcr);
	}

	init_completion(&priv->dma_done);

	priv->irq = platform_get_irq(pdev, 0);
	if (priv->irq < 0) {
		dev_err(dev, "No IRQ available\n");
		return priv->irq;
	}

	priv->clk = devm_clk_get(dev, "ref_clk");
	if (IS_ERR(priv->clk)) {
		dev_err(dev, "input clock not found\n");
		return PTR_ERR(priv->clk);
	}

	err = clk_prepare_enable(priv->clk);
	if (err) {
		dev_err(dev, "unable to enable clock\n");
		return err;
	}

	/* unlock the device */
	zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK);

	zynq_fpga_set_irq(priv, 0);
	zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
	err = devm_request_irq(dev, priv->irq, zynq_fpga_isr, 0, dev_name(dev),
			       priv);
	if (err) {
		dev_err(dev, "unable to request IRQ\n");
		clk_disable_unprepare(priv->clk);
		return err;
	}

	clk_disable(priv->clk);

	err = fpga_mgr_register(dev, "Xilinx Zynq FPGA Manager",
				&zynq_fpga_ops, priv);
	if (err) {
		dev_err(dev, "unable to register FPGA manager\n");
		clk_unprepare(priv->clk);
		return err;
	}

	return 0;
}

static int zynq_fpga_remove(struct platform_device *pdev)
{
	struct zynq_fpga_priv *priv;
	struct fpga_manager *mgr;

	mgr = platform_get_drvdata(pdev);
	priv = mgr->priv;

	fpga_mgr_unregister(&pdev->dev);

	clk_unprepare(priv->clk);

	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id zynq_fpga_of_match[] = {
	{ .compatible = "xlnx,zynq-devcfg-1.0", },
	{},
};

MODULE_DEVICE_TABLE(of, zynq_fpga_of_match);
#endif

static struct platform_driver zynq_fpga_driver = {
	.probe = zynq_fpga_probe,
	.remove = zynq_fpga_remove,
	.driver = {
		.name = "zynq_fpga_manager",
		.of_match_table = of_match_ptr(zynq_fpga_of_match),
	},
};

module_platform_driver(zynq_fpga_driver);

MODULE_AUTHOR("Moritz Fischer <moritz.fischer@ettus.com>");
MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>");
MODULE_DESCRIPTION("Xilinx Zynq FPGA Manager");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
37784706 MF	1	/*
	2	* Copyright (c) 2011-2015 Xilinx Inc.
	3	* Copyright (c) 2015, National Instruments Corp.
	4	*
	5	* FPGA Manager Driver for Xilinx Zynq, heavily based on xdevcfg driver
	6	* in their vendor tree.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; version 2 of the License.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
	18	#include <linux/clk.h>
	19	#include <linux/completion.h>
	20	#include <linux/delay.h>
	21	#include <linux/dma-mapping.h>
	22	#include <linux/fpga/fpga-mgr.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/io.h>
	25	#include <linux/iopoll.h>
	26	#include <linux/module.h>
	27	#include <linux/mfd/syscon.h>
	28	#include <linux/of_address.h>
	29	#include <linux/of_irq.h>
	30	#include <linux/pm.h>
	31	#include <linux/regmap.h>
	32	#include <linux/string.h>
	33
	34	/* Offsets into SLCR regmap */
	35
	36	/* FPGA Software Reset Control */
	37	#define SLCR_FPGA_RST_CTRL_OFFSET 0x240
	38	/* Level Shifters Enable */
	39	#define SLCR_LVL_SHFTR_EN_OFFSET 0x900
	40
	41	/* Constant Definitions */
	42
	43	/* Control Register */
	44	#define CTRL_OFFSET 0x00
	45	/* Lock Register */
	46	#define LOCK_OFFSET 0x04
	47	/* Interrupt Status Register */
	48	#define INT_STS_OFFSET 0x0c
	49	/* Interrupt Mask Register */
	50	#define INT_MASK_OFFSET 0x10
	51	/* Status Register */
	52	#define STATUS_OFFSET 0x14
	53	/* DMA Source Address Register */
	54	#define DMA_SRC_ADDR_OFFSET 0x18
	55	/* DMA Destination Address Reg */
	56	#define DMA_DST_ADDR_OFFSET 0x1c
	57	/* DMA Source Transfer Length */
	58	#define DMA_SRC_LEN_OFFSET 0x20
	59	/* DMA Destination Transfer */
	60	#define DMA_DEST_LEN_OFFSET 0x24
	61	/* Unlock Register */
	62	#define UNLOCK_OFFSET 0x34
	63	/* Misc. Control Register */
	64	#define MCTRL_OFFSET 0x80
65
66	/* Control Register Bit definitions */
67
68	/* Signal to reset FPGA */
69	#define CTRL_PCFG_PROG_B_MASK BIT(30)
70	/* Enable PCAP for PR */
71	#define CTRL_PCAP_PR_MASK BIT(27)
72	/* Enable PCAP */
73	#define CTRL_PCAP_MODE_MASK BIT(26)
74
75	/* Miscellaneous Control Register bit definitions */
76	/* Internal PCAP loopback */
77	#define MCTRL_PCAP_LPBK_MASK BIT(4)
78
79	/* Status register bit definitions */
80
81	/* FPGA init status */
82	#define STATUS_DMA_Q_F BIT(31)
83	#define STATUS_PCFG_INIT_MASK BIT(4)
84
85	/* Interrupt Status/Mask Register Bit definitions */
86	/* DMA command done */
87	#define IXR_DMA_DONE_MASK BIT(13)
88	/* DMA and PCAP cmd done */
89	#define IXR_D_P_DONE_MASK BIT(12)
90	/* FPGA programmed */
91	#define IXR_PCFG_DONE_MASK BIT(2)
6b45e0f2	92	#define IXR_ERROR_FLAGS_MASK 0x00F0C860
37784706 MF	93	#define IXR_ALL_MASK 0xF8F7F87F
	94
	95	/* Miscellaneous constant values */
	96
	97	/* Invalid DMA addr */
	98	#define DMA_INVALID_ADDRESS GENMASK(31, 0)
	99	/* Used to unlock the dev */
	100	#define UNLOCK_MASK 0x757bdf0d
	101	/* Timeout for DMA to complete */
	102	#define DMA_DONE_TIMEOUT msecs_to_jiffies(1000)
	103	/* Timeout for polling reset bits */
	104	#define INIT_POLL_TIMEOUT 2500000
	105	/* Delay for polling reset bits */
	106	#define INIT_POLL_DELAY 20
	107
	108	/* Masks for controlling stuff in SLCR */
	109	/* Disable all Level shifters */
	110	#define LVL_SHFTR_DISABLE_ALL_MASK 0x0
	111	/* Enable Level shifters from PS to PL */
	112	#define LVL_SHFTR_ENABLE_PS_TO_PL 0xa
	113	/* Enable Level shifters from PL to PS */
	114	#define LVL_SHFTR_ENABLE_PL_TO_PS 0xf
	115	/* Enable global resets */
	116	#define FPGA_RST_ALL_MASK 0xf
	117	/* Disable global resets */
	118	#define FPGA_RST_NONE_MASK 0x0
	119
	120	struct zynq_fpga_priv {
37784706 MF	121	int irq;
	122	struct clk *clk;
	123
	124	void __iomem *io_base;
	125	struct regmap *slcr;
	126
	127	struct completion dma_done;
	128	};
	129
	130	static inline void zynq_fpga_write(struct zynq_fpga_priv *priv, u32 offset,
	131	u32 val)
	132	{
	133	writel(val, priv->io_base + offset);
	134	}
	135
	136	static inline u32 zynq_fpga_read(const struct zynq_fpga_priv *priv,
	137	u32 offset)
	138	{
	139	return readl(priv->io_base + offset);
	140	}
	141
	142	#define zynq_fpga_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \
	143	readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
	144	timeout_us)
	145
6b45e0f2 JG	146	/* Cause the specified irq mask bits to generate IRQs */
6b45e0f2 JG	147	static inline void zynq_fpga_set_irq(struct zynq_fpga_priv *priv, u32 enable)
37784706	148	{
6b45e0f2	149	zynq_fpga_write(priv, INT_MASK_OFFSET, ~enable);
37784706 MF	150	}
	151
	152	static irqreturn_t zynq_fpga_isr(int irq, void *data)
	153	{
	154	struct zynq_fpga_priv *priv = data;
	155
	156	/* disable DMA and error IRQs */
6b45e0f2	157	zynq_fpga_set_irq(priv, 0);
37784706 MF	158
	159	complete(&priv->dma_done);
	160
	161	return IRQ_HANDLED;
	162	}
	163
b496df86 JG	164	/* Sanity check the proposed bitstream. It must start with the sync word in
	165	* the correct byte order, and be dword aligned. The input is a Xilinx .bin
	166	* file with every 32 bit quantity swapped.
	167	*/
	168	static bool zynq_fpga_has_sync(const u8 *buf, size_t count)
	169	{
	170	for (; count >= 4; buf += 4, count -= 4)
	171	if (buf[0] == 0x66 && buf[1] == 0x55 && buf[2] == 0x99 &&
	172	buf[3] == 0xaa)
	173	return true;
	174	return false;
	175	}
	176
1df2865f AT	177	static int zynq_fpga_ops_write_init(struct fpga_manager *mgr,
1df2865f AT	178	struct fpga_image_info *info,
37784706 MF	179	const char *buf, size_t count)
	180	{
	181	struct zynq_fpga_priv *priv;
	182	u32 ctrl, status;
	183	int err;
	184
	185	priv = mgr->priv;
	186
	187	err = clk_enable(priv->clk);
	188	if (err)
	189	return err;
	190
	191	/* don't globally reset PL if we're doing partial reconfig */
1df2865f	192	if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
b496df86 JG	193	if (!zynq_fpga_has_sync(buf, count)) {
	194	dev_err(&mgr->dev,
	195	"Invalid bitstream, could not find a sync word. Bitstream must be a byte swapped .bin file\n");
	196	err = -EINVAL;
	197	goto out_err;
	198	}
	199
37784706 MF	200	/* assert AXI interface resets */
	201	regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,
	202	FPGA_RST_ALL_MASK);
	203
	204	/* disable all level shifters */
	205	regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
	206	LVL_SHFTR_DISABLE_ALL_MASK);
	207	/* enable level shifters from PS to PL */
	208	regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
	209	LVL_SHFTR_ENABLE_PS_TO_PL);
	210
	211	/* create a rising edge on PCFG_INIT. PCFG_INIT follows
	212	* PCFG_PROG_B, so we need to poll it after setting PCFG_PROG_B
	213	* to make sure the rising edge actually happens.
	214	* Note: PCFG_PROG_B is low active, sequence as described in
	215	* UG585 v1.10 page 211
	216	*/
	217	ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
	218	ctrl \|= CTRL_PCFG_PROG_B_MASK;
	219
	220	zynq_fpga_write(priv, CTRL_OFFSET, ctrl);
	221
	222	err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
	223	status & STATUS_PCFG_INIT_MASK,
	224	INIT_POLL_DELAY,
	225	INIT_POLL_TIMEOUT);
	226	if (err) {
80baf649	227	dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");
37784706 MF	228	goto out_err;
	229	}
	230
	231	ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
	232	ctrl &= ~CTRL_PCFG_PROG_B_MASK;
	233
	234	zynq_fpga_write(priv, CTRL_OFFSET, ctrl);
	235
	236	err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
	237	!(status & STATUS_PCFG_INIT_MASK),
	238	INIT_POLL_DELAY,
	239	INIT_POLL_TIMEOUT);
	240	if (err) {
80baf649	241	dev_err(&mgr->dev, "Timeout waiting for !PCFG_INIT\n");
37784706 MF	242	goto out_err;
	243	}
	244
	245	ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
	246	ctrl \|= CTRL_PCFG_PROG_B_MASK;
	247
	248	zynq_fpga_write(priv, CTRL_OFFSET, ctrl);
	249
	250	err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
	251	status & STATUS_PCFG_INIT_MASK,
	252	INIT_POLL_DELAY,
	253	INIT_POLL_TIMEOUT);
	254	if (err) {
80baf649	255	dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");
37784706 MF	256	goto out_err;
	257	}
	258	}
	259
	260	/* set configuration register with following options:
	261	* - enable PCAP interface
	262	* - set throughput for maximum speed
	263	* - set CPU in user mode
	264	*/
	265	ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
	266	zynq_fpga_write(priv, CTRL_OFFSET,
	267	(CTRL_PCAP_PR_MASK \| CTRL_PCAP_MODE_MASK \| ctrl));
	268
	269	/* check that we have room in the command queue */
	270	status = zynq_fpga_read(priv, STATUS_OFFSET);
	271	if (status & STATUS_DMA_Q_F) {
80baf649	272	dev_err(&mgr->dev, "DMA command queue full\n");
37784706 MF	273	err = -EBUSY;
	274	goto out_err;
	275	}
	276
	277	/* ensure internal PCAP loopback is disabled */
	278	ctrl = zynq_fpga_read(priv, MCTRL_OFFSET);
	279	zynq_fpga_write(priv, MCTRL_OFFSET, (~MCTRL_PCAP_LPBK_MASK & ctrl));
	280
	281	clk_disable(priv->clk);
	282
	283	return 0;
	284
	285	out_err:
	286	clk_disable(priv->clk);
	287
	288	return err;
	289	}
	290
	291	static int zynq_fpga_ops_write(struct fpga_manager *mgr,
	292	const char *buf, size_t count)
	293	{
	294	struct zynq_fpga_priv *priv;
6b45e0f2	295	const char *why;
37784706 MF	296	int err;
37784706 MF	297	char *kbuf;
4d10eaff	298	size_t in_count;
37784706	299	dma_addr_t dma_addr;
4d10eaff	300	u32 transfer_length;
37784706 MF	301	u32 intr_status;
	302
	303	in_count = count;
	304	priv = mgr->priv;
	305
80baf649 JG	306	kbuf =
80baf649 JG	307	dma_alloc_coherent(mgr->dev.parent, count, &dma_addr, GFP_KERNEL);
37784706 MF	308	if (!kbuf)
	309	return -ENOMEM;
	310
	311	memcpy(kbuf, buf, count);
	312
37784706 MF	313	/* enable clock */
	314	err = clk_enable(priv->clk);
	315	if (err)
	316	goto out_free;
	317
	318	zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
	319
	320	reinit_completion(&priv->dma_done);
	321
	322	/* enable DMA and error IRQs */
6b45e0f2	323	zynq_fpga_set_irq(priv, IXR_D_P_DONE_MASK \| IXR_ERROR_FLAGS_MASK);
37784706 MF	324
	325	/* the +1 in the src addr is used to hold off on DMA_DONE IRQ
	326	* until both AXI and PCAP are done ...
	327	*/
	328	zynq_fpga_write(priv, DMA_SRC_ADDR_OFFSET, (u32)(dma_addr) + 1);
	329	zynq_fpga_write(priv, DMA_DST_ADDR_OFFSET, (u32)DMA_INVALID_ADDRESS);
	330
	331	/* convert #bytes to #words */
	332	transfer_length = (count + 3) / 4;
	333
	334	zynq_fpga_write(priv, DMA_SRC_LEN_OFFSET, transfer_length);
	335	zynq_fpga_write(priv, DMA_DEST_LEN_OFFSET, 0);
	336
	337	wait_for_completion(&priv->dma_done);
	338
	339	intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
	340	zynq_fpga_write(priv, INT_STS_OFFSET, intr_status);
	341
6b45e0f2 JG	342	if (intr_status & IXR_ERROR_FLAGS_MASK) {
	343	why = "DMA reported error";
	344	err = -EIO;
	345	goto out_report;
	346	}
	347
37784706	348	if (!((intr_status & IXR_D_P_DONE_MASK) == IXR_D_P_DONE_MASK)) {
6b45e0f2 JG	349	why = "DMA did not complete";
	350	err = -EIO;
	351	goto out_report;
37784706 MF	352	}
37784706 MF	353
6b45e0f2 JG	354	err = 0;
	355	goto out_clk;
	356
	357	out_report:
	358	dev_err(&mgr->dev,
	359	"%s: INT_STS:0x%x CTRL:0x%x LOCK:0x%x INT_MASK:0x%x STATUS:0x%x MCTRL:0x%x\n",
	360	why,
	361	intr_status,
	362	zynq_fpga_read(priv, CTRL_OFFSET),
	363	zynq_fpga_read(priv, LOCK_OFFSET),
	364	zynq_fpga_read(priv, INT_MASK_OFFSET),
	365	zynq_fpga_read(priv, STATUS_OFFSET),
	366	zynq_fpga_read(priv, MCTRL_OFFSET));
	367
	368	out_clk:
37784706 MF	369	clk_disable(priv->clk);
	370
	371	out_free:
80baf649	372	dma_free_coherent(mgr->dev.parent, count, kbuf, dma_addr);
37784706 MF	373	return err;
	374	}
	375
1df2865f AT	376	static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr,
1df2865f AT	377	struct fpga_image_info *info)
37784706 MF	378	{
	379	struct zynq_fpga_priv *priv = mgr->priv;
	380	int err;
	381	u32 intr_status;
	382
	383	err = clk_enable(priv->clk);
	384	if (err)
	385	return err;
	386
	387	err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status,
	388	intr_status & IXR_PCFG_DONE_MASK,
	389	INIT_POLL_DELAY,
	390	INIT_POLL_TIMEOUT);
	391
	392	clk_disable(priv->clk);
	393
	394	if (err)
	395	return err;
	396
	397	/* for the partial reconfig case we didn't touch the level shifters */
1df2865f	398	if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
37784706 MF	399	/* enable level shifters from PL to PS */
	400	regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
	401	LVL_SHFTR_ENABLE_PL_TO_PS);
	402
	403	/* deassert AXI interface resets */
	404	regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,
	405	FPGA_RST_NONE_MASK);
	406	}
	407
	408	return 0;
	409	}
	410
	411	static enum fpga_mgr_states zynq_fpga_ops_state(struct fpga_manager *mgr)
	412	{
	413	int err;
	414	u32 intr_status;
	415	struct zynq_fpga_priv *priv;
	416
	417	priv = mgr->priv;
	418
	419	err = clk_enable(priv->clk);
	420	if (err)
	421	return FPGA_MGR_STATE_UNKNOWN;
	422
	423	intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
	424	clk_disable(priv->clk);
	425
	426	if (intr_status & IXR_PCFG_DONE_MASK)
	427	return FPGA_MGR_STATE_OPERATING;
	428
	429	return FPGA_MGR_STATE_UNKNOWN;
	430	}
	431
	432	static const struct fpga_manager_ops zynq_fpga_ops = {
b496df86	433	.initial_header_size = 128,
37784706 MF	434	.state = zynq_fpga_ops_state,
	435	.write_init = zynq_fpga_ops_write_init,
	436	.write = zynq_fpga_ops_write,
	437	.write_complete = zynq_fpga_ops_write_complete,
	438	};
	439
	440	static int zynq_fpga_probe(struct platform_device *pdev)
	441	{
	442	struct device *dev = &pdev->dev;
	443	struct zynq_fpga_priv *priv;
	444	struct resource *res;
	445	int err;
	446
	447	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	448	if (!priv)
	449	return -ENOMEM;
	450
37784706 MF	451	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	452	priv->io_base = devm_ioremap_resource(dev, res);
	453	if (IS_ERR(priv->io_base))
	454	return PTR_ERR(priv->io_base);
	455
	456	priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node,
	457	"syscon");
	458	if (IS_ERR(priv->slcr)) {
1930c286	459	dev_err(dev, "unable to get zynq-slcr regmap\n");
37784706 MF	460	return PTR_ERR(priv->slcr);
	461	}
	462
	463	init_completion(&priv->dma_done);
	464
	465	priv->irq = platform_get_irq(pdev, 0);
	466	if (priv->irq < 0) {
1930c286	467	dev_err(dev, "No IRQ available\n");
37784706 MF	468	return priv->irq;
	469	}
	470
37784706 MF	471	priv->clk = devm_clk_get(dev, "ref_clk");
37784706 MF	472	if (IS_ERR(priv->clk)) {
1930c286	473	dev_err(dev, "input clock not found\n");
37784706 MF	474	return PTR_ERR(priv->clk);
	475	}
	476
	477	err = clk_prepare_enable(priv->clk);
	478	if (err) {
1930c286	479	dev_err(dev, "unable to enable clock\n");
37784706 MF	480	return err;
	481	}
	482
	483	/* unlock the device */
	484	zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK);
	485
6b45e0f2	486	zynq_fpga_set_irq(priv, 0);
340c0c53 JG	487	zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
	488	err = devm_request_irq(dev, priv->irq, zynq_fpga_isr, 0, dev_name(dev),
	489	priv);
	490	if (err) {
	491	dev_err(dev, "unable to request IRQ\n");
	492	clk_disable_unprepare(priv->clk);
	493	return err;
	494	}
	495
37784706 MF	496	clk_disable(priv->clk);
	497
	498	err = fpga_mgr_register(dev, "Xilinx Zynq FPGA Manager",
	499	&zynq_fpga_ops, priv);
	500	if (err) {
1930c286	501	dev_err(dev, "unable to register FPGA manager\n");
6376931b	502	clk_unprepare(priv->clk);
37784706 MF	503	return err;
	504	}
	505
	506	return 0;
	507	}
	508
	509	static int zynq_fpga_remove(struct platform_device *pdev)
	510	{
	511	struct zynq_fpga_priv *priv;
28f98a12	512	struct fpga_manager *mgr;
37784706	513
28f98a12 MF	514	mgr = platform_get_drvdata(pdev);
28f98a12 MF	515	priv = mgr->priv;
37784706	516
28f98a12	517	fpga_mgr_unregister(&pdev->dev);
37784706	518
6376931b	519	clk_unprepare(priv->clk);
37784706 MF	520
	521	return 0;
	522	}
	523
	524	#ifdef CONFIG_OF
	525	static const struct of_device_id zynq_fpga_of_match[] = {
	526	{ .compatible = "xlnx,zynq-devcfg-1.0", },
	527	{},
	528	};
	529
	530	MODULE_DEVICE_TABLE(of, zynq_fpga_of_match);
	531	#endif
	532
	533	static struct platform_driver zynq_fpga_driver = {
	534	.probe = zynq_fpga_probe,
	535	.remove = zynq_fpga_remove,
	536	.driver = {
	537	.name = "zynq_fpga_manager",
	538	.of_match_table = of_match_ptr(zynq_fpga_of_match),
	539	},
	540	};
	541
	542	module_platform_driver(zynq_fpga_driver);
	543
	544	MODULE_AUTHOR("Moritz Fischer <moritz.fischer@ettus.com>");
	545	MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>");
	546	MODULE_DESCRIPTION("Xilinx Zynq FPGA Manager");
	547	MODULE_LICENSE("GPL v2");