[linux-2.6-block.git] / drivers / fpga / xilinx-pr-decoupler.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2017, National Instruments Corp.
 * Copyright (c) 2017, Xilinx Inc
 *
 * FPGA Bridge Driver for the Xilinx LogiCORE Partial Reconfiguration
 * Decoupler IP Core.
 */

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/fpga/fpga-bridge.h>

#define CTRL_CMD_DECOUPLE	BIT(0)
#define CTRL_CMD_COUPLE		0
#define CTRL_OFFSET		0

struct xlnx_config_data {
	const char *name;
};

struct xlnx_pr_decoupler_data {
	const struct xlnx_config_data *ipconfig;
	void __iomem *io_base;
	struct clk *clk;
};

static inline void xlnx_pr_decoupler_write(struct xlnx_pr_decoupler_data *d,
					   u32 offset, u32 val)
{
	writel(val, d->io_base + offset);
}

static inline u32 xlnx_pr_decouple_read(const struct xlnx_pr_decoupler_data *d,
					u32 offset)
{
	return readl(d->io_base + offset);
}

static int xlnx_pr_decoupler_enable_set(struct fpga_bridge *bridge, bool enable)
{
	int err;
	struct xlnx_pr_decoupler_data *priv = bridge->priv;

	err = clk_enable(priv->clk);
	if (err)
		return err;

	if (enable)
		xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_COUPLE);
	else
		xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_DECOUPLE);

	clk_disable(priv->clk);

	return 0;
}

static int xlnx_pr_decoupler_enable_show(struct fpga_bridge *bridge)
{
	const struct xlnx_pr_decoupler_data *priv = bridge->priv;
	u32 status;
	int err;

	err = clk_enable(priv->clk);
	if (err)
		return err;

	status = xlnx_pr_decouple_read(priv, CTRL_OFFSET);

	clk_disable(priv->clk);

	return !status;
}

static const struct fpga_bridge_ops xlnx_pr_decoupler_br_ops = {
	.enable_set = xlnx_pr_decoupler_enable_set,
	.enable_show = xlnx_pr_decoupler_enable_show,
};

static const struct xlnx_config_data decoupler_config = {
	.name = "Xilinx PR Decoupler",
};

static const struct xlnx_config_data shutdown_config = {
	.name = "Xilinx DFX AXI Shutdown Manager",
};

static const struct of_device_id xlnx_pr_decoupler_of_match[] = {
	{ .compatible = "xlnx,pr-decoupler-1.00", .data = &decoupler_config },
	{ .compatible = "xlnx,pr-decoupler", .data = &decoupler_config },
	{ .compatible = "xlnx,dfx-axi-shutdown-manager-1.00",
					.data = &shutdown_config },
	{ .compatible = "xlnx,dfx-axi-shutdown-manager",
					.data = &shutdown_config },
	{},
};
MODULE_DEVICE_TABLE(of, xlnx_pr_decoupler_of_match);

static int xlnx_pr_decoupler_probe(struct platform_device *pdev)
{
	struct xlnx_pr_decoupler_data *priv;
	struct fpga_bridge *br;
	int err;

	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->ipconfig = device_get_match_data(&pdev->dev);

	priv->io_base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(priv->io_base))
		return PTR_ERR(priv->io_base);

	priv->clk = devm_clk_get(&pdev->dev, "aclk");
	if (IS_ERR(priv->clk))
		return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk),
				     "input clock not found\n");

	err = clk_prepare_enable(priv->clk);
	if (err) {
		dev_err(&pdev->dev, "unable to enable clock\n");
		return err;
	}

	clk_disable(priv->clk);

	br = fpga_bridge_register(&pdev->dev, priv->ipconfig->name,
				  &xlnx_pr_decoupler_br_ops, priv);
	if (IS_ERR(br)) {
		err = PTR_ERR(br);
		dev_err(&pdev->dev, "unable to register %s",
			priv->ipconfig->name);
		goto err_clk;
	}

	platform_set_drvdata(pdev, br);

	return 0;

err_clk:
	clk_unprepare(priv->clk);

	return err;
}

static void xlnx_pr_decoupler_remove(struct platform_device *pdev)
{
	struct fpga_bridge *bridge = platform_get_drvdata(pdev);
	struct xlnx_pr_decoupler_data *p = bridge->priv;

	fpga_bridge_unregister(bridge);

	clk_unprepare(p->clk);
}

static struct platform_driver xlnx_pr_decoupler_driver = {
	.probe = xlnx_pr_decoupler_probe,
	.remove_new = xlnx_pr_decoupler_remove,
	.driver = {
		.name = "xlnx_pr_decoupler",
		.of_match_table = xlnx_pr_decoupler_of_match,
	},
};

module_platform_driver(xlnx_pr_decoupler_driver);

MODULE_DESCRIPTION("Xilinx Partial Reconfiguration Decoupler");
MODULE_AUTHOR("Moritz Fischer <mdf@kernel.org>");
MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
8e8e69d6	1	// SPDX-License-Identifier: GPL-2.0-only
7e961c12 MF	2	/*
7e961c12 MF	3	* Copyright (c) 2017, National Instruments Corp.
30a2ac9a	4	* Copyright (c) 2017, Xilinx Inc
7e961c12 MF	5	*
	6	* FPGA Bridge Driver for the Xilinx LogiCORE Partial Reconfiguration
	7	* Decoupler IP Core.
7e961c12 MF	8	*/
	9
	10	#include <linux/clk.h>
	11	#include <linux/io.h>
	12	#include <linux/kernel.h>
7e961c12	13	#include <linux/module.h>
4e807eb0 RH	14	#include <linux/of.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/property.h>
7e961c12 MF	17	#include <linux/fpga/fpga-bridge.h>
	18
	19	#define CTRL_CMD_DECOUPLE BIT(0)
	20	#define CTRL_CMD_COUPLE 0
	21	#define CTRL_OFFSET 0
	22
30a2ac9a NM	23	struct xlnx_config_data {
	24	const char *name;
	25	};
	26
7e961c12	27	struct xlnx_pr_decoupler_data {
30a2ac9a	28	const struct xlnx_config_data *ipconfig;
7e961c12 MF	29	void __iomem *io_base;
	30	struct clk *clk;
	31	};
	32
	33	static inline void xlnx_pr_decoupler_write(struct xlnx_pr_decoupler_data *d,
	34	u32 offset, u32 val)
	35	{
	36	writel(val, d->io_base + offset);
	37	}
	38
	39	static inline u32 xlnx_pr_decouple_read(const struct xlnx_pr_decoupler_data *d,
	40	u32 offset)
	41	{
	42	return readl(d->io_base + offset);
	43	}
	44
	45	static int xlnx_pr_decoupler_enable_set(struct fpga_bridge *bridge, bool enable)
	46	{
	47	int err;
	48	struct xlnx_pr_decoupler_data *priv = bridge->priv;
	49
	50	err = clk_enable(priv->clk);
	51	if (err)
	52	return err;
	53
	54	if (enable)
	55	xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_COUPLE);
	56	else
	57	xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_DECOUPLE);
	58
	59	clk_disable(priv->clk);
	60
	61	return 0;
	62	}
	63
	64	static int xlnx_pr_decoupler_enable_show(struct fpga_bridge *bridge)
	65	{
	66	const struct xlnx_pr_decoupler_data *priv = bridge->priv;
	67	u32 status;
	68	int err;
	69
	70	err = clk_enable(priv->clk);
	71	if (err)
	72	return err;
	73
d2b727cb	74	status = xlnx_pr_decouple_read(priv, CTRL_OFFSET);
7e961c12 MF	75
	76	clk_disable(priv->clk);
	77
	78	return !status;
	79	}
	80
d8d9d936	81	static const struct fpga_bridge_ops xlnx_pr_decoupler_br_ops = {
7e961c12 MF	82	.enable_set = xlnx_pr_decoupler_enable_set,
	83	.enable_show = xlnx_pr_decoupler_enable_show,
	84	};
	85
30a2ac9a NM	86	static const struct xlnx_config_data decoupler_config = {
	87	.name = "Xilinx PR Decoupler",
	88	};
	89
	90	static const struct xlnx_config_data shutdown_config = {
	91	.name = "Xilinx DFX AXI Shutdown Manager",
	92	};
	93
7e961c12	94	static const struct of_device_id xlnx_pr_decoupler_of_match[] = {
30a2ac9a NM	95	{ .compatible = "xlnx,pr-decoupler-1.00", .data = &decoupler_config },
	96	{ .compatible = "xlnx,pr-decoupler", .data = &decoupler_config },
	97	{ .compatible = "xlnx,dfx-axi-shutdown-manager-1.00",
	98	.data = &shutdown_config },
	99	{ .compatible = "xlnx,dfx-axi-shutdown-manager",
	100	.data = &shutdown_config },
7e961c12 MF	101	{},
	102	};
	103	MODULE_DEVICE_TABLE(of, xlnx_pr_decoupler_of_match);
	104
	105	static int xlnx_pr_decoupler_probe(struct platform_device *pdev)
	106	{
	107	struct xlnx_pr_decoupler_data *priv;
371cd1b1	108	struct fpga_bridge *br;
7e961c12	109	int err;
7e961c12 MF	110
	111	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	112	if (!priv)
	113	return -ENOMEM;
	114
4e807eb0	115	priv->ipconfig = device_get_match_data(&pdev->dev);
30a2ac9a	116
ebe00825	117	priv->io_base = devm_platform_ioremap_resource(pdev, 0);
7e961c12 MF	118	if (IS_ERR(priv->io_base))
	119	return PTR_ERR(priv->io_base);
	120
	121	priv->clk = devm_clk_get(&pdev->dev, "aclk");
b5c6ecfd MS	122	if (IS_ERR(priv->clk))
	123	return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk),
	124	"input clock not found\n");
7e961c12 MF	125
	126	err = clk_prepare_enable(priv->clk);
	127	if (err) {
	128	dev_err(&pdev->dev, "unable to enable clock\n");
	129	return err;
	130	}
	131
	132	clk_disable(priv->clk);
	133
0d70af3c RW	134	br = fpga_bridge_register(&pdev->dev, priv->ipconfig->name,
	135	&xlnx_pr_decoupler_br_ops, priv);
	136	if (IS_ERR(br)) {
	137	err = PTR_ERR(br);
30a2ac9a NM	138	dev_err(&pdev->dev, "unable to register %s",
30a2ac9a NM	139	priv->ipconfig->name);
371cd1b1	140	goto err_clk;
7e961c12 MF	141	}
7e961c12 MF	142
0d70af3c RW	143	platform_set_drvdata(pdev, br);
0d70af3c RW	144
7e961c12	145	return 0;
371cd1b1 AT	146
	147	err_clk:
	148	clk_unprepare(priv->clk);
	149
	150	return err;
7e961c12 MF	151	}
7e961c12 MF	152
a584df30	153	static void xlnx_pr_decoupler_remove(struct platform_device *pdev)
7e961c12 MF	154	{
	155	struct fpga_bridge *bridge = platform_get_drvdata(pdev);
	156	struct xlnx_pr_decoupler_data *p = bridge->priv;
	157
371cd1b1	158	fpga_bridge_unregister(bridge);
7e961c12 MF	159
7e961c12 MF	160	clk_unprepare(p->clk);
7e961c12 MF	161	}
	162
	163	static struct platform_driver xlnx_pr_decoupler_driver = {
	164	.probe = xlnx_pr_decoupler_probe,
a584df30	165	.remove_new = xlnx_pr_decoupler_remove,
7e961c12 MF	166	.driver = {
7e961c12 MF	167	.name = "xlnx_pr_decoupler",
4e807eb0	168	.of_match_table = xlnx_pr_decoupler_of_match,
7e961c12 MF	169	},
	170	};
	171
	172	module_platform_driver(xlnx_pr_decoupler_driver);
	173
	174	MODULE_DESCRIPTION("Xilinx Partial Reconfiguration Decoupler");
	175	MODULE_AUTHOR("Moritz Fischer <mdf@kernel.org>");
	176	MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>");
	177	MODULE_LICENSE("GPL v2");