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e7eef1d7 AT |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * FPGA Manager Driver for Intel Stratix10 SoC | |
4 | * | |
5 | * Copyright (C) 2018 Intel Corporation | |
6 | */ | |
7 | #include <linux/completion.h> | |
8 | #include <linux/fpga/fpga-mgr.h> | |
9 | #include <linux/firmware/intel/stratix10-svc-client.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/of.h> | |
12 | #include <linux/of_platform.h> | |
13 | ||
14 | /* | |
15 | * FPGA programming requires a higher level of privilege (EL3), per the SoC | |
16 | * design. | |
17 | */ | |
18 | #define NUM_SVC_BUFS 4 | |
19 | #define SVC_BUF_SIZE SZ_512K | |
20 | ||
21 | /* Indicates buffer is in use if set */ | |
22 | #define SVC_BUF_LOCK 0 | |
23 | ||
24 | #define S10_BUFFER_TIMEOUT (msecs_to_jiffies(SVC_RECONFIG_BUFFER_TIMEOUT_MS)) | |
25 | #define S10_RECONFIG_TIMEOUT (msecs_to_jiffies(SVC_RECONFIG_REQUEST_TIMEOUT_MS)) | |
26 | ||
27 | /* | |
28 | * struct s10_svc_buf | |
29 | * buf: virtual address of buf provided by service layer | |
30 | * lock: locked if buffer is in use | |
31 | */ | |
32 | struct s10_svc_buf { | |
33 | char *buf; | |
34 | unsigned long lock; | |
35 | }; | |
36 | ||
37 | struct s10_priv { | |
38 | struct stratix10_svc_chan *chan; | |
39 | struct stratix10_svc_client client; | |
40 | struct completion status_return_completion; | |
41 | struct s10_svc_buf svc_bufs[NUM_SVC_BUFS]; | |
42 | unsigned long status; | |
43 | }; | |
44 | ||
45 | static int s10_svc_send_msg(struct s10_priv *priv, | |
46 | enum stratix10_svc_command_code command, | |
47 | void *payload, u32 payload_length) | |
48 | { | |
49 | struct stratix10_svc_chan *chan = priv->chan; | |
50 | struct device *dev = priv->client.dev; | |
51 | struct stratix10_svc_client_msg msg; | |
52 | int ret; | |
53 | ||
54 | dev_dbg(dev, "%s cmd=%d payload=%p length=%d\n", | |
55 | __func__, command, payload, payload_length); | |
56 | ||
57 | msg.command = command; | |
58 | msg.payload = payload; | |
59 | msg.payload_length = payload_length; | |
60 | ||
61 | ret = stratix10_svc_send(chan, &msg); | |
62 | dev_dbg(dev, "stratix10_svc_send returned status %d\n", ret); | |
63 | ||
64 | return ret; | |
65 | } | |
66 | ||
67 | /* | |
68 | * Free buffers allocated from the service layer's pool that are not in use. | |
69 | * Return true when all buffers are freed. | |
70 | */ | |
71 | static bool s10_free_buffers(struct fpga_manager *mgr) | |
72 | { | |
73 | struct s10_priv *priv = mgr->priv; | |
74 | uint num_free = 0; | |
75 | uint i; | |
76 | ||
77 | for (i = 0; i < NUM_SVC_BUFS; i++) { | |
78 | if (!priv->svc_bufs[i].buf) { | |
79 | num_free++; | |
80 | continue; | |
81 | } | |
82 | ||
83 | if (!test_and_set_bit_lock(SVC_BUF_LOCK, | |
84 | &priv->svc_bufs[i].lock)) { | |
85 | stratix10_svc_free_memory(priv->chan, | |
86 | priv->svc_bufs[i].buf); | |
87 | priv->svc_bufs[i].buf = NULL; | |
88 | num_free++; | |
89 | } | |
90 | } | |
91 | ||
92 | return num_free == NUM_SVC_BUFS; | |
93 | } | |
94 | ||
95 | /* | |
96 | * Returns count of how many buffers are not in use. | |
97 | */ | |
98 | static uint s10_free_buffer_count(struct fpga_manager *mgr) | |
99 | { | |
100 | struct s10_priv *priv = mgr->priv; | |
101 | uint num_free = 0; | |
102 | uint i; | |
103 | ||
104 | for (i = 0; i < NUM_SVC_BUFS; i++) | |
105 | if (!priv->svc_bufs[i].buf) | |
106 | num_free++; | |
107 | ||
108 | return num_free; | |
109 | } | |
110 | ||
111 | /* | |
112 | * s10_unlock_bufs | |
113 | * Given the returned buffer address, match that address to our buffer struct | |
114 | * and unlock that buffer. This marks it as available to be refilled and sent | |
115 | * (or freed). | |
116 | * priv: private data | |
117 | * kaddr: kernel address of buffer that was returned from service layer | |
118 | */ | |
119 | static void s10_unlock_bufs(struct s10_priv *priv, void *kaddr) | |
120 | { | |
121 | uint i; | |
122 | ||
123 | if (!kaddr) | |
124 | return; | |
125 | ||
126 | for (i = 0; i < NUM_SVC_BUFS; i++) | |
127 | if (priv->svc_bufs[i].buf == kaddr) { | |
128 | clear_bit_unlock(SVC_BUF_LOCK, | |
129 | &priv->svc_bufs[i].lock); | |
130 | return; | |
131 | } | |
132 | ||
133 | WARN(1, "Unknown buffer returned from service layer %p\n", kaddr); | |
134 | } | |
135 | ||
136 | /* | |
137 | * s10_receive_callback - callback for service layer to use to provide client | |
138 | * (this driver) messages received through the mailbox. | |
139 | * client: service layer client struct | |
140 | * data: message from service layer | |
141 | */ | |
142 | static void s10_receive_callback(struct stratix10_svc_client *client, | |
143 | struct stratix10_svc_cb_data *data) | |
144 | { | |
145 | struct s10_priv *priv = client->priv; | |
146 | u32 status; | |
147 | int i; | |
148 | ||
149 | WARN_ONCE(!data, "%s: stratix10_svc_rc_data = NULL", __func__); | |
150 | ||
151 | status = data->status; | |
152 | ||
153 | /* | |
154 | * Here we set status bits as we receive them. Elsewhere, we always use | |
155 | * test_and_clear_bit() to check status in priv->status | |
156 | */ | |
7536ad8d | 157 | for (i = 0; i <= SVC_STATUS_ERROR; i++) |
e7eef1d7 AT |
158 | if (status & (1 << i)) |
159 | set_bit(i, &priv->status); | |
160 | ||
7536ad8d | 161 | if (status & BIT(SVC_STATUS_BUFFER_DONE)) { |
e7eef1d7 AT |
162 | s10_unlock_bufs(priv, data->kaddr1); |
163 | s10_unlock_bufs(priv, data->kaddr2); | |
164 | s10_unlock_bufs(priv, data->kaddr3); | |
165 | } | |
166 | ||
167 | complete(&priv->status_return_completion); | |
168 | } | |
169 | ||
170 | /* | |
171 | * s10_ops_write_init - prepare for FPGA reconfiguration by requesting | |
172 | * partial reconfig and allocating buffers from the service layer. | |
173 | */ | |
174 | static int s10_ops_write_init(struct fpga_manager *mgr, | |
175 | struct fpga_image_info *info, | |
176 | const char *buf, size_t count) | |
177 | { | |
178 | struct s10_priv *priv = mgr->priv; | |
179 | struct device *dev = priv->client.dev; | |
180 | struct stratix10_svc_command_config_type ctype; | |
181 | char *kbuf; | |
182 | uint i; | |
183 | int ret; | |
184 | ||
185 | ctype.flags = 0; | |
186 | if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { | |
187 | dev_dbg(dev, "Requesting partial reconfiguration.\n"); | |
188 | ctype.flags |= BIT(COMMAND_RECONFIG_FLAG_PARTIAL); | |
189 | } else { | |
190 | dev_dbg(dev, "Requesting full reconfiguration.\n"); | |
191 | } | |
192 | ||
193 | reinit_completion(&priv->status_return_completion); | |
194 | ret = s10_svc_send_msg(priv, COMMAND_RECONFIG, | |
195 | &ctype, sizeof(ctype)); | |
196 | if (ret < 0) | |
197 | goto init_done; | |
198 | ||
199 | ret = wait_for_completion_interruptible_timeout( | |
200 | &priv->status_return_completion, S10_RECONFIG_TIMEOUT); | |
201 | if (!ret) { | |
202 | dev_err(dev, "timeout waiting for RECONFIG_REQUEST\n"); | |
203 | ret = -ETIMEDOUT; | |
204 | goto init_done; | |
205 | } | |
206 | if (ret < 0) { | |
207 | dev_err(dev, "error (%d) waiting for RECONFIG_REQUEST\n", ret); | |
208 | goto init_done; | |
209 | } | |
210 | ||
211 | ret = 0; | |
7536ad8d | 212 | if (!test_and_clear_bit(SVC_STATUS_OK, &priv->status)) { |
e7eef1d7 AT |
213 | ret = -ETIMEDOUT; |
214 | goto init_done; | |
215 | } | |
216 | ||
217 | /* Allocate buffers from the service layer's pool. */ | |
218 | for (i = 0; i < NUM_SVC_BUFS; i++) { | |
219 | kbuf = stratix10_svc_allocate_memory(priv->chan, SVC_BUF_SIZE); | |
220 | if (!kbuf) { | |
221 | s10_free_buffers(mgr); | |
222 | ret = -ENOMEM; | |
223 | goto init_done; | |
224 | } | |
225 | ||
226 | priv->svc_bufs[i].buf = kbuf; | |
227 | priv->svc_bufs[i].lock = 0; | |
228 | } | |
229 | ||
230 | init_done: | |
231 | stratix10_svc_done(priv->chan); | |
232 | return ret; | |
233 | } | |
234 | ||
235 | /* | |
236 | * s10_send_buf - send a buffer to the service layer queue | |
237 | * mgr: fpga manager struct | |
238 | * buf: fpga image buffer | |
239 | * count: size of buf in bytes | |
240 | * Returns # of bytes transferred or -ENOBUFS if the all the buffers are in use | |
241 | * or if the service queue is full. Never returns 0. | |
242 | */ | |
243 | static int s10_send_buf(struct fpga_manager *mgr, const char *buf, size_t count) | |
244 | { | |
245 | struct s10_priv *priv = mgr->priv; | |
246 | struct device *dev = priv->client.dev; | |
247 | void *svc_buf; | |
248 | size_t xfer_sz; | |
249 | int ret; | |
250 | uint i; | |
251 | ||
252 | /* get/lock a buffer that that's not being used */ | |
253 | for (i = 0; i < NUM_SVC_BUFS; i++) | |
254 | if (!test_and_set_bit_lock(SVC_BUF_LOCK, | |
255 | &priv->svc_bufs[i].lock)) | |
256 | break; | |
257 | ||
258 | if (i == NUM_SVC_BUFS) | |
259 | return -ENOBUFS; | |
260 | ||
261 | xfer_sz = count < SVC_BUF_SIZE ? count : SVC_BUF_SIZE; | |
262 | ||
263 | svc_buf = priv->svc_bufs[i].buf; | |
264 | memcpy(svc_buf, buf, xfer_sz); | |
265 | ret = s10_svc_send_msg(priv, COMMAND_RECONFIG_DATA_SUBMIT, | |
266 | svc_buf, xfer_sz); | |
267 | if (ret < 0) { | |
268 | dev_err(dev, | |
269 | "Error while sending data to service layer (%d)", ret); | |
270 | clear_bit_unlock(SVC_BUF_LOCK, &priv->svc_bufs[i].lock); | |
271 | return ret; | |
272 | } | |
273 | ||
274 | return xfer_sz; | |
275 | } | |
276 | ||
277 | /* | |
278 | * Send a FPGA image to privileged layers to write to the FPGA. When done | |
279 | * sending, free all service layer buffers we allocated in write_init. | |
280 | */ | |
281 | static int s10_ops_write(struct fpga_manager *mgr, const char *buf, | |
282 | size_t count) | |
283 | { | |
284 | struct s10_priv *priv = mgr->priv; | |
285 | struct device *dev = priv->client.dev; | |
286 | long wait_status; | |
287 | int sent = 0; | |
288 | int ret = 0; | |
289 | ||
290 | /* | |
291 | * Loop waiting for buffers to be returned. When a buffer is returned, | |
292 | * reuse it to send more data or free if if all data has been sent. | |
293 | */ | |
294 | while (count > 0 || s10_free_buffer_count(mgr) != NUM_SVC_BUFS) { | |
295 | reinit_completion(&priv->status_return_completion); | |
296 | ||
297 | if (count > 0) { | |
298 | sent = s10_send_buf(mgr, buf, count); | |
299 | if (sent < 0) | |
300 | continue; | |
301 | ||
302 | count -= sent; | |
303 | buf += sent; | |
304 | } else { | |
305 | if (s10_free_buffers(mgr)) | |
306 | return 0; | |
307 | ||
308 | ret = s10_svc_send_msg( | |
309 | priv, COMMAND_RECONFIG_DATA_CLAIM, | |
310 | NULL, 0); | |
311 | if (ret < 0) | |
312 | break; | |
313 | } | |
314 | ||
315 | /* | |
316 | * If callback hasn't already happened, wait for buffers to be | |
317 | * returned from service layer | |
318 | */ | |
319 | wait_status = 1; /* not timed out */ | |
320 | if (!priv->status) | |
321 | wait_status = wait_for_completion_interruptible_timeout( | |
322 | &priv->status_return_completion, | |
323 | S10_BUFFER_TIMEOUT); | |
324 | ||
7536ad8d RG |
325 | if (test_and_clear_bit(SVC_STATUS_BUFFER_DONE, &priv->status) || |
326 | test_and_clear_bit(SVC_STATUS_BUFFER_SUBMITTED, | |
e7eef1d7 AT |
327 | &priv->status)) { |
328 | ret = 0; | |
329 | continue; | |
330 | } | |
331 | ||
7536ad8d RG |
332 | if (test_and_clear_bit(SVC_STATUS_ERROR, &priv->status)) { |
333 | dev_err(dev, "ERROR - giving up - SVC_STATUS_ERROR\n"); | |
e7eef1d7 AT |
334 | ret = -EFAULT; |
335 | break; | |
336 | } | |
337 | ||
338 | if (!wait_status) { | |
339 | dev_err(dev, "timeout waiting for svc layer buffers\n"); | |
340 | ret = -ETIMEDOUT; | |
341 | break; | |
342 | } | |
343 | if (wait_status < 0) { | |
344 | ret = wait_status; | |
345 | dev_err(dev, | |
346 | "error (%d) waiting for svc layer buffers\n", | |
347 | ret); | |
348 | break; | |
349 | } | |
350 | } | |
351 | ||
352 | if (!s10_free_buffers(mgr)) | |
353 | dev_err(dev, "%s not all buffers were freed\n", __func__); | |
354 | ||
355 | return ret; | |
356 | } | |
357 | ||
358 | static int s10_ops_write_complete(struct fpga_manager *mgr, | |
359 | struct fpga_image_info *info) | |
360 | { | |
361 | struct s10_priv *priv = mgr->priv; | |
362 | struct device *dev = priv->client.dev; | |
363 | unsigned long timeout; | |
364 | int ret; | |
365 | ||
366 | timeout = usecs_to_jiffies(info->config_complete_timeout_us); | |
367 | ||
368 | do { | |
369 | reinit_completion(&priv->status_return_completion); | |
370 | ||
371 | ret = s10_svc_send_msg(priv, COMMAND_RECONFIG_STATUS, NULL, 0); | |
372 | if (ret < 0) | |
373 | break; | |
374 | ||
375 | ret = wait_for_completion_interruptible_timeout( | |
376 | &priv->status_return_completion, timeout); | |
377 | if (!ret) { | |
378 | dev_err(dev, | |
379 | "timeout waiting for RECONFIG_COMPLETED\n"); | |
380 | ret = -ETIMEDOUT; | |
381 | break; | |
382 | } | |
383 | if (ret < 0) { | |
384 | dev_err(dev, | |
385 | "error (%d) waiting for RECONFIG_COMPLETED\n", | |
386 | ret); | |
387 | break; | |
388 | } | |
389 | /* Not error or timeout, so ret is # of jiffies until timeout */ | |
390 | timeout = ret; | |
391 | ret = 0; | |
392 | ||
7536ad8d | 393 | if (test_and_clear_bit(SVC_STATUS_COMPLETED, &priv->status)) |
e7eef1d7 AT |
394 | break; |
395 | ||
7536ad8d RG |
396 | if (test_and_clear_bit(SVC_STATUS_ERROR, &priv->status)) { |
397 | dev_err(dev, "ERROR - giving up - SVC_STATUS_ERROR\n"); | |
e7eef1d7 AT |
398 | ret = -EFAULT; |
399 | break; | |
400 | } | |
401 | } while (1); | |
402 | ||
403 | stratix10_svc_done(priv->chan); | |
404 | ||
405 | return ret; | |
406 | } | |
407 | ||
408 | static enum fpga_mgr_states s10_ops_state(struct fpga_manager *mgr) | |
409 | { | |
410 | return FPGA_MGR_STATE_UNKNOWN; | |
411 | } | |
412 | ||
413 | static const struct fpga_manager_ops s10_ops = { | |
414 | .state = s10_ops_state, | |
415 | .write_init = s10_ops_write_init, | |
416 | .write = s10_ops_write, | |
417 | .write_complete = s10_ops_write_complete, | |
418 | }; | |
419 | ||
420 | static int s10_probe(struct platform_device *pdev) | |
421 | { | |
422 | struct device *dev = &pdev->dev; | |
423 | struct s10_priv *priv; | |
424 | struct fpga_manager *mgr; | |
425 | int ret; | |
426 | ||
427 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
428 | if (!priv) | |
429 | return -ENOMEM; | |
430 | ||
431 | priv->client.dev = dev; | |
432 | priv->client.receive_cb = s10_receive_callback; | |
433 | priv->client.priv = priv; | |
434 | ||
435 | priv->chan = stratix10_svc_request_channel_byname(&priv->client, | |
436 | SVC_CLIENT_FPGA); | |
437 | if (IS_ERR(priv->chan)) { | |
438 | dev_err(dev, "couldn't get service channel (%s)\n", | |
439 | SVC_CLIENT_FPGA); | |
440 | return PTR_ERR(priv->chan); | |
441 | } | |
442 | ||
443 | init_completion(&priv->status_return_completion); | |
444 | ||
445 | mgr = fpga_mgr_create(dev, "Stratix10 SOC FPGA Manager", | |
446 | &s10_ops, priv); | |
447 | if (!mgr) { | |
448 | dev_err(dev, "unable to create FPGA manager\n"); | |
449 | ret = -ENOMEM; | |
450 | goto probe_err; | |
451 | } | |
452 | ||
453 | ret = fpga_mgr_register(mgr); | |
454 | if (ret) { | |
455 | dev_err(dev, "unable to register FPGA manager\n"); | |
456 | fpga_mgr_free(mgr); | |
457 | goto probe_err; | |
458 | } | |
459 | ||
460 | platform_set_drvdata(pdev, mgr); | |
461 | return ret; | |
462 | ||
463 | probe_err: | |
464 | stratix10_svc_free_channel(priv->chan); | |
465 | return ret; | |
466 | } | |
467 | ||
468 | static int s10_remove(struct platform_device *pdev) | |
469 | { | |
470 | struct fpga_manager *mgr = platform_get_drvdata(pdev); | |
471 | struct s10_priv *priv = mgr->priv; | |
472 | ||
473 | fpga_mgr_unregister(mgr); | |
474 | stratix10_svc_free_channel(priv->chan); | |
475 | ||
476 | return 0; | |
477 | } | |
478 | ||
479 | static const struct of_device_id s10_of_match[] = { | |
d299253c RG |
480 | {.compatible = "intel,stratix10-soc-fpga-mgr"}, |
481 | {.compatible = "intel,agilex-soc-fpga-mgr"}, | |
e7eef1d7 AT |
482 | {}, |
483 | }; | |
484 | ||
485 | MODULE_DEVICE_TABLE(of, s10_of_match); | |
486 | ||
487 | static struct platform_driver s10_driver = { | |
488 | .probe = s10_probe, | |
489 | .remove = s10_remove, | |
490 | .driver = { | |
491 | .name = "Stratix10 SoC FPGA manager", | |
492 | .of_match_table = of_match_ptr(s10_of_match), | |
493 | }, | |
494 | }; | |
495 | ||
496 | static int __init s10_init(void) | |
497 | { | |
498 | struct device_node *fw_np; | |
499 | struct device_node *np; | |
500 | int ret; | |
501 | ||
502 | fw_np = of_find_node_by_name(NULL, "svc"); | |
503 | if (!fw_np) | |
504 | return -ENODEV; | |
505 | ||
f5dd8732 | 506 | of_node_get(fw_np); |
e7eef1d7 | 507 | np = of_find_matching_node(fw_np, s10_of_match); |
f5dd8732 WY |
508 | if (!np) { |
509 | of_node_put(fw_np); | |
e7eef1d7 | 510 | return -ENODEV; |
f5dd8732 | 511 | } |
e7eef1d7 AT |
512 | |
513 | of_node_put(np); | |
514 | ret = of_platform_populate(fw_np, s10_of_match, NULL, NULL); | |
f5dd8732 | 515 | of_node_put(fw_np); |
e7eef1d7 AT |
516 | if (ret) |
517 | return ret; | |
518 | ||
519 | return platform_driver_register(&s10_driver); | |
520 | } | |
521 | ||
522 | static void __exit s10_exit(void) | |
523 | { | |
524 | return platform_driver_unregister(&s10_driver); | |
525 | } | |
526 | ||
527 | module_init(s10_init); | |
528 | module_exit(s10_exit); | |
529 | ||
530 | MODULE_AUTHOR("Alan Tull <atull@kernel.org>"); | |
531 | MODULE_DESCRIPTION("Intel Stratix 10 SOC FPGA Manager"); | |
532 | MODULE_LICENSE("GPL v2"); |