Commit | Line | Data |
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0fa20cdf AT |
1 | /* |
2 | * FPGA Region - Device Tree support for FPGA programming under Linux | |
3 | * | |
4 | * Copyright (C) 2013-2016 Altera Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #include <linux/fpga/fpga-bridge.h> | |
20 | #include <linux/fpga/fpga-mgr.h> | |
21 | #include <linux/idr.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/list.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/of_platform.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/spinlock.h> | |
28 | ||
29 | /** | |
30 | * struct fpga_region - FPGA Region structure | |
31 | * @dev: FPGA Region device | |
32 | * @mutex: enforces exclusive reference to region | |
33 | * @bridge_list: list of FPGA bridges specified in region | |
34 | * @info: fpga image specific information | |
35 | */ | |
36 | struct fpga_region { | |
37 | struct device dev; | |
38 | struct mutex mutex; /* for exclusive reference to region */ | |
39 | struct list_head bridge_list; | |
40 | struct fpga_image_info *info; | |
41 | }; | |
42 | ||
43 | #define to_fpga_region(d) container_of(d, struct fpga_region, dev) | |
44 | ||
45 | static DEFINE_IDA(fpga_region_ida); | |
46 | static struct class *fpga_region_class; | |
47 | ||
48 | static const struct of_device_id fpga_region_of_match[] = { | |
49 | { .compatible = "fpga-region", }, | |
50 | {}, | |
51 | }; | |
52 | MODULE_DEVICE_TABLE(of, fpga_region_of_match); | |
53 | ||
54 | static int fpga_region_of_node_match(struct device *dev, const void *data) | |
55 | { | |
56 | return dev->of_node == data; | |
57 | } | |
58 | ||
59 | /** | |
60 | * fpga_region_find - find FPGA region | |
61 | * @np: device node of FPGA Region | |
62 | * Caller will need to put_device(®ion->dev) when done. | |
63 | * Returns FPGA Region struct or NULL | |
64 | */ | |
65 | static struct fpga_region *fpga_region_find(struct device_node *np) | |
66 | { | |
67 | struct device *dev; | |
68 | ||
69 | dev = class_find_device(fpga_region_class, NULL, np, | |
70 | fpga_region_of_node_match); | |
71 | if (!dev) | |
72 | return NULL; | |
73 | ||
74 | return to_fpga_region(dev); | |
75 | } | |
76 | ||
77 | /** | |
78 | * fpga_region_get - get an exclusive reference to a fpga region | |
79 | * @region: FPGA Region struct | |
80 | * | |
81 | * Caller should call fpga_region_put() when done with region. | |
82 | * | |
83 | * Return fpga_region struct if successful. | |
84 | * Return -EBUSY if someone already has a reference to the region. | |
85 | * Return -ENODEV if @np is not a FPGA Region. | |
86 | */ | |
87 | static struct fpga_region *fpga_region_get(struct fpga_region *region) | |
88 | { | |
89 | struct device *dev = ®ion->dev; | |
90 | ||
91 | if (!mutex_trylock(®ion->mutex)) { | |
92 | dev_dbg(dev, "%s: FPGA Region already in use\n", __func__); | |
93 | return ERR_PTR(-EBUSY); | |
94 | } | |
95 | ||
96 | get_device(dev); | |
0fa20cdf | 97 | if (!try_module_get(dev->parent->driver->owner)) { |
0fa20cdf AT |
98 | put_device(dev); |
99 | mutex_unlock(®ion->mutex); | |
100 | return ERR_PTR(-ENODEV); | |
101 | } | |
102 | ||
c3d971ad | 103 | dev_dbg(dev, "get\n"); |
0fa20cdf AT |
104 | |
105 | return region; | |
106 | } | |
107 | ||
108 | /** | |
109 | * fpga_region_put - release a reference to a region | |
110 | * | |
111 | * @region: FPGA region | |
112 | */ | |
113 | static void fpga_region_put(struct fpga_region *region) | |
114 | { | |
115 | struct device *dev = ®ion->dev; | |
116 | ||
c3d971ad | 117 | dev_dbg(dev, "put\n"); |
0fa20cdf AT |
118 | |
119 | module_put(dev->parent->driver->owner); | |
0fa20cdf AT |
120 | put_device(dev); |
121 | mutex_unlock(®ion->mutex); | |
122 | } | |
123 | ||
124 | /** | |
ebf877a5 | 125 | * fpga_region_get_manager - get reference for FPGA manager |
0fa20cdf AT |
126 | * @region: FPGA region |
127 | * | |
128 | * Get FPGA Manager from "fpga-mgr" property or from ancestor region. | |
129 | * | |
130 | * Caller should call fpga_mgr_put() when done with manager. | |
131 | * | |
132 | * Return: fpga manager struct or IS_ERR() condition containing error code. | |
133 | */ | |
134 | static struct fpga_manager *fpga_region_get_manager(struct fpga_region *region) | |
135 | { | |
136 | struct device *dev = ®ion->dev; | |
137 | struct device_node *np = dev->of_node; | |
138 | struct device_node *mgr_node; | |
139 | struct fpga_manager *mgr; | |
140 | ||
141 | of_node_get(np); | |
142 | while (np) { | |
143 | if (of_device_is_compatible(np, "fpga-region")) { | |
144 | mgr_node = of_parse_phandle(np, "fpga-mgr", 0); | |
145 | if (mgr_node) { | |
146 | mgr = of_fpga_mgr_get(mgr_node); | |
147 | of_node_put(np); | |
148 | return mgr; | |
149 | } | |
150 | } | |
151 | np = of_get_next_parent(np); | |
152 | } | |
153 | of_node_put(np); | |
154 | ||
155 | return ERR_PTR(-EINVAL); | |
156 | } | |
157 | ||
158 | /** | |
159 | * fpga_region_get_bridges - create a list of bridges | |
160 | * @region: FPGA region | |
161 | * @overlay: device node of the overlay | |
162 | * | |
163 | * Create a list of bridges including the parent bridge and the bridges | |
164 | * specified by "fpga-bridges" property. Note that the | |
165 | * fpga_bridges_enable/disable/put functions are all fine with an empty list | |
166 | * if that happens. | |
167 | * | |
168 | * Caller should call fpga_bridges_put(®ion->bridge_list) when | |
169 | * done with the bridges. | |
170 | * | |
171 | * Return 0 for success (even if there are no bridges specified) | |
172 | * or -EBUSY if any of the bridges are in use. | |
173 | */ | |
174 | static int fpga_region_get_bridges(struct fpga_region *region, | |
175 | struct device_node *overlay) | |
176 | { | |
177 | struct device *dev = ®ion->dev; | |
178 | struct device_node *region_np = dev->of_node; | |
179 | struct device_node *br, *np, *parent_br = NULL; | |
180 | int i, ret; | |
181 | ||
182 | /* If parent is a bridge, add to list */ | |
9c1c4b27 AT |
183 | ret = of_fpga_bridge_get_to_list(region_np->parent, region->info, |
184 | ®ion->bridge_list); | |
185 | ||
186 | /* -EBUSY means parent is a bridge that is under use. Give up. */ | |
0fa20cdf AT |
187 | if (ret == -EBUSY) |
188 | return ret; | |
189 | ||
9c1c4b27 | 190 | /* Zero return code means parent was a bridge and was added to list. */ |
0fa20cdf AT |
191 | if (!ret) |
192 | parent_br = region_np->parent; | |
193 | ||
194 | /* If overlay has a list of bridges, use it. */ | |
195 | if (of_parse_phandle(overlay, "fpga-bridges", 0)) | |
196 | np = overlay; | |
197 | else | |
198 | np = region_np; | |
199 | ||
200 | for (i = 0; ; i++) { | |
201 | br = of_parse_phandle(np, "fpga-bridges", i); | |
202 | if (!br) | |
203 | break; | |
204 | ||
205 | /* If parent bridge is in list, skip it. */ | |
206 | if (br == parent_br) | |
207 | continue; | |
208 | ||
209 | /* If node is a bridge, get it and add to list */ | |
9c1c4b27 AT |
210 | ret = of_fpga_bridge_get_to_list(br, region->info, |
211 | ®ion->bridge_list); | |
0fa20cdf AT |
212 | |
213 | /* If any of the bridges are in use, give up */ | |
214 | if (ret == -EBUSY) { | |
215 | fpga_bridges_put(®ion->bridge_list); | |
216 | return -EBUSY; | |
217 | } | |
218 | } | |
219 | ||
220 | return 0; | |
221 | } | |
222 | ||
223 | /** | |
224 | * fpga_region_program_fpga - program FPGA | |
225 | * @region: FPGA region | |
0fa20cdf | 226 | * @overlay: device node of the overlay |
5cf0c7f6 | 227 | * Program an FPGA using information in the region's fpga image info. |
0fa20cdf AT |
228 | * Return 0 for success or negative error code. |
229 | */ | |
230 | static int fpga_region_program_fpga(struct fpga_region *region, | |
0fa20cdf AT |
231 | struct device_node *overlay) |
232 | { | |
ebf877a5 | 233 | struct device *dev = ®ion->dev; |
0fa20cdf AT |
234 | struct fpga_manager *mgr; |
235 | int ret; | |
236 | ||
237 | region = fpga_region_get(region); | |
238 | if (IS_ERR(region)) { | |
c3d971ad | 239 | dev_err(dev, "failed to get FPGA region\n"); |
0fa20cdf AT |
240 | return PTR_ERR(region); |
241 | } | |
242 | ||
243 | mgr = fpga_region_get_manager(region); | |
244 | if (IS_ERR(mgr)) { | |
c3d971ad | 245 | dev_err(dev, "failed to get FPGA manager\n"); |
e73bbf64 TK |
246 | ret = PTR_ERR(mgr); |
247 | goto err_put_region; | |
0fa20cdf AT |
248 | } |
249 | ||
ebf877a5 AT |
250 | ret = fpga_mgr_lock(mgr); |
251 | if (ret) { | |
252 | dev_err(dev, "FPGA manager is busy\n"); | |
253 | goto err_put_mgr; | |
254 | } | |
255 | ||
0fa20cdf AT |
256 | ret = fpga_region_get_bridges(region, overlay); |
257 | if (ret) { | |
c3d971ad | 258 | dev_err(dev, "failed to get FPGA bridges\n"); |
ebf877a5 | 259 | goto err_unlock_mgr; |
0fa20cdf AT |
260 | } |
261 | ||
262 | ret = fpga_bridges_disable(®ion->bridge_list); | |
263 | if (ret) { | |
c3d971ad | 264 | dev_err(dev, "failed to disable bridges\n"); |
0fa20cdf AT |
265 | goto err_put_br; |
266 | } | |
267 | ||
5cf0c7f6 | 268 | ret = fpga_mgr_load(mgr, region->info); |
0fa20cdf | 269 | if (ret) { |
c3d971ad | 270 | dev_err(dev, "failed to load FPGA image\n"); |
0fa20cdf AT |
271 | goto err_put_br; |
272 | } | |
273 | ||
274 | ret = fpga_bridges_enable(®ion->bridge_list); | |
275 | if (ret) { | |
c3d971ad | 276 | dev_err(dev, "failed to enable region bridges\n"); |
0fa20cdf AT |
277 | goto err_put_br; |
278 | } | |
279 | ||
ebf877a5 | 280 | fpga_mgr_unlock(mgr); |
0fa20cdf AT |
281 | fpga_mgr_put(mgr); |
282 | fpga_region_put(region); | |
283 | ||
284 | return 0; | |
285 | ||
286 | err_put_br: | |
287 | fpga_bridges_put(®ion->bridge_list); | |
ebf877a5 AT |
288 | err_unlock_mgr: |
289 | fpga_mgr_unlock(mgr); | |
0fa20cdf AT |
290 | err_put_mgr: |
291 | fpga_mgr_put(mgr); | |
e73bbf64 | 292 | err_put_region: |
0fa20cdf AT |
293 | fpga_region_put(region); |
294 | ||
295 | return ret; | |
296 | } | |
297 | ||
298 | /** | |
299 | * child_regions_with_firmware | |
300 | * @overlay: device node of the overlay | |
301 | * | |
302 | * If the overlay adds child FPGA regions, they are not allowed to have | |
303 | * firmware-name property. | |
304 | * | |
305 | * Return 0 for OK or -EINVAL if child FPGA region adds firmware-name. | |
306 | */ | |
307 | static int child_regions_with_firmware(struct device_node *overlay) | |
308 | { | |
309 | struct device_node *child_region; | |
310 | const char *child_firmware_name; | |
311 | int ret = 0; | |
312 | ||
313 | of_node_get(overlay); | |
314 | ||
315 | child_region = of_find_matching_node(overlay, fpga_region_of_match); | |
316 | while (child_region) { | |
317 | if (!of_property_read_string(child_region, "firmware-name", | |
318 | &child_firmware_name)) { | |
319 | ret = -EINVAL; | |
320 | break; | |
321 | } | |
322 | child_region = of_find_matching_node(child_region, | |
323 | fpga_region_of_match); | |
324 | } | |
325 | ||
326 | of_node_put(child_region); | |
327 | ||
328 | if (ret) | |
13bf35b5 RH |
329 | pr_err("firmware-name not allowed in child FPGA region: %pOF", |
330 | child_region); | |
0fa20cdf AT |
331 | |
332 | return ret; | |
333 | } | |
334 | ||
335 | /** | |
336 | * fpga_region_notify_pre_apply - pre-apply overlay notification | |
337 | * | |
338 | * @region: FPGA region that the overlay was applied to | |
339 | * @nd: overlay notification data | |
340 | * | |
341 | * Called after when an overlay targeted to a FPGA Region is about to be | |
342 | * applied. Function will check the properties that will be added to the FPGA | |
343 | * region. If the checks pass, it will program the FPGA. | |
344 | * | |
345 | * The checks are: | |
346 | * The overlay must add either firmware-name or external-fpga-config property | |
347 | * to the FPGA Region. | |
348 | * | |
161db575 MF |
349 | * firmware-name : program the FPGA |
350 | * external-fpga-config : FPGA is already programmed | |
351 | * encrypted-fpga-config : FPGA bitstream is encrypted | |
0fa20cdf AT |
352 | * |
353 | * The overlay can add other FPGA regions, but child FPGA regions cannot have a | |
354 | * firmware-name property since those regions don't exist yet. | |
355 | * | |
356 | * If the overlay that breaks the rules, notifier returns an error and the | |
357 | * overlay is rejected before it goes into the main tree. | |
358 | * | |
359 | * Returns 0 for success or negative error code for failure. | |
360 | */ | |
361 | static int fpga_region_notify_pre_apply(struct fpga_region *region, | |
362 | struct of_overlay_notify_data *nd) | |
363 | { | |
5cf0c7f6 | 364 | struct device *dev = ®ion->dev; |
0fa20cdf | 365 | struct fpga_image_info *info; |
5cf0c7f6 | 366 | const char *firmware_name; |
0fa20cdf AT |
367 | int ret; |
368 | ||
5cf0c7f6 | 369 | info = fpga_image_info_alloc(dev); |
0fa20cdf AT |
370 | if (!info) |
371 | return -ENOMEM; | |
372 | ||
0fa20cdf AT |
373 | /* Reject overlay if child FPGA Regions have firmware-name property */ |
374 | ret = child_regions_with_firmware(nd->overlay); | |
375 | if (ret) | |
376 | return ret; | |
377 | ||
378 | /* Read FPGA region properties from the overlay */ | |
379 | if (of_property_read_bool(nd->overlay, "partial-fpga-config")) | |
380 | info->flags |= FPGA_MGR_PARTIAL_RECONFIG; | |
381 | ||
382 | if (of_property_read_bool(nd->overlay, "external-fpga-config")) | |
383 | info->flags |= FPGA_MGR_EXTERNAL_CONFIG; | |
384 | ||
161db575 MF |
385 | if (of_property_read_bool(nd->overlay, "encrypted-fpga-config")) |
386 | info->flags |= FPGA_MGR_ENCRYPTED_BITSTREAM; | |
387 | ||
5cf0c7f6 AT |
388 | if (!of_property_read_string(nd->overlay, "firmware-name", |
389 | &firmware_name)) { | |
390 | info->firmware_name = devm_kstrdup(dev, firmware_name, | |
391 | GFP_KERNEL); | |
392 | if (!info->firmware_name) | |
393 | return -ENOMEM; | |
394 | } | |
0fa20cdf AT |
395 | |
396 | of_property_read_u32(nd->overlay, "region-unfreeze-timeout-us", | |
397 | &info->enable_timeout_us); | |
398 | ||
399 | of_property_read_u32(nd->overlay, "region-freeze-timeout-us", | |
400 | &info->disable_timeout_us); | |
401 | ||
42d5ec95 AT |
402 | of_property_read_u32(nd->overlay, "config-complete-timeout-us", |
403 | &info->config_complete_timeout_us); | |
404 | ||
0fa20cdf | 405 | /* If FPGA was externally programmed, don't specify firmware */ |
5cf0c7f6 | 406 | if ((info->flags & FPGA_MGR_EXTERNAL_CONFIG) && info->firmware_name) { |
c3d971ad | 407 | dev_err(dev, "error: specified firmware and external-fpga-config"); |
5cf0c7f6 | 408 | fpga_image_info_free(info); |
0fa20cdf AT |
409 | return -EINVAL; |
410 | } | |
411 | ||
412 | /* FPGA is already configured externally. We're done. */ | |
5cf0c7f6 AT |
413 | if (info->flags & FPGA_MGR_EXTERNAL_CONFIG) { |
414 | fpga_image_info_free(info); | |
0fa20cdf | 415 | return 0; |
5cf0c7f6 | 416 | } |
0fa20cdf AT |
417 | |
418 | /* If we got this far, we should be programming the FPGA */ | |
5cf0c7f6 | 419 | if (!info->firmware_name) { |
c3d971ad | 420 | dev_err(dev, "should specify firmware-name or external-fpga-config\n"); |
5cf0c7f6 | 421 | fpga_image_info_free(info); |
0fa20cdf AT |
422 | return -EINVAL; |
423 | } | |
424 | ||
5cf0c7f6 AT |
425 | region->info = info; |
426 | ret = fpga_region_program_fpga(region, nd->overlay); | |
427 | if (ret) { | |
428 | fpga_image_info_free(info); | |
429 | region->info = NULL; | |
430 | } | |
431 | ||
432 | return ret; | |
0fa20cdf AT |
433 | } |
434 | ||
435 | /** | |
436 | * fpga_region_notify_post_remove - post-remove overlay notification | |
437 | * | |
438 | * @region: FPGA region that was targeted by the overlay that was removed | |
439 | * @nd: overlay notification data | |
440 | * | |
441 | * Called after an overlay has been removed if the overlay's target was a | |
442 | * FPGA region. | |
443 | */ | |
444 | static void fpga_region_notify_post_remove(struct fpga_region *region, | |
445 | struct of_overlay_notify_data *nd) | |
446 | { | |
447 | fpga_bridges_disable(®ion->bridge_list); | |
448 | fpga_bridges_put(®ion->bridge_list); | |
5cf0c7f6 | 449 | fpga_image_info_free(region->info); |
0fa20cdf AT |
450 | region->info = NULL; |
451 | } | |
452 | ||
453 | /** | |
454 | * of_fpga_region_notify - reconfig notifier for dynamic DT changes | |
455 | * @nb: notifier block | |
456 | * @action: notifier action | |
457 | * @arg: reconfig data | |
458 | * | |
459 | * This notifier handles programming a FPGA when a "firmware-name" property is | |
460 | * added to a fpga-region. | |
461 | * | |
462 | * Returns NOTIFY_OK or error if FPGA programming fails. | |
463 | */ | |
464 | static int of_fpga_region_notify(struct notifier_block *nb, | |
465 | unsigned long action, void *arg) | |
466 | { | |
467 | struct of_overlay_notify_data *nd = arg; | |
468 | struct fpga_region *region; | |
469 | int ret; | |
470 | ||
471 | switch (action) { | |
472 | case OF_OVERLAY_PRE_APPLY: | |
473 | pr_debug("%s OF_OVERLAY_PRE_APPLY\n", __func__); | |
474 | break; | |
475 | case OF_OVERLAY_POST_APPLY: | |
476 | pr_debug("%s OF_OVERLAY_POST_APPLY\n", __func__); | |
477 | return NOTIFY_OK; /* not for us */ | |
478 | case OF_OVERLAY_PRE_REMOVE: | |
479 | pr_debug("%s OF_OVERLAY_PRE_REMOVE\n", __func__); | |
480 | return NOTIFY_OK; /* not for us */ | |
481 | case OF_OVERLAY_POST_REMOVE: | |
482 | pr_debug("%s OF_OVERLAY_POST_REMOVE\n", __func__); | |
483 | break; | |
484 | default: /* should not happen */ | |
485 | return NOTIFY_OK; | |
486 | } | |
487 | ||
488 | region = fpga_region_find(nd->target); | |
489 | if (!region) | |
490 | return NOTIFY_OK; | |
491 | ||
492 | ret = 0; | |
493 | switch (action) { | |
494 | case OF_OVERLAY_PRE_APPLY: | |
495 | ret = fpga_region_notify_pre_apply(region, nd); | |
496 | break; | |
497 | ||
498 | case OF_OVERLAY_POST_REMOVE: | |
499 | fpga_region_notify_post_remove(region, nd); | |
500 | break; | |
501 | } | |
502 | ||
503 | put_device(®ion->dev); | |
504 | ||
505 | if (ret) | |
506 | return notifier_from_errno(ret); | |
507 | ||
508 | return NOTIFY_OK; | |
509 | } | |
510 | ||
511 | static struct notifier_block fpga_region_of_nb = { | |
512 | .notifier_call = of_fpga_region_notify, | |
513 | }; | |
514 | ||
515 | static int fpga_region_probe(struct platform_device *pdev) | |
516 | { | |
517 | struct device *dev = &pdev->dev; | |
518 | struct device_node *np = dev->of_node; | |
519 | struct fpga_region *region; | |
520 | int id, ret = 0; | |
521 | ||
522 | region = kzalloc(sizeof(*region), GFP_KERNEL); | |
523 | if (!region) | |
524 | return -ENOMEM; | |
525 | ||
526 | id = ida_simple_get(&fpga_region_ida, 0, 0, GFP_KERNEL); | |
527 | if (id < 0) { | |
528 | ret = id; | |
529 | goto err_kfree; | |
530 | } | |
531 | ||
532 | mutex_init(®ion->mutex); | |
533 | INIT_LIST_HEAD(®ion->bridge_list); | |
534 | ||
535 | device_initialize(®ion->dev); | |
536 | region->dev.class = fpga_region_class; | |
537 | region->dev.parent = dev; | |
538 | region->dev.of_node = np; | |
539 | region->dev.id = id; | |
540 | dev_set_drvdata(dev, region); | |
541 | ||
542 | ret = dev_set_name(®ion->dev, "region%d", id); | |
543 | if (ret) | |
544 | goto err_remove; | |
545 | ||
546 | ret = device_add(®ion->dev); | |
547 | if (ret) | |
548 | goto err_remove; | |
549 | ||
550 | of_platform_populate(np, fpga_region_of_match, NULL, ®ion->dev); | |
551 | ||
552 | dev_info(dev, "FPGA Region probed\n"); | |
553 | ||
554 | return 0; | |
555 | ||
556 | err_remove: | |
557 | ida_simple_remove(&fpga_region_ida, id); | |
558 | err_kfree: | |
559 | kfree(region); | |
560 | ||
561 | return ret; | |
562 | } | |
563 | ||
564 | static int fpga_region_remove(struct platform_device *pdev) | |
565 | { | |
566 | struct fpga_region *region = platform_get_drvdata(pdev); | |
567 | ||
568 | device_unregister(®ion->dev); | |
569 | ||
570 | return 0; | |
571 | } | |
572 | ||
573 | static struct platform_driver fpga_region_driver = { | |
574 | .probe = fpga_region_probe, | |
575 | .remove = fpga_region_remove, | |
576 | .driver = { | |
577 | .name = "fpga-region", | |
578 | .of_match_table = of_match_ptr(fpga_region_of_match), | |
579 | }, | |
580 | }; | |
581 | ||
582 | static void fpga_region_dev_release(struct device *dev) | |
583 | { | |
584 | struct fpga_region *region = to_fpga_region(dev); | |
585 | ||
586 | ida_simple_remove(&fpga_region_ida, region->dev.id); | |
587 | kfree(region); | |
588 | } | |
589 | ||
590 | /** | |
591 | * fpga_region_init - init function for fpga_region class | |
592 | * Creates the fpga_region class and registers a reconfig notifier. | |
593 | */ | |
594 | static int __init fpga_region_init(void) | |
595 | { | |
596 | int ret; | |
597 | ||
598 | fpga_region_class = class_create(THIS_MODULE, "fpga_region"); | |
599 | if (IS_ERR(fpga_region_class)) | |
600 | return PTR_ERR(fpga_region_class); | |
601 | ||
602 | fpga_region_class->dev_release = fpga_region_dev_release; | |
603 | ||
604 | ret = of_overlay_notifier_register(&fpga_region_of_nb); | |
605 | if (ret) | |
606 | goto err_class; | |
607 | ||
608 | ret = platform_driver_register(&fpga_region_driver); | |
609 | if (ret) | |
610 | goto err_plat; | |
611 | ||
612 | return 0; | |
613 | ||
614 | err_plat: | |
615 | of_overlay_notifier_unregister(&fpga_region_of_nb); | |
616 | err_class: | |
617 | class_destroy(fpga_region_class); | |
618 | ida_destroy(&fpga_region_ida); | |
619 | return ret; | |
620 | } | |
621 | ||
622 | static void __exit fpga_region_exit(void) | |
623 | { | |
624 | platform_driver_unregister(&fpga_region_driver); | |
625 | of_overlay_notifier_unregister(&fpga_region_of_nb); | |
626 | class_destroy(fpga_region_class); | |
627 | ida_destroy(&fpga_region_ida); | |
628 | } | |
629 | ||
630 | subsys_initcall(fpga_region_init); | |
631 | module_exit(fpga_region_exit); | |
632 | ||
633 | MODULE_DESCRIPTION("FPGA Region"); | |
634 | MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>"); | |
635 | MODULE_LICENSE("GPL v2"); |