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473f01f7 | 1 | // SPDX-License-Identifier: GPL-2.0 |
6a8c3be7 AT |
2 | /* |
3 | * FPGA Manager Core | |
4 | * | |
5 | * Copyright (C) 2013-2015 Altera Corporation | |
5cf0c7f6 | 6 | * Copyright (C) 2017 Intel Corporation |
6a8c3be7 AT |
7 | * |
8 | * With code from the mailing list: | |
9 | * Copyright (C) 2013 Xilinx, Inc. | |
6a8c3be7 AT |
10 | */ |
11 | #include <linux/firmware.h> | |
12 | #include <linux/fpga/fpga-mgr.h> | |
13 | #include <linux/idr.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/of.h> | |
16 | #include <linux/mutex.h> | |
17 | #include <linux/slab.h> | |
baa6d396 JG |
18 | #include <linux/scatterlist.h> |
19 | #include <linux/highmem.h> | |
6a8c3be7 AT |
20 | |
21 | static DEFINE_IDA(fpga_mgr_ida); | |
22 | static struct class *fpga_mgr_class; | |
23 | ||
57d9352b MF |
24 | struct fpga_mgr_devres { |
25 | struct fpga_manager *mgr; | |
26 | }; | |
27 | ||
ff9da89c AT |
28 | /** |
29 | * fpga_image_info_alloc - Allocate a FPGA image info struct | |
30 | * @dev: owning device | |
31 | * | |
32 | * Return: struct fpga_image_info or NULL | |
33 | */ | |
5cf0c7f6 AT |
34 | struct fpga_image_info *fpga_image_info_alloc(struct device *dev) |
35 | { | |
36 | struct fpga_image_info *info; | |
37 | ||
38 | get_device(dev); | |
39 | ||
40 | info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); | |
41 | if (!info) { | |
42 | put_device(dev); | |
43 | return NULL; | |
44 | } | |
45 | ||
46 | info->dev = dev; | |
47 | ||
48 | return info; | |
49 | } | |
50 | EXPORT_SYMBOL_GPL(fpga_image_info_alloc); | |
51 | ||
ff9da89c AT |
52 | /** |
53 | * fpga_image_info_free - Free a FPGA image info struct | |
54 | * @info: FPGA image info struct to free | |
55 | */ | |
5cf0c7f6 AT |
56 | void fpga_image_info_free(struct fpga_image_info *info) |
57 | { | |
58 | struct device *dev; | |
59 | ||
60 | if (!info) | |
61 | return; | |
62 | ||
63 | dev = info->dev; | |
64 | if (info->firmware_name) | |
65 | devm_kfree(dev, info->firmware_name); | |
66 | ||
67 | devm_kfree(dev, info); | |
68 | put_device(dev); | |
69 | } | |
70 | EXPORT_SYMBOL_GPL(fpga_image_info_free); | |
71 | ||
baa6d396 JG |
72 | /* |
73 | * Call the low level driver's write_init function. This will do the | |
74 | * device-specific things to get the FPGA into the state where it is ready to | |
75 | * receive an FPGA image. The low level driver only gets to see the first | |
76 | * initial_header_size bytes in the buffer. | |
77 | */ | |
78 | static int fpga_mgr_write_init_buf(struct fpga_manager *mgr, | |
79 | struct fpga_image_info *info, | |
80 | const char *buf, size_t count) | |
81 | { | |
82 | int ret; | |
83 | ||
84 | mgr->state = FPGA_MGR_STATE_WRITE_INIT; | |
85 | if (!mgr->mops->initial_header_size) | |
86 | ret = mgr->mops->write_init(mgr, info, NULL, 0); | |
87 | else | |
88 | ret = mgr->mops->write_init( | |
89 | mgr, info, buf, min(mgr->mops->initial_header_size, count)); | |
90 | ||
91 | if (ret) { | |
92 | dev_err(&mgr->dev, "Error preparing FPGA for writing\n"); | |
93 | mgr->state = FPGA_MGR_STATE_WRITE_INIT_ERR; | |
94 | return ret; | |
95 | } | |
96 | ||
97 | return 0; | |
98 | } | |
99 | ||
100 | static int fpga_mgr_write_init_sg(struct fpga_manager *mgr, | |
101 | struct fpga_image_info *info, | |
102 | struct sg_table *sgt) | |
103 | { | |
104 | struct sg_mapping_iter miter; | |
105 | size_t len; | |
106 | char *buf; | |
107 | int ret; | |
108 | ||
109 | if (!mgr->mops->initial_header_size) | |
110 | return fpga_mgr_write_init_buf(mgr, info, NULL, 0); | |
111 | ||
112 | /* | |
113 | * First try to use miter to map the first fragment to access the | |
114 | * header, this is the typical path. | |
115 | */ | |
116 | sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG); | |
117 | if (sg_miter_next(&miter) && | |
118 | miter.length >= mgr->mops->initial_header_size) { | |
119 | ret = fpga_mgr_write_init_buf(mgr, info, miter.addr, | |
120 | miter.length); | |
121 | sg_miter_stop(&miter); | |
122 | return ret; | |
123 | } | |
124 | sg_miter_stop(&miter); | |
125 | ||
126 | /* Otherwise copy the fragments into temporary memory. */ | |
127 | buf = kmalloc(mgr->mops->initial_header_size, GFP_KERNEL); | |
128 | if (!buf) | |
129 | return -ENOMEM; | |
130 | ||
131 | len = sg_copy_to_buffer(sgt->sgl, sgt->nents, buf, | |
132 | mgr->mops->initial_header_size); | |
133 | ret = fpga_mgr_write_init_buf(mgr, info, buf, len); | |
134 | ||
135 | kfree(buf); | |
136 | ||
137 | return ret; | |
138 | } | |
139 | ||
140 | /* | |
141 | * After all the FPGA image has been written, do the device specific steps to | |
142 | * finish and set the FPGA into operating mode. | |
143 | */ | |
144 | static int fpga_mgr_write_complete(struct fpga_manager *mgr, | |
145 | struct fpga_image_info *info) | |
146 | { | |
147 | int ret; | |
148 | ||
149 | mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE; | |
150 | ret = mgr->mops->write_complete(mgr, info); | |
151 | if (ret) { | |
152 | dev_err(&mgr->dev, "Error after writing image data to FPGA\n"); | |
153 | mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE_ERR; | |
154 | return ret; | |
155 | } | |
156 | mgr->state = FPGA_MGR_STATE_OPERATING; | |
157 | ||
158 | return 0; | |
159 | } | |
160 | ||
6a8c3be7 | 161 | /** |
baa6d396 | 162 | * fpga_mgr_buf_load_sg - load fpga from image in buffer from a scatter list |
6a8c3be7 | 163 | * @mgr: fpga manager |
1df2865f | 164 | * @info: fpga image specific information |
baa6d396 | 165 | * @sgt: scatterlist table |
6a8c3be7 AT |
166 | * |
167 | * Step the low level fpga manager through the device-specific steps of getting | |
168 | * an FPGA ready to be configured, writing the image to it, then doing whatever | |
92d94a7e | 169 | * post-configuration steps necessary. This code assumes the caller got the |
9dce0287 AT |
170 | * mgr pointer from of_fpga_mgr_get() or fpga_mgr_get() and checked that it is |
171 | * not an error code. | |
6a8c3be7 | 172 | * |
baa6d396 JG |
173 | * This is the preferred entry point for FPGA programming, it does not require |
174 | * any contiguous kernel memory. | |
175 | * | |
6a8c3be7 AT |
176 | * Return: 0 on success, negative error code otherwise. |
177 | */ | |
5cf0c7f6 AT |
178 | static int fpga_mgr_buf_load_sg(struct fpga_manager *mgr, |
179 | struct fpga_image_info *info, | |
180 | struct sg_table *sgt) | |
6a8c3be7 | 181 | { |
6a8c3be7 AT |
182 | int ret; |
183 | ||
baa6d396 JG |
184 | ret = fpga_mgr_write_init_sg(mgr, info, sgt); |
185 | if (ret) | |
186 | return ret; | |
187 | ||
188 | /* Write the FPGA image to the FPGA. */ | |
189 | mgr->state = FPGA_MGR_STATE_WRITE; | |
190 | if (mgr->mops->write_sg) { | |
191 | ret = mgr->mops->write_sg(mgr, sgt); | |
192 | } else { | |
193 | struct sg_mapping_iter miter; | |
194 | ||
195 | sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG); | |
196 | while (sg_miter_next(&miter)) { | |
197 | ret = mgr->mops->write(mgr, miter.addr, miter.length); | |
198 | if (ret) | |
199 | break; | |
200 | } | |
201 | sg_miter_stop(&miter); | |
202 | } | |
203 | ||
6a8c3be7 | 204 | if (ret) { |
baa6d396 JG |
205 | dev_err(&mgr->dev, "Error while writing image data to FPGA\n"); |
206 | mgr->state = FPGA_MGR_STATE_WRITE_ERR; | |
6a8c3be7 AT |
207 | return ret; |
208 | } | |
209 | ||
baa6d396 JG |
210 | return fpga_mgr_write_complete(mgr, info); |
211 | } | |
baa6d396 JG |
212 | |
213 | static int fpga_mgr_buf_load_mapped(struct fpga_manager *mgr, | |
214 | struct fpga_image_info *info, | |
215 | const char *buf, size_t count) | |
216 | { | |
217 | int ret; | |
218 | ||
219 | ret = fpga_mgr_write_init_buf(mgr, info, buf, count); | |
220 | if (ret) | |
221 | return ret; | |
222 | ||
6a8c3be7 AT |
223 | /* |
224 | * Write the FPGA image to the FPGA. | |
225 | */ | |
226 | mgr->state = FPGA_MGR_STATE_WRITE; | |
227 | ret = mgr->mops->write(mgr, buf, count); | |
228 | if (ret) { | |
baa6d396 | 229 | dev_err(&mgr->dev, "Error while writing image data to FPGA\n"); |
6a8c3be7 AT |
230 | mgr->state = FPGA_MGR_STATE_WRITE_ERR; |
231 | return ret; | |
232 | } | |
233 | ||
baa6d396 JG |
234 | return fpga_mgr_write_complete(mgr, info); |
235 | } | |
236 | ||
237 | /** | |
238 | * fpga_mgr_buf_load - load fpga from image in buffer | |
239 | * @mgr: fpga manager | |
ff9da89c | 240 | * @info: fpga image info |
baa6d396 JG |
241 | * @buf: buffer contain fpga image |
242 | * @count: byte count of buf | |
243 | * | |
244 | * Step the low level fpga manager through the device-specific steps of getting | |
245 | * an FPGA ready to be configured, writing the image to it, then doing whatever | |
246 | * post-configuration steps necessary. This code assumes the caller got the | |
247 | * mgr pointer from of_fpga_mgr_get() and checked that it is not an error code. | |
248 | * | |
249 | * Return: 0 on success, negative error code otherwise. | |
250 | */ | |
5cf0c7f6 AT |
251 | static int fpga_mgr_buf_load(struct fpga_manager *mgr, |
252 | struct fpga_image_info *info, | |
253 | const char *buf, size_t count) | |
baa6d396 JG |
254 | { |
255 | struct page **pages; | |
256 | struct sg_table sgt; | |
257 | const void *p; | |
258 | int nr_pages; | |
259 | int index; | |
260 | int rc; | |
261 | ||
6a8c3be7 | 262 | /* |
baa6d396 JG |
263 | * This is just a fast path if the caller has already created a |
264 | * contiguous kernel buffer and the driver doesn't require SG, non-SG | |
265 | * drivers will still work on the slow path. | |
6a8c3be7 | 266 | */ |
baa6d396 JG |
267 | if (mgr->mops->write) |
268 | return fpga_mgr_buf_load_mapped(mgr, info, buf, count); | |
269 | ||
270 | /* | |
271 | * Convert the linear kernel pointer into a sg_table of pages for use | |
272 | * by the driver. | |
273 | */ | |
274 | nr_pages = DIV_ROUND_UP((unsigned long)buf + count, PAGE_SIZE) - | |
275 | (unsigned long)buf / PAGE_SIZE; | |
276 | pages = kmalloc_array(nr_pages, sizeof(struct page *), GFP_KERNEL); | |
277 | if (!pages) | |
278 | return -ENOMEM; | |
279 | ||
280 | p = buf - offset_in_page(buf); | |
281 | for (index = 0; index < nr_pages; index++) { | |
282 | if (is_vmalloc_addr(p)) | |
283 | pages[index] = vmalloc_to_page(p); | |
284 | else | |
285 | pages[index] = kmap_to_page((void *)p); | |
286 | if (!pages[index]) { | |
287 | kfree(pages); | |
288 | return -EFAULT; | |
289 | } | |
290 | p += PAGE_SIZE; | |
6a8c3be7 | 291 | } |
6a8c3be7 | 292 | |
baa6d396 JG |
293 | /* |
294 | * The temporary pages list is used to code share the merging algorithm | |
295 | * in sg_alloc_table_from_pages | |
296 | */ | |
297 | rc = sg_alloc_table_from_pages(&sgt, pages, index, offset_in_page(buf), | |
298 | count, GFP_KERNEL); | |
299 | kfree(pages); | |
300 | if (rc) | |
301 | return rc; | |
302 | ||
303 | rc = fpga_mgr_buf_load_sg(mgr, info, &sgt); | |
304 | sg_free_table(&sgt); | |
305 | ||
306 | return rc; | |
6a8c3be7 | 307 | } |
6a8c3be7 AT |
308 | |
309 | /** | |
310 | * fpga_mgr_firmware_load - request firmware and load to fpga | |
311 | * @mgr: fpga manager | |
1df2865f | 312 | * @info: fpga image specific information |
6a8c3be7 AT |
313 | * @image_name: name of image file on the firmware search path |
314 | * | |
315 | * Request an FPGA image using the firmware class, then write out to the FPGA. | |
316 | * Update the state before each step to provide info on what step failed if | |
92d94a7e | 317 | * there is a failure. This code assumes the caller got the mgr pointer |
9dce0287 AT |
318 | * from of_fpga_mgr_get() or fpga_mgr_get() and checked that it is not an error |
319 | * code. | |
6a8c3be7 AT |
320 | * |
321 | * Return: 0 on success, negative error code otherwise. | |
322 | */ | |
5cf0c7f6 AT |
323 | static int fpga_mgr_firmware_load(struct fpga_manager *mgr, |
324 | struct fpga_image_info *info, | |
325 | const char *image_name) | |
6a8c3be7 AT |
326 | { |
327 | struct device *dev = &mgr->dev; | |
328 | const struct firmware *fw; | |
329 | int ret; | |
330 | ||
6a8c3be7 AT |
331 | dev_info(dev, "writing %s to %s\n", image_name, mgr->name); |
332 | ||
333 | mgr->state = FPGA_MGR_STATE_FIRMWARE_REQ; | |
334 | ||
335 | ret = request_firmware(&fw, image_name, dev); | |
336 | if (ret) { | |
337 | mgr->state = FPGA_MGR_STATE_FIRMWARE_REQ_ERR; | |
338 | dev_err(dev, "Error requesting firmware %s\n", image_name); | |
339 | return ret; | |
340 | } | |
341 | ||
1df2865f | 342 | ret = fpga_mgr_buf_load(mgr, info, fw->data, fw->size); |
6a8c3be7 AT |
343 | |
344 | release_firmware(fw); | |
345 | ||
e8c77bda | 346 | return ret; |
6a8c3be7 | 347 | } |
5cf0c7f6 | 348 | |
ff9da89c AT |
349 | /** |
350 | * fpga_mgr_load - load FPGA from scatter/gather table, buffer, or firmware | |
351 | * @mgr: fpga manager | |
352 | * @info: fpga image information. | |
353 | * | |
354 | * Load the FPGA from an image which is indicated in @info. If successful, the | |
355 | * FPGA ends up in operating mode. | |
356 | * | |
357 | * Return: 0 on success, negative error code otherwise. | |
358 | */ | |
5cf0c7f6 AT |
359 | int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info) |
360 | { | |
361 | if (info->sgt) | |
362 | return fpga_mgr_buf_load_sg(mgr, info, info->sgt); | |
363 | if (info->buf && info->count) | |
364 | return fpga_mgr_buf_load(mgr, info, info->buf, info->count); | |
365 | if (info->firmware_name) | |
366 | return fpga_mgr_firmware_load(mgr, info, info->firmware_name); | |
367 | return -EINVAL; | |
368 | } | |
369 | EXPORT_SYMBOL_GPL(fpga_mgr_load); | |
6a8c3be7 AT |
370 | |
371 | static const char * const state_str[] = { | |
372 | [FPGA_MGR_STATE_UNKNOWN] = "unknown", | |
373 | [FPGA_MGR_STATE_POWER_OFF] = "power off", | |
374 | [FPGA_MGR_STATE_POWER_UP] = "power up", | |
375 | [FPGA_MGR_STATE_RESET] = "reset", | |
376 | ||
377 | /* requesting FPGA image from firmware */ | |
378 | [FPGA_MGR_STATE_FIRMWARE_REQ] = "firmware request", | |
379 | [FPGA_MGR_STATE_FIRMWARE_REQ_ERR] = "firmware request error", | |
380 | ||
381 | /* Preparing FPGA to receive image */ | |
382 | [FPGA_MGR_STATE_WRITE_INIT] = "write init", | |
383 | [FPGA_MGR_STATE_WRITE_INIT_ERR] = "write init error", | |
384 | ||
385 | /* Writing image to FPGA */ | |
386 | [FPGA_MGR_STATE_WRITE] = "write", | |
387 | [FPGA_MGR_STATE_WRITE_ERR] = "write error", | |
388 | ||
389 | /* Finishing configuration after image has been written */ | |
390 | [FPGA_MGR_STATE_WRITE_COMPLETE] = "write complete", | |
391 | [FPGA_MGR_STATE_WRITE_COMPLETE_ERR] = "write complete error", | |
392 | ||
393 | /* FPGA reports to be in normal operating mode */ | |
394 | [FPGA_MGR_STATE_OPERATING] = "operating", | |
395 | }; | |
396 | ||
397 | static ssize_t name_show(struct device *dev, | |
398 | struct device_attribute *attr, char *buf) | |
399 | { | |
400 | struct fpga_manager *mgr = to_fpga_manager(dev); | |
401 | ||
402 | return sprintf(buf, "%s\n", mgr->name); | |
403 | } | |
404 | ||
405 | static ssize_t state_show(struct device *dev, | |
406 | struct device_attribute *attr, char *buf) | |
407 | { | |
408 | struct fpga_manager *mgr = to_fpga_manager(dev); | |
409 | ||
410 | return sprintf(buf, "%s\n", state_str[mgr->state]); | |
411 | } | |
412 | ||
ecb5fbe2 WH |
413 | static ssize_t status_show(struct device *dev, |
414 | struct device_attribute *attr, char *buf) | |
415 | { | |
416 | struct fpga_manager *mgr = to_fpga_manager(dev); | |
417 | u64 status; | |
418 | int len = 0; | |
419 | ||
420 | if (!mgr->mops->status) | |
421 | return -ENOENT; | |
422 | ||
423 | status = mgr->mops->status(mgr); | |
424 | ||
425 | if (status & FPGA_MGR_STATUS_OPERATION_ERR) | |
426 | len += sprintf(buf + len, "reconfig operation error\n"); | |
427 | if (status & FPGA_MGR_STATUS_CRC_ERR) | |
428 | len += sprintf(buf + len, "reconfig CRC error\n"); | |
429 | if (status & FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR) | |
430 | len += sprintf(buf + len, "reconfig incompatible image\n"); | |
431 | if (status & FPGA_MGR_STATUS_IP_PROTOCOL_ERR) | |
432 | len += sprintf(buf + len, "reconfig IP protocol error\n"); | |
433 | if (status & FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR) | |
434 | len += sprintf(buf + len, "reconfig fifo overflow error\n"); | |
435 | ||
436 | return len; | |
437 | } | |
438 | ||
6a8c3be7 AT |
439 | static DEVICE_ATTR_RO(name); |
440 | static DEVICE_ATTR_RO(state); | |
ecb5fbe2 | 441 | static DEVICE_ATTR_RO(status); |
6a8c3be7 AT |
442 | |
443 | static struct attribute *fpga_mgr_attrs[] = { | |
444 | &dev_attr_name.attr, | |
445 | &dev_attr_state.attr, | |
ecb5fbe2 | 446 | &dev_attr_status.attr, |
6a8c3be7 AT |
447 | NULL, |
448 | }; | |
449 | ATTRIBUTE_GROUPS(fpga_mgr); | |
450 | ||
47910a49 | 451 | static struct fpga_manager *__fpga_mgr_get(struct device *dev) |
6a8c3be7 AT |
452 | { |
453 | struct fpga_manager *mgr; | |
6a8c3be7 | 454 | |
6a8c3be7 | 455 | mgr = to_fpga_manager(dev); |
6a8c3be7 | 456 | |
654ba4cc | 457 | if (!try_module_get(dev->parent->driver->owner)) |
ebf877a5 | 458 | goto err_dev; |
654ba4cc | 459 | |
6a8c3be7 | 460 | return mgr; |
654ba4cc | 461 | |
654ba4cc AT |
462 | err_dev: |
463 | put_device(dev); | |
ebf877a5 | 464 | return ERR_PTR(-ENODEV); |
6a8c3be7 | 465 | } |
9dce0287 AT |
466 | |
467 | static int fpga_mgr_dev_match(struct device *dev, const void *data) | |
468 | { | |
469 | return dev->parent == data; | |
470 | } | |
471 | ||
472 | /** | |
ff9da89c | 473 | * fpga_mgr_get - Given a device, get a reference to a fpga mgr. |
9dce0287 AT |
474 | * @dev: parent device that fpga mgr was registered with |
475 | * | |
9dce0287 AT |
476 | * Return: fpga manager struct or IS_ERR() condition containing error code. |
477 | */ | |
478 | struct fpga_manager *fpga_mgr_get(struct device *dev) | |
479 | { | |
480 | struct device *mgr_dev = class_find_device(fpga_mgr_class, NULL, dev, | |
481 | fpga_mgr_dev_match); | |
482 | if (!mgr_dev) | |
483 | return ERR_PTR(-ENODEV); | |
484 | ||
485 | return __fpga_mgr_get(mgr_dev); | |
486 | } | |
487 | EXPORT_SYMBOL_GPL(fpga_mgr_get); | |
488 | ||
9dce0287 | 489 | /** |
ff9da89c | 490 | * of_fpga_mgr_get - Given a device node, get a reference to a fpga mgr. |
9dce0287 | 491 | * |
ff9da89c | 492 | * @node: device node |
9dce0287 AT |
493 | * |
494 | * Return: fpga manager struct or IS_ERR() condition containing error code. | |
495 | */ | |
496 | struct fpga_manager *of_fpga_mgr_get(struct device_node *node) | |
497 | { | |
498 | struct device *dev; | |
499 | ||
cfba5de9 | 500 | dev = class_find_device_by_of_node(fpga_mgr_class, node); |
9dce0287 AT |
501 | if (!dev) |
502 | return ERR_PTR(-ENODEV); | |
503 | ||
504 | return __fpga_mgr_get(dev); | |
505 | } | |
6a8c3be7 AT |
506 | EXPORT_SYMBOL_GPL(of_fpga_mgr_get); |
507 | ||
508 | /** | |
509 | * fpga_mgr_put - release a reference to a fpga manager | |
510 | * @mgr: fpga manager structure | |
511 | */ | |
512 | void fpga_mgr_put(struct fpga_manager *mgr) | |
513 | { | |
654ba4cc | 514 | module_put(mgr->dev.parent->driver->owner); |
654ba4cc | 515 | put_device(&mgr->dev); |
6a8c3be7 AT |
516 | } |
517 | EXPORT_SYMBOL_GPL(fpga_mgr_put); | |
518 | ||
ebf877a5 AT |
519 | /** |
520 | * fpga_mgr_lock - Lock FPGA manager for exclusive use | |
521 | * @mgr: fpga manager | |
522 | * | |
523 | * Given a pointer to FPGA Manager (from fpga_mgr_get() or | |
ff9da89c AT |
524 | * of_fpga_mgr_put()) attempt to get the mutex. The user should call |
525 | * fpga_mgr_lock() and verify that it returns 0 before attempting to | |
526 | * program the FPGA. Likewise, the user should call fpga_mgr_unlock | |
527 | * when done programming the FPGA. | |
ebf877a5 AT |
528 | * |
529 | * Return: 0 for success or -EBUSY | |
530 | */ | |
531 | int fpga_mgr_lock(struct fpga_manager *mgr) | |
532 | { | |
533 | if (!mutex_trylock(&mgr->ref_mutex)) { | |
534 | dev_err(&mgr->dev, "FPGA manager is in use.\n"); | |
535 | return -EBUSY; | |
536 | } | |
537 | ||
538 | return 0; | |
539 | } | |
540 | EXPORT_SYMBOL_GPL(fpga_mgr_lock); | |
541 | ||
542 | /** | |
ff9da89c | 543 | * fpga_mgr_unlock - Unlock FPGA manager after done programming |
ebf877a5 AT |
544 | * @mgr: fpga manager |
545 | */ | |
546 | void fpga_mgr_unlock(struct fpga_manager *mgr) | |
547 | { | |
548 | mutex_unlock(&mgr->ref_mutex); | |
549 | } | |
550 | EXPORT_SYMBOL_GPL(fpga_mgr_unlock); | |
551 | ||
6a8c3be7 | 552 | /** |
7085e2a9 | 553 | * fpga_mgr_create - create and initialize a FPGA manager struct |
6a8c3be7 AT |
554 | * @dev: fpga manager device from pdev |
555 | * @name: fpga manager name | |
556 | * @mops: pointer to structure of fpga manager ops | |
557 | * @priv: fpga manager private data | |
558 | * | |
084181fe AT |
559 | * The caller of this function is responsible for freeing the struct with |
560 | * fpga_mgr_free(). Using devm_fpga_mgr_create() instead is recommended. | |
561 | * | |
7085e2a9 | 562 | * Return: pointer to struct fpga_manager or NULL |
6a8c3be7 | 563 | */ |
7085e2a9 AT |
564 | struct fpga_manager *fpga_mgr_create(struct device *dev, const char *name, |
565 | const struct fpga_manager_ops *mops, | |
566 | void *priv) | |
6a8c3be7 AT |
567 | { |
568 | struct fpga_manager *mgr; | |
6a8c3be7 AT |
569 | int id, ret; |
570 | ||
baa6d396 JG |
571 | if (!mops || !mops->write_complete || !mops->state || |
572 | !mops->write_init || (!mops->write && !mops->write_sg) || | |
573 | (mops->write && mops->write_sg)) { | |
6a8c3be7 | 574 | dev_err(dev, "Attempt to register without fpga_manager_ops\n"); |
7085e2a9 | 575 | return NULL; |
6a8c3be7 AT |
576 | } |
577 | ||
578 | if (!name || !strlen(name)) { | |
579 | dev_err(dev, "Attempt to register with no name!\n"); | |
7085e2a9 | 580 | return NULL; |
6a8c3be7 AT |
581 | } |
582 | ||
583 | mgr = kzalloc(sizeof(*mgr), GFP_KERNEL); | |
584 | if (!mgr) | |
7085e2a9 | 585 | return NULL; |
6a8c3be7 AT |
586 | |
587 | id = ida_simple_get(&fpga_mgr_ida, 0, 0, GFP_KERNEL); | |
88aaab92 | 588 | if (id < 0) |
6a8c3be7 | 589 | goto error_kfree; |
6a8c3be7 AT |
590 | |
591 | mutex_init(&mgr->ref_mutex); | |
592 | ||
593 | mgr->name = name; | |
594 | mgr->mops = mops; | |
595 | mgr->priv = priv; | |
596 | ||
6a8c3be7 AT |
597 | device_initialize(&mgr->dev); |
598 | mgr->dev.class = fpga_mgr_class; | |
845089bb | 599 | mgr->dev.groups = mops->groups; |
6a8c3be7 AT |
600 | mgr->dev.parent = dev; |
601 | mgr->dev.of_node = dev->of_node; | |
602 | mgr->dev.id = id; | |
6a8c3be7 | 603 | |
07687c03 AT |
604 | ret = dev_set_name(&mgr->dev, "fpga%d", id); |
605 | if (ret) | |
606 | goto error_device; | |
6a8c3be7 | 607 | |
7085e2a9 AT |
608 | return mgr; |
609 | ||
610 | error_device: | |
611 | ida_simple_remove(&fpga_mgr_ida, id); | |
612 | error_kfree: | |
613 | kfree(mgr); | |
614 | ||
615 | return NULL; | |
616 | } | |
617 | EXPORT_SYMBOL_GPL(fpga_mgr_create); | |
618 | ||
619 | /** | |
084181fe AT |
620 | * fpga_mgr_free - free a FPGA manager created with fpga_mgr_create() |
621 | * @mgr: fpga manager struct | |
7085e2a9 AT |
622 | */ |
623 | void fpga_mgr_free(struct fpga_manager *mgr) | |
624 | { | |
625 | ida_simple_remove(&fpga_mgr_ida, mgr->dev.id); | |
626 | kfree(mgr); | |
627 | } | |
628 | EXPORT_SYMBOL_GPL(fpga_mgr_free); | |
629 | ||
084181fe AT |
630 | static void devm_fpga_mgr_release(struct device *dev, void *res) |
631 | { | |
57d9352b | 632 | struct fpga_mgr_devres *dr = res; |
084181fe | 633 | |
57d9352b | 634 | fpga_mgr_free(dr->mgr); |
084181fe AT |
635 | } |
636 | ||
637 | /** | |
638 | * devm_fpga_mgr_create - create and initialize a managed FPGA manager struct | |
639 | * @dev: fpga manager device from pdev | |
640 | * @name: fpga manager name | |
641 | * @mops: pointer to structure of fpga manager ops | |
642 | * @priv: fpga manager private data | |
643 | * | |
644 | * This function is intended for use in a FPGA manager driver's probe function. | |
645 | * After the manager driver creates the manager struct with | |
646 | * devm_fpga_mgr_create(), it should register it with fpga_mgr_register(). The | |
647 | * manager driver's remove function should call fpga_mgr_unregister(). The | |
648 | * manager struct allocated with this function will be freed automatically on | |
649 | * driver detach. This includes the case of a probe function returning error | |
650 | * before calling fpga_mgr_register(), the struct will still get cleaned up. | |
651 | * | |
652 | * Return: pointer to struct fpga_manager or NULL | |
653 | */ | |
654 | struct fpga_manager *devm_fpga_mgr_create(struct device *dev, const char *name, | |
655 | const struct fpga_manager_ops *mops, | |
656 | void *priv) | |
657 | { | |
57d9352b | 658 | struct fpga_mgr_devres *dr; |
084181fe | 659 | |
57d9352b MF |
660 | dr = devres_alloc(devm_fpga_mgr_release, sizeof(*dr), GFP_KERNEL); |
661 | if (!dr) | |
084181fe AT |
662 | return NULL; |
663 | ||
57d9352b MF |
664 | dr->mgr = fpga_mgr_create(dev, name, mops, priv); |
665 | if (!dr->mgr) { | |
666 | devres_free(dr); | |
667 | return NULL; | |
084181fe AT |
668 | } |
669 | ||
57d9352b MF |
670 | devres_add(dev, dr); |
671 | ||
672 | return dr->mgr; | |
084181fe AT |
673 | } |
674 | EXPORT_SYMBOL_GPL(devm_fpga_mgr_create); | |
675 | ||
7085e2a9 AT |
676 | /** |
677 | * fpga_mgr_register - register a FPGA manager | |
084181fe | 678 | * @mgr: fpga manager struct |
7085e2a9 AT |
679 | * |
680 | * Return: 0 on success, negative error code otherwise. | |
681 | */ | |
682 | int fpga_mgr_register(struct fpga_manager *mgr) | |
683 | { | |
684 | int ret; | |
685 | ||
686 | /* | |
687 | * Initialize framework state by requesting low level driver read state | |
688 | * from device. FPGA may be in reset mode or may have been programmed | |
689 | * by bootloader or EEPROM. | |
690 | */ | |
691 | mgr->state = mgr->mops->state(mgr); | |
692 | ||
6a8c3be7 AT |
693 | ret = device_add(&mgr->dev); |
694 | if (ret) | |
695 | goto error_device; | |
696 | ||
697 | dev_info(&mgr->dev, "%s registered\n", mgr->name); | |
698 | ||
699 | return 0; | |
700 | ||
701 | error_device: | |
7085e2a9 | 702 | ida_simple_remove(&fpga_mgr_ida, mgr->dev.id); |
6a8c3be7 AT |
703 | |
704 | return ret; | |
705 | } | |
706 | EXPORT_SYMBOL_GPL(fpga_mgr_register); | |
707 | ||
708 | /** | |
084181fe AT |
709 | * fpga_mgr_unregister - unregister a FPGA manager |
710 | * @mgr: fpga manager struct | |
711 | * | |
712 | * This function is intended for use in a FPGA manager driver's remove function. | |
6a8c3be7 | 713 | */ |
7085e2a9 | 714 | void fpga_mgr_unregister(struct fpga_manager *mgr) |
6a8c3be7 | 715 | { |
6a8c3be7 AT |
716 | dev_info(&mgr->dev, "%s %s\n", __func__, mgr->name); |
717 | ||
718 | /* | |
719 | * If the low level driver provides a method for putting fpga into | |
720 | * a desired state upon unregister, do it. | |
721 | */ | |
722 | if (mgr->mops->fpga_remove) | |
723 | mgr->mops->fpga_remove(mgr); | |
724 | ||
725 | device_unregister(&mgr->dev); | |
726 | } | |
727 | EXPORT_SYMBOL_GPL(fpga_mgr_unregister); | |
728 | ||
57d9352b MF |
729 | static int fpga_mgr_devres_match(struct device *dev, void *res, |
730 | void *match_data) | |
731 | { | |
732 | struct fpga_mgr_devres *dr = res; | |
733 | ||
734 | return match_data == dr->mgr; | |
735 | } | |
736 | ||
737 | static void devm_fpga_mgr_unregister(struct device *dev, void *res) | |
738 | { | |
739 | struct fpga_mgr_devres *dr = res; | |
740 | ||
741 | fpga_mgr_unregister(dr->mgr); | |
742 | } | |
743 | ||
744 | /** | |
745 | * devm_fpga_mgr_register - resource managed variant of fpga_mgr_register() | |
746 | * @dev: managing device for this FPGA manager | |
747 | * @mgr: fpga manager struct | |
748 | * | |
749 | * This is the devres variant of fpga_mgr_register() for which the unregister | |
750 | * function will be called automatically when the managing device is detached. | |
751 | */ | |
752 | int devm_fpga_mgr_register(struct device *dev, struct fpga_manager *mgr) | |
753 | { | |
754 | struct fpga_mgr_devres *dr; | |
755 | int ret; | |
756 | ||
757 | /* | |
758 | * Make sure that the struct fpga_manager * that is passed in is | |
759 | * managed itself. | |
760 | */ | |
761 | if (WARN_ON(!devres_find(dev, devm_fpga_mgr_release, | |
762 | fpga_mgr_devres_match, mgr))) | |
763 | return -EINVAL; | |
764 | ||
765 | dr = devres_alloc(devm_fpga_mgr_unregister, sizeof(*dr), GFP_KERNEL); | |
766 | if (!dr) | |
767 | return -ENOMEM; | |
768 | ||
769 | ret = fpga_mgr_register(mgr); | |
770 | if (ret) { | |
771 | devres_free(dr); | |
772 | return ret; | |
773 | } | |
774 | ||
775 | dr->mgr = mgr; | |
776 | devres_add(dev, dr); | |
777 | ||
778 | return 0; | |
779 | } | |
780 | EXPORT_SYMBOL_GPL(devm_fpga_mgr_register); | |
781 | ||
6a8c3be7 AT |
782 | static void fpga_mgr_dev_release(struct device *dev) |
783 | { | |
6a8c3be7 AT |
784 | } |
785 | ||
786 | static int __init fpga_mgr_class_init(void) | |
787 | { | |
788 | pr_info("FPGA manager framework\n"); | |
789 | ||
790 | fpga_mgr_class = class_create(THIS_MODULE, "fpga_manager"); | |
791 | if (IS_ERR(fpga_mgr_class)) | |
792 | return PTR_ERR(fpga_mgr_class); | |
793 | ||
794 | fpga_mgr_class->dev_groups = fpga_mgr_groups; | |
795 | fpga_mgr_class->dev_release = fpga_mgr_dev_release; | |
796 | ||
797 | return 0; | |
798 | } | |
799 | ||
800 | static void __exit fpga_mgr_class_exit(void) | |
801 | { | |
802 | class_destroy(fpga_mgr_class); | |
803 | ida_destroy(&fpga_mgr_ida); | |
804 | } | |
805 | ||
5cf0c7f6 | 806 | MODULE_AUTHOR("Alan Tull <atull@kernel.org>"); |
6a8c3be7 AT |
807 | MODULE_DESCRIPTION("FPGA manager framework"); |
808 | MODULE_LICENSE("GPL v2"); | |
809 | ||
810 | subsys_initcall(fpga_mgr_class_init); | |
811 | module_exit(fpga_mgr_class_exit); |