[linux-2.6-block.git] / drivers / fpga / dfl.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Driver Header File for FPGA Device Feature List (DFL) Support
 *
 * Copyright (C) 2017-2018 Intel Corporation, Inc.
 *
 * Authors:
 *   Kang Luwei <luwei.kang@intel.com>
 *   Zhang Yi <yi.z.zhang@intel.com>
 *   Wu Hao <hao.wu@intel.com>
 *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
 */

#ifndef __FPGA_DFL_H
#define __FPGA_DFL_H

#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/fs.h>
#include <linux/iopoll.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/uuid.h>
#include <linux/fpga/fpga-region.h>

/* maximum supported number of ports */
#define MAX_DFL_FPGA_PORT_NUM 4
/* plus one for fme device */
#define MAX_DFL_FEATURE_DEV_NUM    (MAX_DFL_FPGA_PORT_NUM + 1)

/* Reserved 0x0 for Header Group Register and 0xff for AFU */
#define FEATURE_ID_FIU_HEADER		0x0
#define FEATURE_ID_AFU			0xff

#define FME_FEATURE_ID_HEADER		FEATURE_ID_FIU_HEADER
#define FME_FEATURE_ID_THERMAL_MGMT	0x1
#define FME_FEATURE_ID_POWER_MGMT	0x2
#define FME_FEATURE_ID_GLOBAL_IPERF	0x3
#define FME_FEATURE_ID_GLOBAL_ERR	0x4
#define FME_FEATURE_ID_PR_MGMT		0x5
#define FME_FEATURE_ID_HSSI		0x6
#define FME_FEATURE_ID_GLOBAL_DPERF	0x7

#define PORT_FEATURE_ID_HEADER		FEATURE_ID_FIU_HEADER
#define PORT_FEATURE_ID_AFU		FEATURE_ID_AFU
#define PORT_FEATURE_ID_ERROR		0x10
#define PORT_FEATURE_ID_UMSG		0x11
#define PORT_FEATURE_ID_UINT		0x12
#define PORT_FEATURE_ID_STP		0x13

/*
 * Device Feature Header Register Set
 *
 * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers.
 * For AFUs, they have DFH + GUID as common header registers.
 * For private features, they only have DFH register as common header.
 */
#define DFH			0x0
#define GUID_L			0x8
#define GUID_H			0x10
#define NEXT_AFU		0x18

#define DFH_SIZE		0x8

/* Device Feature Header Register Bitfield */
#define DFH_ID			GENMASK_ULL(11, 0)	/* Feature ID */
#define DFH_ID_FIU_FME		0
#define DFH_ID_FIU_PORT		1
#define DFH_REVISION		GENMASK_ULL(15, 12)	/* Feature revision */
#define DFH_NEXT_HDR_OFST	GENMASK_ULL(39, 16)	/* Offset to next DFH */
#define DFH_EOL			BIT_ULL(40)		/* End of list */
#define DFH_TYPE		GENMASK_ULL(63, 60)	/* Feature type */
#define DFH_TYPE_AFU		1
#define DFH_TYPE_PRIVATE	3
#define DFH_TYPE_FIU		4

/* Next AFU Register Bitfield */
#define NEXT_AFU_NEXT_DFH_OFST	GENMASK_ULL(23, 0)	/* Offset to next AFU */

/* FME Header Register Set */
#define FME_HDR_DFH		DFH
#define FME_HDR_GUID_L		GUID_L
#define FME_HDR_GUID_H		GUID_H
#define FME_HDR_NEXT_AFU	NEXT_AFU
#define FME_HDR_CAP		0x30
#define FME_HDR_PORT_OFST(n)	(0x38 + ((n) * 0x8))
#define FME_HDR_BITSTREAM_ID	0x60
#define FME_HDR_BITSTREAM_MD	0x68

/* FME Fab Capability Register Bitfield */
#define FME_CAP_FABRIC_VERID	GENMASK_ULL(7, 0)	/* Fabric version ID */
#define FME_CAP_SOCKET_ID	BIT_ULL(8)		/* Socket ID */
#define FME_CAP_PCIE0_LINK_AVL	BIT_ULL(12)		/* PCIE0 Link */
#define FME_CAP_PCIE1_LINK_AVL	BIT_ULL(13)		/* PCIE1 Link */
#define FME_CAP_COHR_LINK_AVL	BIT_ULL(14)		/* Coherent Link */
#define FME_CAP_IOMMU_AVL	BIT_ULL(16)		/* IOMMU available */
#define FME_CAP_NUM_PORTS	GENMASK_ULL(19, 17)	/* Number of ports */
#define FME_CAP_ADDR_WIDTH	GENMASK_ULL(29, 24)	/* Address bus width */
#define FME_CAP_CACHE_SIZE	GENMASK_ULL(43, 32)	/* cache size in KB */
#define FME_CAP_CACHE_ASSOC	GENMASK_ULL(47, 44)	/* Associativity */

/* FME Port Offset Register Bitfield */
/* Offset to port device feature header */
#define FME_PORT_OFST_DFH_OFST	GENMASK_ULL(23, 0)
/* PCI Bar ID for this port */
#define FME_PORT_OFST_BAR_ID	GENMASK_ULL(34, 32)
/* AFU MMIO access permission. 1 - VF, 0 - PF. */
#define FME_PORT_OFST_ACC_CTRL	BIT_ULL(55)
#define FME_PORT_OFST_ACC_PF	0
#define FME_PORT_OFST_ACC_VF	1
#define FME_PORT_OFST_IMP	BIT_ULL(60)

/* PORT Header Register Set */
#define PORT_HDR_DFH		DFH
#define PORT_HDR_GUID_L		GUID_L
#define PORT_HDR_GUID_H		GUID_H
#define PORT_HDR_NEXT_AFU	NEXT_AFU
#define PORT_HDR_CAP		0x30
#define PORT_HDR_CTRL		0x38

/* Port Capability Register Bitfield */
#define PORT_CAP_PORT_NUM	GENMASK_ULL(1, 0)	/* ID of this port */
#define PORT_CAP_MMIO_SIZE	GENMASK_ULL(23, 8)	/* MMIO size in KB */
#define PORT_CAP_SUPP_INT_NUM	GENMASK_ULL(35, 32)	/* Interrupts num */

/* Port Control Register Bitfield */
#define PORT_CTRL_SFTRST	BIT_ULL(0)		/* Port soft reset */
/* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/
#define PORT_CTRL_LATENCY	BIT_ULL(2)
#define PORT_CTRL_SFTRST_ACK	BIT_ULL(4)		/* HW ack for reset */

/**
 * struct dfl_feature - sub feature of the feature devices
 *
 * @id: sub feature id.
 * @resource_index: each sub feature has one mmio resource for its registers.
 *		    this index is used to find its mmio resource from the
 *		    feature dev (platform device)'s reources.
 * @ioaddr: mapped mmio resource address.
 */
struct dfl_feature {
	u64 id;
	int resource_index;
	void __iomem *ioaddr;
};

/**
 * struct dfl_feature_platform_data - platform data for feature devices
 *
 * @node: node to link feature devs to container device's port_dev_list.
 * @lock: mutex to protect platform data.
 * @dev: ptr to platform device linked with this platform data.
 * @dfl_cdev: ptr to container device.
 * @disable_count: count for port disable.
 * @num: number for sub features.
 * @features: sub features of this feature dev.
 */
struct dfl_feature_platform_data {
	struct list_head node;
	struct mutex lock;
	struct platform_device *dev;
	struct dfl_fpga_cdev *dfl_cdev;
	unsigned int disable_count;

	int num;
	struct dfl_feature features[0];
};

#define DFL_FPGA_FEATURE_DEV_FME		"dfl-fme"
#define DFL_FPGA_FEATURE_DEV_PORT		"dfl-port"

static inline int dfl_feature_platform_data_size(const int num)
{
	return sizeof(struct dfl_feature_platform_data) +
		num * sizeof(struct dfl_feature);
}

#define dfl_fpga_dev_for_each_feature(pdata, feature)			    \
	for ((feature) = (pdata)->features;				    \
	   (feature) < (pdata)->features + (pdata)->num; (feature)++)

static inline
struct dfl_feature *dfl_get_feature_by_id(struct device *dev, u64 id)
{
	struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
	struct dfl_feature *feature;

	dfl_fpga_dev_for_each_feature(pdata, feature)
		if (feature->id == id)
			return feature;

	return NULL;
}

static inline
void __iomem *dfl_get_feature_ioaddr_by_id(struct device *dev, u64 id)
{
	struct dfl_feature *feature = dfl_get_feature_by_id(dev, id);

	if (feature && feature->ioaddr)
		return feature->ioaddr;

	WARN_ON(1);
	return NULL;
}

static inline bool dfl_feature_is_fme(void __iomem *base)
{
	u64 v = readq(base + DFH);

	return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
		(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME);
}

static inline bool dfl_feature_is_port(void __iomem *base)
{
	u64 v = readq(base + DFH);

	return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
		(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);
}

/**
 * struct dfl_fpga_enum_info - DFL FPGA enumeration information
 *
 * @dev: parent device.
 * @dfls: list of device feature lists.
 */
struct dfl_fpga_enum_info {
	struct device *dev;
	struct list_head dfls;
};

/**
 * struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info
 *
 * @start: base address of this device feature list.
 * @len: size of this device feature list.
 * @ioaddr: mapped base address of this device feature list.
 * @node: node in list of device feature lists.
 */
struct dfl_fpga_enum_dfl {
	resource_size_t start;
	resource_size_t len;

	void __iomem *ioaddr;

	struct list_head node;
};

struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev);
int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
			       resource_size_t start, resource_size_t len,
			       void __iomem *ioaddr);
void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info);

/**
 * struct dfl_fpga_cdev - container device of DFL based FPGA
 *
 * @parent: parent device of this container device.
 * @region: base fpga region.
 * @fme_dev: FME feature device under this container device.
 * @lock: mutex lock to protect the port device list.
 * @port_dev_list: list of all port feature devices under this container device.
 */
struct dfl_fpga_cdev {
	struct device *parent;
	struct fpga_region *region;
	struct device *fme_dev;
	struct mutex lock;
	struct list_head port_dev_list;
};

struct dfl_fpga_cdev *
dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info);
void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev);

#endif /* __FPGA_DFL_H */
Commit	Line	Data
543be3d8 WH	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Driver Header File for FPGA Device Feature List (DFL) Support
	4	*
	5	* Copyright (C) 2017-2018 Intel Corporation, Inc.
	6	*
	7	* Authors:
	8	* Kang Luwei <luwei.kang@intel.com>
	9	* Zhang Yi <yi.z.zhang@intel.com>
	10	* Wu Hao <hao.wu@intel.com>
	11	* Xiao Guangrong <guangrong.xiao@linux.intel.com>
	12	*/
	13
	14	#ifndef __FPGA_DFL_H
	15	#define __FPGA_DFL_H
	16
	17	#include <linux/bitfield.h>
	18	#include <linux/delay.h>
	19	#include <linux/fs.h>
	20	#include <linux/iopoll.h>
	21	#include <linux/io-64-nonatomic-lo-hi.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/slab.h>
	24	#include <linux/uuid.h>
	25	#include <linux/fpga/fpga-region.h>
	26
	27	/* maximum supported number of ports */
	28	#define MAX_DFL_FPGA_PORT_NUM 4
	29	/* plus one for fme device */
	30	#define MAX_DFL_FEATURE_DEV_NUM (MAX_DFL_FPGA_PORT_NUM + 1)
	31
	32	/* Reserved 0x0 for Header Group Register and 0xff for AFU */
	33	#define FEATURE_ID_FIU_HEADER 0x0
	34	#define FEATURE_ID_AFU 0xff
	35
	36	#define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
	37	#define FME_FEATURE_ID_THERMAL_MGMT 0x1
	38	#define FME_FEATURE_ID_POWER_MGMT 0x2
	39	#define FME_FEATURE_ID_GLOBAL_IPERF 0x3
	40	#define FME_FEATURE_ID_GLOBAL_ERR 0x4
	41	#define FME_FEATURE_ID_PR_MGMT 0x5
	42	#define FME_FEATURE_ID_HSSI 0x6
	43	#define FME_FEATURE_ID_GLOBAL_DPERF 0x7
	44
	45	#define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
	46	#define PORT_FEATURE_ID_AFU FEATURE_ID_AFU
	47	#define PORT_FEATURE_ID_ERROR 0x10
	48	#define PORT_FEATURE_ID_UMSG 0x11
	49	#define PORT_FEATURE_ID_UINT 0x12
	50	#define PORT_FEATURE_ID_STP 0x13
	51
	52	/*
	53	* Device Feature Header Register Set
	54	*
	55	* For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers.
	56	* For AFUs, they have DFH + GUID as common header registers.
	57	* For private features, they only have DFH register as common header.
	58	*/
	59	#define DFH 0x0
	60	#define GUID_L 0x8
	61	#define GUID_H 0x10
	62	#define NEXT_AFU 0x18
	63
	64	#define DFH_SIZE 0x8
65
66	/* Device Feature Header Register Bitfield */
67	#define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */
68	#define DFH_ID_FIU_FME 0
69	#define DFH_ID_FIU_PORT 1
70	#define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */
71	#define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */
72	#define DFH_EOL BIT_ULL(40) /* End of list */
73	#define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */
74	#define DFH_TYPE_AFU 1
75	#define DFH_TYPE_PRIVATE 3
76	#define DFH_TYPE_FIU 4
77
78	/* Next AFU Register Bitfield */
79	#define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */
80
81	/* FME Header Register Set */
82	#define FME_HDR_DFH DFH
83	#define FME_HDR_GUID_L GUID_L
84	#define FME_HDR_GUID_H GUID_H
85	#define FME_HDR_NEXT_AFU NEXT_AFU
86	#define FME_HDR_CAP 0x30
87	#define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8))
88	#define FME_HDR_BITSTREAM_ID 0x60
89	#define FME_HDR_BITSTREAM_MD 0x68
90
91	/* FME Fab Capability Register Bitfield */
92	#define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */
93	#define FME_CAP_SOCKET_ID BIT_ULL(8) /* Socket ID */
94	#define FME_CAP_PCIE0_LINK_AVL BIT_ULL(12) /* PCIE0 Link */
95	#define FME_CAP_PCIE1_LINK_AVL BIT_ULL(13) /* PCIE1 Link */
96	#define FME_CAP_COHR_LINK_AVL BIT_ULL(14) /* Coherent Link */
97	#define FME_CAP_IOMMU_AVL BIT_ULL(16) /* IOMMU available */
98	#define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */
99	#define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */
100	#define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */
101	#define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */
102
103	/* FME Port Offset Register Bitfield */
104	/* Offset to port device feature header */
105	#define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0)
106	/* PCI Bar ID for this port */
107	#define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32)
108	/* AFU MMIO access permission. 1 - VF, 0 - PF. */
109	#define FME_PORT_OFST_ACC_CTRL BIT_ULL(55)
110	#define FME_PORT_OFST_ACC_PF 0
111	#define FME_PORT_OFST_ACC_VF 1
112	#define FME_PORT_OFST_IMP BIT_ULL(60)
113
114	/* PORT Header Register Set */
115	#define PORT_HDR_DFH DFH
116	#define PORT_HDR_GUID_L GUID_L
117	#define PORT_HDR_GUID_H GUID_H
118	#define PORT_HDR_NEXT_AFU NEXT_AFU
119	#define PORT_HDR_CAP 0x30
120	#define PORT_HDR_CTRL 0x38
121
122	/* Port Capability Register Bitfield */
123	#define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */
124	#define PORT_CAP_MMIO_SIZE GENMASK_ULL(23, 8) /* MMIO size in KB */
125	#define PORT_CAP_SUPP_INT_NUM GENMASK_ULL(35, 32) /* Interrupts num */
126
127	/* Port Control Register Bitfield */
128	#define PORT_CTRL_SFTRST BIT_ULL(0) /* Port soft reset */
129	/* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/
130	#define PORT_CTRL_LATENCY BIT_ULL(2)
131	#define PORT_CTRL_SFTRST_ACK BIT_ULL(4) /* HW ack for reset */
132
133	/**
134	* struct dfl_feature - sub feature of the feature devices
135	*
136	* @id: sub feature id.
137	* @resource_index: each sub feature has one mmio resource for its registers.
138	* this index is used to find its mmio resource from the
139	* feature dev (platform device)'s reources.
140	* @ioaddr: mapped mmio resource address.
141	*/
142	struct dfl_feature {
143	u64 id;
144	int resource_index;
145	void __iomem *ioaddr;
146	};
147
148	/**
149	* struct dfl_feature_platform_data - platform data for feature devices
150	*
151	* @node: node to link feature devs to container device's port_dev_list.
152	* @lock: mutex to protect platform data.
153	* @dev: ptr to platform device linked with this platform data.
154	* @dfl_cdev: ptr to container device.
155	* @disable_count: count for port disable.
156	* @num: number for sub features.
157	* @features: sub features of this feature dev.
158	*/
159	struct dfl_feature_platform_data {
160	struct list_head node;
161	struct mutex lock;
162	struct platform_device *dev;
163	struct dfl_fpga_cdev *dfl_cdev;
164	unsigned int disable_count;
165
166	int num;
167	struct dfl_feature features[0];
168	};
169
170	#define DFL_FPGA_FEATURE_DEV_FME "dfl-fme"
171	#define DFL_FPGA_FEATURE_DEV_PORT "dfl-port"
172
173	static inline int dfl_feature_platform_data_size(const int num)
174	{
175	return sizeof(struct dfl_feature_platform_data) +
176	num * sizeof(struct dfl_feature);
177	}
178
179	#define dfl_fpga_dev_for_each_feature(pdata, feature) \
180	for ((feature) = (pdata)->features; \
181	(feature) < (pdata)->features + (pdata)->num; (feature)++)
182
183	static inline
184	struct dfl_feature dfl_get_feature_by_id(struct device dev, u64 id)
185	{
186	struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
187	struct dfl_feature *feature;
188
189	dfl_fpga_dev_for_each_feature(pdata, feature)
190	if (feature->id == id)
191	return feature;
192
193	return NULL;
194	}
195
196	static inline
197	void __iomem dfl_get_feature_ioaddr_by_id(struct device dev, u64 id)
198	{
199	struct dfl_feature *feature = dfl_get_feature_by_id(dev, id);
200
201	if (feature && feature->ioaddr)
202	return feature->ioaddr;
203
204	WARN_ON(1);
205	return NULL;
206	}
207
208	static inline bool dfl_feature_is_fme(void __iomem *base)
209	{
210	u64 v = readq(base + DFH);
211
212	return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
213	(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME);
214	}
215
216	static inline bool dfl_feature_is_port(void __iomem *base)
217	{
218	u64 v = readq(base + DFH);
219
220	return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
221	(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);
222	}
223
224	/**
225	* struct dfl_fpga_enum_info - DFL FPGA enumeration information
226	*
227	* @dev: parent device.
228	* @dfls: list of device feature lists.
229	*/
230	struct dfl_fpga_enum_info {
231	struct device *dev;
232	struct list_head dfls;
233	};
234
235	/**
236	* struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info
237	*
238	* @start: base address of this device feature list.
239	* @len: size of this device feature list.
240	* @ioaddr: mapped base address of this device feature list.
241	* @node: node in list of device feature lists.
242	*/
243	struct dfl_fpga_enum_dfl {
244	resource_size_t start;
245	resource_size_t len;
246
247	void __iomem *ioaddr;
248
249	struct list_head node;
250	};
251
252	struct dfl_fpga_enum_info dfl_fpga_enum_info_alloc(struct device dev);
253	int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
254	resource_size_t start, resource_size_t len,
255	void __iomem *ioaddr);
256	void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info);
257
258	/**
259	* struct dfl_fpga_cdev - container device of DFL based FPGA
260	*
261	* @parent: parent device of this container device.
262	* @region: base fpga region.
263	* @fme_dev: FME feature device under this container device.
264	* @lock: mutex lock to protect the port device list.
265	* @port_dev_list: list of all port feature devices under this container device.
266	*/
267	struct dfl_fpga_cdev {
268	struct device *parent;
269	struct fpga_region *region;
270	struct device *fme_dev;
271	struct mutex lock;
272	struct list_head port_dev_list;
273	};
274
275	struct dfl_fpga_cdev *
276	dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info);
277	void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev);
278
279	#endif /* __FPGA_DFL_H */