[linux-block.git] / drivers / fpga / dfl.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Driver Header File for FPGA Device Feature List (DFL) Support
 *
 * Copyright (C) 2017-2018 Intel Corporation, Inc.
 *
 * Authors:
 *   Kang Luwei <luwei.kang@intel.com>
 *   Zhang Yi <yi.z.zhang@intel.com>
 *   Wu Hao <hao.wu@intel.com>
 *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
 */

#ifndef __FPGA_DFL_H
#define __FPGA_DFL_H

#include <linux/bitfield.h>
#include <linux/cdev.h>
#include <linux/delay.h>
#include <linux/fs.h>
#include <linux/iopoll.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/uuid.h>
#include <linux/fpga/fpga-region.h>

/* maximum supported number of ports */
#define MAX_DFL_FPGA_PORT_NUM 4
/* plus one for fme device */
#define MAX_DFL_FEATURE_DEV_NUM    (MAX_DFL_FPGA_PORT_NUM + 1)

/* Reserved 0xfe for Header Group Register and 0xff for AFU */
#define FEATURE_ID_FIU_HEADER		0xfe
#define FEATURE_ID_AFU			0xff

#define FME_FEATURE_ID_HEADER		FEATURE_ID_FIU_HEADER
#define FME_FEATURE_ID_THERMAL_MGMT	0x1
#define FME_FEATURE_ID_POWER_MGMT	0x2
#define FME_FEATURE_ID_GLOBAL_IPERF	0x3
#define FME_FEATURE_ID_GLOBAL_ERR	0x4
#define FME_FEATURE_ID_PR_MGMT		0x5
#define FME_FEATURE_ID_HSSI		0x6
#define FME_FEATURE_ID_GLOBAL_DPERF	0x7

#define PORT_FEATURE_ID_HEADER		FEATURE_ID_FIU_HEADER
#define PORT_FEATURE_ID_AFU		FEATURE_ID_AFU
#define PORT_FEATURE_ID_ERROR		0x10
#define PORT_FEATURE_ID_UMSG		0x11
#define PORT_FEATURE_ID_UINT		0x12
#define PORT_FEATURE_ID_STP		0x13

/*
 * Device Feature Header Register Set
 *
 * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers.
 * For AFUs, they have DFH + GUID as common header registers.
 * For private features, they only have DFH register as common header.
 */
#define DFH			0x0
#define GUID_L			0x8
#define GUID_H			0x10
#define NEXT_AFU		0x18

#define DFH_SIZE		0x8

/* Device Feature Header Register Bitfield */
#define DFH_ID			GENMASK_ULL(11, 0)	/* Feature ID */
#define DFH_ID_FIU_FME		0
#define DFH_ID_FIU_PORT		1
#define DFH_REVISION		GENMASK_ULL(15, 12)	/* Feature revision */
#define DFH_NEXT_HDR_OFST	GENMASK_ULL(39, 16)	/* Offset to next DFH */
#define DFH_EOL			BIT_ULL(40)		/* End of list */
#define DFH_TYPE		GENMASK_ULL(63, 60)	/* Feature type */
#define DFH_TYPE_AFU		1
#define DFH_TYPE_PRIVATE	3
#define DFH_TYPE_FIU		4

/* Next AFU Register Bitfield */
#define NEXT_AFU_NEXT_DFH_OFST	GENMASK_ULL(23, 0)	/* Offset to next AFU */

/* FME Header Register Set */
#define FME_HDR_DFH		DFH
#define FME_HDR_GUID_L		GUID_L
#define FME_HDR_GUID_H		GUID_H
#define FME_HDR_NEXT_AFU	NEXT_AFU
#define FME_HDR_CAP		0x30
#define FME_HDR_PORT_OFST(n)	(0x38 + ((n) * 0x8))
#define FME_HDR_BITSTREAM_ID	0x60
#define FME_HDR_BITSTREAM_MD	0x68

/* FME Fab Capability Register Bitfield */
#define FME_CAP_FABRIC_VERID	GENMASK_ULL(7, 0)	/* Fabric version ID */
#define FME_CAP_SOCKET_ID	BIT_ULL(8)		/* Socket ID */
#define FME_CAP_PCIE0_LINK_AVL	BIT_ULL(12)		/* PCIE0 Link */
#define FME_CAP_PCIE1_LINK_AVL	BIT_ULL(13)		/* PCIE1 Link */
#define FME_CAP_COHR_LINK_AVL	BIT_ULL(14)		/* Coherent Link */
#define FME_CAP_IOMMU_AVL	BIT_ULL(16)		/* IOMMU available */
#define FME_CAP_NUM_PORTS	GENMASK_ULL(19, 17)	/* Number of ports */
#define FME_CAP_ADDR_WIDTH	GENMASK_ULL(29, 24)	/* Address bus width */
#define FME_CAP_CACHE_SIZE	GENMASK_ULL(43, 32)	/* cache size in KB */
#define FME_CAP_CACHE_ASSOC	GENMASK_ULL(47, 44)	/* Associativity */

/* FME Port Offset Register Bitfield */
/* Offset to port device feature header */
#define FME_PORT_OFST_DFH_OFST	GENMASK_ULL(23, 0)
/* PCI Bar ID for this port */
#define FME_PORT_OFST_BAR_ID	GENMASK_ULL(34, 32)
/* AFU MMIO access permission. 1 - VF, 0 - PF. */
#define FME_PORT_OFST_ACC_CTRL	BIT_ULL(55)
#define FME_PORT_OFST_ACC_PF	0
#define FME_PORT_OFST_ACC_VF	1
#define FME_PORT_OFST_IMP	BIT_ULL(60)

/* PORT Header Register Set */
#define PORT_HDR_DFH		DFH
#define PORT_HDR_GUID_L		GUID_L
#define PORT_HDR_GUID_H		GUID_H
#define PORT_HDR_NEXT_AFU	NEXT_AFU
#define PORT_HDR_CAP		0x30
#define PORT_HDR_CTRL		0x38
#define PORT_HDR_STS		0x40
#define PORT_HDR_USRCLK_CMD0	0x50
#define PORT_HDR_USRCLK_CMD1	0x58
#define PORT_HDR_USRCLK_STS0	0x60
#define PORT_HDR_USRCLK_STS1	0x68

/* Port Capability Register Bitfield */
#define PORT_CAP_PORT_NUM	GENMASK_ULL(1, 0)	/* ID of this port */
#define PORT_CAP_MMIO_SIZE	GENMASK_ULL(23, 8)	/* MMIO size in KB */
#define PORT_CAP_SUPP_INT_NUM	GENMASK_ULL(35, 32)	/* Interrupts num */

/* Port Control Register Bitfield */
#define PORT_CTRL_SFTRST	BIT_ULL(0)		/* Port soft reset */
/* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/
#define PORT_CTRL_LATENCY	BIT_ULL(2)
#define PORT_CTRL_SFTRST_ACK	BIT_ULL(4)		/* HW ack for reset */

/* Port Status Register Bitfield */
#define PORT_STS_AP2_EVT	BIT_ULL(13)		/* AP2 event detected */
#define PORT_STS_AP1_EVT	BIT_ULL(12)		/* AP1 event detected */
#define PORT_STS_PWR_STATE	GENMASK_ULL(11, 8)	/* AFU power states */
#define PORT_STS_PWR_STATE_NORM 0
#define PORT_STS_PWR_STATE_AP1	1			/* 50% throttling */
#define PORT_STS_PWR_STATE_AP2	2			/* 90% throttling */
#define PORT_STS_PWR_STATE_AP6	6			/* 100% throttling */

/**
 * struct dfl_fpga_port_ops - port ops
 *
 * @name: name of this port ops, to match with port platform device.
 * @owner: pointer to the module which owns this port ops.
 * @node: node to link port ops to global list.
 * @get_id: get port id from hardware.
 * @enable_set: enable/disable the port.
 */
struct dfl_fpga_port_ops {
	const char *name;
	struct module *owner;
	struct list_head node;
	int (*get_id)(struct platform_device *pdev);
	int (*enable_set)(struct platform_device *pdev, bool enable);
};

void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops);
void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops);
struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev);
void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops);
int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id);

/**
 * struct dfl_feature_id - dfl private feature id
 *
 * @id: unique dfl private feature id.
 */
struct dfl_feature_id {
	u64 id;
};

/**
 * struct dfl_feature_driver - dfl private feature driver
 *
 * @id_table: id_table for dfl private features supported by this driver.
 * @ops: ops of this dfl private feature driver.
 */
struct dfl_feature_driver {
	const struct dfl_feature_id *id_table;
	const struct dfl_feature_ops *ops;
};

/**
 * struct dfl_feature - sub feature of the feature devices
 *
 * @id: sub feature id.
 * @resource_index: each sub feature has one mmio resource for its registers.
 *		    this index is used to find its mmio resource from the
 *		    feature dev (platform device)'s reources.
 * @ioaddr: mapped mmio resource address.
 * @ops: ops of this sub feature.
 */
struct dfl_feature {
	u64 id;
	int resource_index;
	void __iomem *ioaddr;
	const struct dfl_feature_ops *ops;
};

#define DEV_STATUS_IN_USE	0

#define FEATURE_DEV_ID_UNUSED	(-1)

/**
 * struct dfl_feature_platform_data - platform data for feature devices
 *
 * @node: node to link feature devs to container device's port_dev_list.
 * @lock: mutex to protect platform data.
 * @cdev: cdev of feature dev.
 * @dev: ptr to platform device linked with this platform data.
 * @dfl_cdev: ptr to container device.
 * @id: id used for this feature device.
 * @disable_count: count for port disable.
 * @num: number for sub features.
 * @dev_status: dev status (e.g. DEV_STATUS_IN_USE).
 * @private: ptr to feature dev private data.
 * @features: sub features of this feature dev.
 */
struct dfl_feature_platform_data {
	struct list_head node;
	struct mutex lock;
	struct cdev cdev;
	struct platform_device *dev;
	struct dfl_fpga_cdev *dfl_cdev;
	int id;
	unsigned int disable_count;
	unsigned long dev_status;
	void *private;
	int num;
	struct dfl_feature features[0];
};

static inline
int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata)
{
	/* Test and set IN_USE flags to ensure file is exclusively used */
	if (test_and_set_bit_lock(DEV_STATUS_IN_USE, &pdata->dev_status))
		return -EBUSY;

	return 0;
}

static inline
void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata)
{
	clear_bit_unlock(DEV_STATUS_IN_USE, &pdata->dev_status);
}

static inline
void dfl_fpga_pdata_set_private(struct dfl_feature_platform_data *pdata,
				void *private)
{
	pdata->private = private;
}

static inline
void *dfl_fpga_pdata_get_private(struct dfl_feature_platform_data *pdata)
{
	return pdata->private;
}

struct dfl_feature_ops {
	int (*init)(struct platform_device *pdev, struct dfl_feature *feature);
	void (*uinit)(struct platform_device *pdev,
		      struct dfl_feature *feature);
	long (*ioctl)(struct platform_device *pdev, struct dfl_feature *feature,
		      unsigned int cmd, unsigned long arg);
};

#define DFL_FPGA_FEATURE_DEV_FME		"dfl-fme"
#define DFL_FPGA_FEATURE_DEV_PORT		"dfl-port"

static inline int dfl_feature_platform_data_size(const int num)
{
	return sizeof(struct dfl_feature_platform_data) +
		num * sizeof(struct dfl_feature);
}

void dfl_fpga_dev_feature_uinit(struct platform_device *pdev);
int dfl_fpga_dev_feature_init(struct platform_device *pdev,
			      struct dfl_feature_driver *feature_drvs);

int dfl_fpga_dev_ops_register(struct platform_device *pdev,
			      const struct file_operations *fops,
			      struct module *owner);
void dfl_fpga_dev_ops_unregister(struct platform_device *pdev);

static inline
struct platform_device *dfl_fpga_inode_to_feature_dev(struct inode *inode)
{
	struct dfl_feature_platform_data *pdata;

	pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data,
			     cdev);
	return pdata->dev;
}

#define dfl_fpga_dev_for_each_feature(pdata, feature)			    \
	for ((feature) = (pdata)->features;				    \
	   (feature) < (pdata)->features + (pdata)->num; (feature)++)

static inline
struct dfl_feature *dfl_get_feature_by_id(struct device *dev, u64 id)
{
	struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
	struct dfl_feature *feature;

	dfl_fpga_dev_for_each_feature(pdata, feature)
		if (feature->id == id)
			return feature;

	return NULL;
}

static inline
void __iomem *dfl_get_feature_ioaddr_by_id(struct device *dev, u64 id)
{
	struct dfl_feature *feature = dfl_get_feature_by_id(dev, id);

	if (feature && feature->ioaddr)
		return feature->ioaddr;

	WARN_ON(1);
	return NULL;
}

static inline bool is_dfl_feature_present(struct device *dev, u64 id)
{
	return !!dfl_get_feature_ioaddr_by_id(dev, id);
}

static inline
struct device *dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data *pdata)
{
	return pdata->dev->dev.parent->parent;
}

static inline bool dfl_feature_is_fme(void __iomem *base)
{
	u64 v = readq(base + DFH);

	return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
		(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME);
}

static inline bool dfl_feature_is_port(void __iomem *base)
{
	u64 v = readq(base + DFH);

	return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
		(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);
}

static inline u8 dfl_feature_revision(void __iomem *base)
{
	return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH));
}

/**
 * struct dfl_fpga_enum_info - DFL FPGA enumeration information
 *
 * @dev: parent device.
 * @dfls: list of device feature lists.
 */
struct dfl_fpga_enum_info {
	struct device *dev;
	struct list_head dfls;
};

/**
 * struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info
 *
 * @start: base address of this device feature list.
 * @len: size of this device feature list.
 * @ioaddr: mapped base address of this device feature list.
 * @node: node in list of device feature lists.
 */
struct dfl_fpga_enum_dfl {
	resource_size_t start;
	resource_size_t len;

	void __iomem *ioaddr;

	struct list_head node;
};

struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev);
int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
			       resource_size_t start, resource_size_t len,
			       void __iomem *ioaddr);
void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info);

/**
 * struct dfl_fpga_cdev - container device of DFL based FPGA
 *
 * @parent: parent device of this container device.
 * @region: base fpga region.
 * @fme_dev: FME feature device under this container device.
 * @lock: mutex lock to protect the port device list.
 * @port_dev_list: list of all port feature devices under this container device.
 * @released_port_num: released port number under this container device.
 */
struct dfl_fpga_cdev {
	struct device *parent;
	struct fpga_region *region;
	struct device *fme_dev;
	struct mutex lock;
	struct list_head port_dev_list;
	int released_port_num;
};

struct dfl_fpga_cdev *
dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info);
void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev);

/*
 * need to drop the device reference with put_device() after use port platform
 * device returned by __dfl_fpga_cdev_find_port and dfl_fpga_cdev_find_port
 * functions.
 */
struct platform_device *
__dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
			  int (*match)(struct platform_device *, void *));

static inline struct platform_device *
dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
			int (*match)(struct platform_device *, void *))
{
	struct platform_device *pdev;

	mutex_lock(&cdev->lock);
	pdev = __dfl_fpga_cdev_find_port(cdev, data, match);
	mutex_unlock(&cdev->lock);

	return pdev;
}

int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id);
int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id);
void dfl_fpga_cdev_config_ports_pf(struct dfl_fpga_cdev *cdev);
int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vf);
#endif /* __FPGA_DFL_H */
Commit	Line	Data
543be3d8 WH	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Driver Header File for FPGA Device Feature List (DFL) Support
	4	*
	5	* Copyright (C) 2017-2018 Intel Corporation, Inc.
	6	*
	7	* Authors:
	8	* Kang Luwei <luwei.kang@intel.com>
	9	* Zhang Yi <yi.z.zhang@intel.com>
	10	* Wu Hao <hao.wu@intel.com>
	11	* Xiao Guangrong <guangrong.xiao@linux.intel.com>
	12	*/
	13
	14	#ifndef __FPGA_DFL_H
	15	#define __FPGA_DFL_H
	16
	17	#include <linux/bitfield.h>
b16c5147	18	#include <linux/cdev.h>
543be3d8 WH	19	#include <linux/delay.h>
	20	#include <linux/fs.h>
	21	#include <linux/iopoll.h>
	22	#include <linux/io-64-nonatomic-lo-hi.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/slab.h>
	25	#include <linux/uuid.h>
	26	#include <linux/fpga/fpga-region.h>
	27
	28	/* maximum supported number of ports */
	29	#define MAX_DFL_FPGA_PORT_NUM 4
	30	/* plus one for fme device */
	31	#define MAX_DFL_FEATURE_DEV_NUM (MAX_DFL_FPGA_PORT_NUM + 1)
	32
15bbb300 WH	33	/* Reserved 0xfe for Header Group Register and 0xff for AFU */
15bbb300 WH	34	#define FEATURE_ID_FIU_HEADER 0xfe
543be3d8 WH	35	#define FEATURE_ID_AFU 0xff
	36
	37	#define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
	38	#define FME_FEATURE_ID_THERMAL_MGMT 0x1
	39	#define FME_FEATURE_ID_POWER_MGMT 0x2
	40	#define FME_FEATURE_ID_GLOBAL_IPERF 0x3
	41	#define FME_FEATURE_ID_GLOBAL_ERR 0x4
	42	#define FME_FEATURE_ID_PR_MGMT 0x5
	43	#define FME_FEATURE_ID_HSSI 0x6
	44	#define FME_FEATURE_ID_GLOBAL_DPERF 0x7
	45
	46	#define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
	47	#define PORT_FEATURE_ID_AFU FEATURE_ID_AFU
	48	#define PORT_FEATURE_ID_ERROR 0x10
	49	#define PORT_FEATURE_ID_UMSG 0x11
	50	#define PORT_FEATURE_ID_UINT 0x12
	51	#define PORT_FEATURE_ID_STP 0x13
	52
	53	/*
	54	* Device Feature Header Register Set
	55	*
	56	* For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers.
	57	* For AFUs, they have DFH + GUID as common header registers.
	58	* For private features, they only have DFH register as common header.
	59	*/
	60	#define DFH 0x0
	61	#define GUID_L 0x8
	62	#define GUID_H 0x10
	63	#define NEXT_AFU 0x18
	64
	65	#define DFH_SIZE 0x8
	66
	67	/* Device Feature Header Register Bitfield */
	68	#define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */
	69	#define DFH_ID_FIU_FME 0
	70	#define DFH_ID_FIU_PORT 1
	71	#define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */
	72	#define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */
	73	#define DFH_EOL BIT_ULL(40) /* End of list */
	74	#define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */
	75	#define DFH_TYPE_AFU 1
	76	#define DFH_TYPE_PRIVATE 3
	77	#define DFH_TYPE_FIU 4
	78
	79	/* Next AFU Register Bitfield */
	80	#define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */
	81
	82	/* FME Header Register Set */
	83	#define FME_HDR_DFH DFH
	84	#define FME_HDR_GUID_L GUID_L
	85	#define FME_HDR_GUID_H GUID_H
	86	#define FME_HDR_NEXT_AFU NEXT_AFU
	87	#define FME_HDR_CAP 0x30
	88	#define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8))
	89	#define FME_HDR_BITSTREAM_ID 0x60
	90	#define FME_HDR_BITSTREAM_MD 0x68
	91
	92	/* FME Fab Capability Register Bitfield */
	93	#define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */
	94	#define FME_CAP_SOCKET_ID BIT_ULL(8) /* Socket ID */
	95	#define FME_CAP_PCIE0_LINK_AVL BIT_ULL(12) /* PCIE0 Link */
	96	#define FME_CAP_PCIE1_LINK_AVL BIT_ULL(13) /* PCIE1 Link */
	97	#define FME_CAP_COHR_LINK_AVL BIT_ULL(14) /* Coherent Link */
	98	#define FME_CAP_IOMMU_AVL BIT_ULL(16) /* IOMMU available */
99	#define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */
100	#define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */
101	#define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */
102	#define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */
103
104	/* FME Port Offset Register Bitfield */
105	/* Offset to port device feature header */
106	#define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0)
107	/* PCI Bar ID for this port */
108	#define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32)
109	/* AFU MMIO access permission. 1 - VF, 0 - PF. */
110	#define FME_PORT_OFST_ACC_CTRL BIT_ULL(55)
111	#define FME_PORT_OFST_ACC_PF 0
112	#define FME_PORT_OFST_ACC_VF 1
113	#define FME_PORT_OFST_IMP BIT_ULL(60)
114
115	/* PORT Header Register Set */
116	#define PORT_HDR_DFH DFH
117	#define PORT_HDR_GUID_L GUID_L
118	#define PORT_HDR_GUID_H GUID_H
119	#define PORT_HDR_NEXT_AFU NEXT_AFU
120	#define PORT_HDR_CAP 0x30
121	#define PORT_HDR_CTRL 0x38
d2ad5ac1	122	#define PORT_HDR_STS 0x40
f09991ad WH	123	#define PORT_HDR_USRCLK_CMD0 0x50
	124	#define PORT_HDR_USRCLK_CMD1 0x58
	125	#define PORT_HDR_USRCLK_STS0 0x60
	126	#define PORT_HDR_USRCLK_STS1 0x68
543be3d8 WH	127
	128	/* Port Capability Register Bitfield */
	129	#define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */
	130	#define PORT_CAP_MMIO_SIZE GENMASK_ULL(23, 8) /* MMIO size in KB */
	131	#define PORT_CAP_SUPP_INT_NUM GENMASK_ULL(35, 32) /* Interrupts num */
	132
	133	/* Port Control Register Bitfield */
	134	#define PORT_CTRL_SFTRST BIT_ULL(0) /* Port soft reset */
	135	/* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/
	136	#define PORT_CTRL_LATENCY BIT_ULL(2)
	137	#define PORT_CTRL_SFTRST_ACK BIT_ULL(4) /* HW ack for reset */
d2ad5ac1 WH	138
	139	/* Port Status Register Bitfield */
	140	#define PORT_STS_AP2_EVT BIT_ULL(13) /* AP2 event detected */
	141	#define PORT_STS_AP1_EVT BIT_ULL(12) /* AP1 event detected */
	142	#define PORT_STS_PWR_STATE GENMASK_ULL(11, 8) /* AFU power states */
	143	#define PORT_STS_PWR_STATE_NORM 0
	144	#define PORT_STS_PWR_STATE_AP1 1 /* 50% throttling */
	145	#define PORT_STS_PWR_STATE_AP2 2 /* 90% throttling */
	146	#define PORT_STS_PWR_STATE_AP6 6 /* 100% throttling */
	147
6e8fd6e4 WH	148	/**
	149	* struct dfl_fpga_port_ops - port ops
	150	*
	151	* @name: name of this port ops, to match with port platform device.
	152	* @owner: pointer to the module which owns this port ops.
	153	* @node: node to link port ops to global list.
	154	* @get_id: get port id from hardware.
	155	* @enable_set: enable/disable the port.
	156	*/
	157	struct dfl_fpga_port_ops {
	158	const char *name;
	159	struct module *owner;
	160	struct list_head node;
	161	int (get_id)(struct platform_device pdev);
	162	int (enable_set)(struct platform_device pdev, bool enable);
	163	};
	164
	165	void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops);
	166	void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops);
	167	struct dfl_fpga_port_ops dfl_fpga_port_ops_get(struct platform_device pdev);
	168	void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops);
d06b004b	169	int dfl_fpga_check_port_id(struct platform_device pdev, void pport_id);
543be3d8	170
5b57d02a	171	/**
15bbb300	172	* struct dfl_feature_id - dfl private feature id
5b57d02a	173	*
15bbb300	174	* @id: unique dfl private feature id.
5b57d02a	175	*/
15bbb300	176	struct dfl_feature_id {
5b57d02a	177	u64 id;
15bbb300 WH	178	};
	179
	180	/**
	181	* struct dfl_feature_driver - dfl private feature driver
	182	*
	183	* @id_table: id_table for dfl private features supported by this driver.
	184	* @ops: ops of this dfl private feature driver.
	185	*/
	186	struct dfl_feature_driver {
	187	const struct dfl_feature_id *id_table;
5b57d02a XG	188	const struct dfl_feature_ops *ops;
	189	};
	190
543be3d8 WH	191	/**
	192	* struct dfl_feature - sub feature of the feature devices
	193	*
	194	* @id: sub feature id.
	195	* @resource_index: each sub feature has one mmio resource for its registers.
	196	* this index is used to find its mmio resource from the
	197	* feature dev (platform device)'s reources.
	198	* @ioaddr: mapped mmio resource address.
5b57d02a	199	* @ops: ops of this sub feature.
543be3d8 WH	200	*/
	201	struct dfl_feature {
	202	u64 id;
	203	int resource_index;
	204	void __iomem *ioaddr;
5b57d02a	205	const struct dfl_feature_ops *ops;
543be3d8 WH	206	};
543be3d8 WH	207
5b57d02a XG	208	#define DEV_STATUS_IN_USE 0
5b57d02a XG	209
69bb18dd WH	210	#define FEATURE_DEV_ID_UNUSED (-1)
69bb18dd WH	211
543be3d8 WH	212	/**
	213	* struct dfl_feature_platform_data - platform data for feature devices
	214	*
	215	* @node: node to link feature devs to container device's port_dev_list.
	216	* @lock: mutex to protect platform data.
b16c5147	217	* @cdev: cdev of feature dev.
543be3d8 WH	218	* @dev: ptr to platform device linked with this platform data.
543be3d8 WH	219	* @dfl_cdev: ptr to container device.
69bb18dd	220	* @id: id used for this feature device.
543be3d8 WH	221	* @disable_count: count for port disable.
543be3d8 WH	222	* @num: number for sub features.
5b57d02a XG	223	* @dev_status: dev status (e.g. DEV_STATUS_IN_USE).
5b57d02a XG	224	* @private: ptr to feature dev private data.
543be3d8 WH	225	* @features: sub features of this feature dev.
	226	*/
	227	struct dfl_feature_platform_data {
	228	struct list_head node;
	229	struct mutex lock;
b16c5147	230	struct cdev cdev;
543be3d8 WH	231	struct platform_device *dev;
543be3d8 WH	232	struct dfl_fpga_cdev *dfl_cdev;
69bb18dd	233	int id;
543be3d8	234	unsigned int disable_count;
5b57d02a XG	235	unsigned long dev_status;
5b57d02a XG	236	void *private;
543be3d8 WH	237	int num;
	238	struct dfl_feature features[0];
	239	};
	240
5b57d02a XG	241	static inline
	242	int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata)
	243	{
	244	/* Test and set IN_USE flags to ensure file is exclusively used */
	245	if (test_and_set_bit_lock(DEV_STATUS_IN_USE, &pdata->dev_status))
	246	return -EBUSY;
	247
	248	return 0;
	249	}
	250
	251	static inline
	252	void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata)
	253	{
	254	clear_bit_unlock(DEV_STATUS_IN_USE, &pdata->dev_status);
	255	}
	256
	257	static inline
	258	void dfl_fpga_pdata_set_private(struct dfl_feature_platform_data *pdata,
	259	void *private)
	260	{
	261	pdata->private = private;
	262	}
	263
	264	static inline
	265	void dfl_fpga_pdata_get_private(struct dfl_feature_platform_data pdata)
	266	{
	267	return pdata->private;
	268	}
	269
	270	struct dfl_feature_ops {
	271	int (init)(struct platform_device pdev, struct dfl_feature *feature);
	272	void (uinit)(struct platform_device pdev,
	273	struct dfl_feature *feature);
	274	long (ioctl)(struct platform_device pdev, struct dfl_feature *feature,
	275	unsigned int cmd, unsigned long arg);
	276	};
	277
543be3d8 WH	278	#define DFL_FPGA_FEATURE_DEV_FME "dfl-fme"
	279	#define DFL_FPGA_FEATURE_DEV_PORT "dfl-port"
	280
	281	static inline int dfl_feature_platform_data_size(const int num)
	282	{
	283	return sizeof(struct dfl_feature_platform_data) +
	284	num * sizeof(struct dfl_feature);
	285	}
	286
5b57d02a XG	287	void dfl_fpga_dev_feature_uinit(struct platform_device *pdev);
	288	int dfl_fpga_dev_feature_init(struct platform_device *pdev,
	289	struct dfl_feature_driver *feature_drvs);
	290
b16c5147 WH	291	int dfl_fpga_dev_ops_register(struct platform_device *pdev,
	292	const struct file_operations *fops,
	293	struct module *owner);
	294	void dfl_fpga_dev_ops_unregister(struct platform_device *pdev);
	295
5b57d02a XG	296	static inline
	297	struct platform_device dfl_fpga_inode_to_feature_dev(struct inode inode)
	298	{
	299	struct dfl_feature_platform_data *pdata;
	300
	301	pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data,
	302	cdev);
	303	return pdata->dev;
	304	}
	305
543be3d8 WH	306	#define dfl_fpga_dev_for_each_feature(pdata, feature) \
	307	for ((feature) = (pdata)->features; \
	308	(feature) < (pdata)->features + (pdata)->num; (feature)++)
	309
	310	static inline
	311	struct dfl_feature dfl_get_feature_by_id(struct device dev, u64 id)
	312	{
	313	struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
	314	struct dfl_feature *feature;
	315
	316	dfl_fpga_dev_for_each_feature(pdata, feature)
	317	if (feature->id == id)
	318	return feature;
	319
	320	return NULL;
	321	}
	322
	323	static inline
	324	void __iomem dfl_get_feature_ioaddr_by_id(struct device dev, u64 id)
	325	{
	326	struct dfl_feature *feature = dfl_get_feature_by_id(dev, id);
	327
	328	if (feature && feature->ioaddr)
	329	return feature->ioaddr;
	330
	331	WARN_ON(1);
	332	return NULL;
	333	}
	334
5b57d02a XG	335	static inline bool is_dfl_feature_present(struct device *dev, u64 id)
	336	{
	337	return !!dfl_get_feature_ioaddr_by_id(dev, id);
	338	}
	339
	340	static inline
	341	struct device dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data pdata)
	342	{
	343	return pdata->dev->dev.parent->parent;
	344	}
	345
543be3d8 WH	346	static inline bool dfl_feature_is_fme(void __iomem *base)
	347	{
	348	u64 v = readq(base + DFH);
	349
	350	return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
	351	(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME);
	352	}
	353
	354	static inline bool dfl_feature_is_port(void __iomem *base)
	355	{
	356	u64 v = readq(base + DFH);
	357
	358	return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
	359	(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);
	360	}
	361
f09991ad WH	362	static inline u8 dfl_feature_revision(void __iomem *base)
	363	{
	364	return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH));
	365	}
	366
543be3d8 WH	367	/**
	368	* struct dfl_fpga_enum_info - DFL FPGA enumeration information
	369	*
	370	* @dev: parent device.
	371	* @dfls: list of device feature lists.
	372	*/
	373	struct dfl_fpga_enum_info {
	374	struct device *dev;
	375	struct list_head dfls;
	376	};
	377
	378	/**
	379	* struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info
	380	*
	381	* @start: base address of this device feature list.
	382	* @len: size of this device feature list.
	383	* @ioaddr: mapped base address of this device feature list.
	384	* @node: node in list of device feature lists.
	385	*/
	386	struct dfl_fpga_enum_dfl {
	387	resource_size_t start;
	388	resource_size_t len;
	389
	390	void __iomem *ioaddr;
	391
	392	struct list_head node;
	393	};
	394
	395	struct dfl_fpga_enum_info dfl_fpga_enum_info_alloc(struct device dev);
	396	int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
	397	resource_size_t start, resource_size_t len,
	398	void __iomem *ioaddr);
	399	void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info);
	400
	401	/**
	402	* struct dfl_fpga_cdev - container device of DFL based FPGA
	403	*
	404	* @parent: parent device of this container device.
	405	* @region: base fpga region.
	406	* @fme_dev: FME feature device under this container device.
	407	* @lock: mutex lock to protect the port device list.
	408	* @port_dev_list: list of all port feature devices under this container device.
69bb18dd	409	* @released_port_num: released port number under this container device.
543be3d8 WH	410	*/
	411	struct dfl_fpga_cdev {
	412	struct device *parent;
	413	struct fpga_region *region;
	414	struct device *fme_dev;
	415	struct mutex lock;
	416	struct list_head port_dev_list;
69bb18dd	417	int released_port_num;
543be3d8 WH	418	};
	419
	420	struct dfl_fpga_cdev *
	421	dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info);
	422	void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev);
	423
5d56e117 WH	424	/*
	425	* need to drop the device reference with put_device() after use port platform
	426	* device returned by __dfl_fpga_cdev_find_port and dfl_fpga_cdev_find_port
	427	* functions.
	428	*/
	429	struct platform_device *
	430	__dfl_fpga_cdev_find_port(struct dfl_fpga_cdev cdev, void data,
	431	int (match)(struct platform_device , void *));
	432
	433	static inline struct platform_device *
	434	dfl_fpga_cdev_find_port(struct dfl_fpga_cdev cdev, void data,
	435	int (match)(struct platform_device , void *))
	436	{
	437	struct platform_device *pdev;
	438
	439	mutex_lock(&cdev->lock);
	440	pdev = __dfl_fpga_cdev_find_port(cdev, data, match);
	441	mutex_unlock(&cdev->lock);
	442
	443	return pdev;
	444	}
69bb18dd WH	445
	446	int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id);
	447	int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id);
bdd4f307 WH	448	void dfl_fpga_cdev_config_ports_pf(struct dfl_fpga_cdev *cdev);
bdd4f307 WH	449	int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vf);
543be3d8	450	#endif /* __FPGA_DFL_H */