[linux-2.6-block.git] / drivers / fpga / dfl.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Driver Header File for FPGA Device Feature List (DFL) Support
 *
 * Copyright (C) 2017-2018 Intel Corporation, Inc.
 *
 * Authors:
 *   Kang Luwei <luwei.kang@intel.com>
 *   Zhang Yi <yi.z.zhang@intel.com>
 *   Wu Hao <hao.wu@intel.com>
 *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
 */

#ifndef __FPGA_DFL_H
#define __FPGA_DFL_H

#include <linux/bitfield.h>
#include <linux/cdev.h>
#include <linux/delay.h>
#include <linux/eventfd.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/iopoll.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/uuid.h>
#include <linux/fpga/fpga-region.h>

/* maximum supported number of ports */
#define MAX_DFL_FPGA_PORT_NUM 4
/* plus one for fme device */
#define MAX_DFL_FEATURE_DEV_NUM    (MAX_DFL_FPGA_PORT_NUM + 1)

/* Reserved 0xfe for Header Group Register and 0xff for AFU */
#define FEATURE_ID_FIU_HEADER		0xfe
#define FEATURE_ID_AFU			0xff

#define FME_FEATURE_ID_HEADER		FEATURE_ID_FIU_HEADER
#define FME_FEATURE_ID_THERMAL_MGMT	0x1
#define FME_FEATURE_ID_POWER_MGMT	0x2
#define FME_FEATURE_ID_GLOBAL_IPERF	0x3
#define FME_FEATURE_ID_GLOBAL_ERR	0x4
#define FME_FEATURE_ID_PR_MGMT		0x5
#define FME_FEATURE_ID_HSSI		0x6
#define FME_FEATURE_ID_GLOBAL_DPERF	0x7

#define PORT_FEATURE_ID_HEADER		FEATURE_ID_FIU_HEADER
#define PORT_FEATURE_ID_AFU		FEATURE_ID_AFU
#define PORT_FEATURE_ID_ERROR		0x10
#define PORT_FEATURE_ID_UMSG		0x11
#define PORT_FEATURE_ID_UINT		0x12
#define PORT_FEATURE_ID_STP		0x13

/*
 * Device Feature Header Register Set
 *
 * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers.
 * For AFUs, they have DFH + GUID as common header registers.
 * For private features, they only have DFH register as common header.
 */
#define DFH			0x0
#define GUID_L			0x8
#define GUID_H			0x10
#define NEXT_AFU		0x18

#define DFH_SIZE		0x8

/* Device Feature Header Register Bitfield */
#define DFH_ID			GENMASK_ULL(11, 0)	/* Feature ID */
#define DFH_ID_FIU_FME		0
#define DFH_ID_FIU_PORT		1
#define DFH_REVISION		GENMASK_ULL(15, 12)	/* Feature revision */
#define DFH_NEXT_HDR_OFST	GENMASK_ULL(39, 16)	/* Offset to next DFH */
#define DFH_EOL			BIT_ULL(40)		/* End of list */
#define DFH_TYPE		GENMASK_ULL(63, 60)	/* Feature type */
#define DFH_TYPE_AFU		1
#define DFH_TYPE_PRIVATE	3
#define DFH_TYPE_FIU		4

/* Next AFU Register Bitfield */
#define NEXT_AFU_NEXT_DFH_OFST	GENMASK_ULL(23, 0)	/* Offset to next AFU */

/* FME Header Register Set */
#define FME_HDR_DFH		DFH
#define FME_HDR_GUID_L		GUID_L
#define FME_HDR_GUID_H		GUID_H
#define FME_HDR_NEXT_AFU	NEXT_AFU
#define FME_HDR_CAP		0x30
#define FME_HDR_PORT_OFST(n)	(0x38 + ((n) * 0x8))
#define FME_PORT_OFST_BAR_SKIP	7
#define FME_HDR_BITSTREAM_ID	0x60
#define FME_HDR_BITSTREAM_MD	0x68

/* FME Fab Capability Register Bitfield */
#define FME_CAP_FABRIC_VERID	GENMASK_ULL(7, 0)	/* Fabric version ID */
#define FME_CAP_SOCKET_ID	BIT_ULL(8)		/* Socket ID */
#define FME_CAP_PCIE0_LINK_AVL	BIT_ULL(12)		/* PCIE0 Link */
#define FME_CAP_PCIE1_LINK_AVL	BIT_ULL(13)		/* PCIE1 Link */
#define FME_CAP_COHR_LINK_AVL	BIT_ULL(14)		/* Coherent Link */
#define FME_CAP_IOMMU_AVL	BIT_ULL(16)		/* IOMMU available */
#define FME_CAP_NUM_PORTS	GENMASK_ULL(19, 17)	/* Number of ports */
#define FME_CAP_ADDR_WIDTH	GENMASK_ULL(29, 24)	/* Address bus width */
#define FME_CAP_CACHE_SIZE	GENMASK_ULL(43, 32)	/* cache size in KB */
#define FME_CAP_CACHE_ASSOC	GENMASK_ULL(47, 44)	/* Associativity */

/* FME Port Offset Register Bitfield */
/* Offset to port device feature header */
#define FME_PORT_OFST_DFH_OFST	GENMASK_ULL(23, 0)
/* PCI Bar ID for this port */
#define FME_PORT_OFST_BAR_ID	GENMASK_ULL(34, 32)
/* AFU MMIO access permission. 1 - VF, 0 - PF. */
#define FME_PORT_OFST_ACC_CTRL	BIT_ULL(55)
#define FME_PORT_OFST_ACC_PF	0
#define FME_PORT_OFST_ACC_VF	1
#define FME_PORT_OFST_IMP	BIT_ULL(60)

/* FME Error Capability Register */
#define FME_ERROR_CAP		0x70

/* FME Error Capability Register Bitfield */
#define FME_ERROR_CAP_SUPP_INT	BIT_ULL(0)		/* Interrupt Support */
#define FME_ERROR_CAP_INT_VECT	GENMASK_ULL(12, 1)	/* Interrupt vector */

/* PORT Header Register Set */
#define PORT_HDR_DFH		DFH
#define PORT_HDR_GUID_L		GUID_L
#define PORT_HDR_GUID_H		GUID_H
#define PORT_HDR_NEXT_AFU	NEXT_AFU
#define PORT_HDR_CAP		0x30
#define PORT_HDR_CTRL		0x38
#define PORT_HDR_STS		0x40
#define PORT_HDR_USRCLK_CMD0	0x50
#define PORT_HDR_USRCLK_CMD1	0x58
#define PORT_HDR_USRCLK_STS0	0x60
#define PORT_HDR_USRCLK_STS1	0x68

/* Port Capability Register Bitfield */
#define PORT_CAP_PORT_NUM	GENMASK_ULL(1, 0)	/* ID of this port */
#define PORT_CAP_MMIO_SIZE	GENMASK_ULL(23, 8)	/* MMIO size in KB */
#define PORT_CAP_SUPP_INT_NUM	GENMASK_ULL(35, 32)	/* Interrupts num */

/* Port Control Register Bitfield */
#define PORT_CTRL_SFTRST	BIT_ULL(0)		/* Port soft reset */
/* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/
#define PORT_CTRL_LATENCY	BIT_ULL(2)
#define PORT_CTRL_SFTRST_ACK	BIT_ULL(4)		/* HW ack for reset */

/* Port Status Register Bitfield */
#define PORT_STS_AP2_EVT	BIT_ULL(13)		/* AP2 event detected */
#define PORT_STS_AP1_EVT	BIT_ULL(12)		/* AP1 event detected */
#define PORT_STS_PWR_STATE	GENMASK_ULL(11, 8)	/* AFU power states */
#define PORT_STS_PWR_STATE_NORM 0
#define PORT_STS_PWR_STATE_AP1	1			/* 50% throttling */
#define PORT_STS_PWR_STATE_AP2	2			/* 90% throttling */
#define PORT_STS_PWR_STATE_AP6	6			/* 100% throttling */

/* Port Error Capability Register */
#define PORT_ERROR_CAP		0x38

/* Port Error Capability Register Bitfield */
#define PORT_ERROR_CAP_SUPP_INT	BIT_ULL(0)		/* Interrupt Support */
#define PORT_ERROR_CAP_INT_VECT	GENMASK_ULL(12, 1)	/* Interrupt vector */

/* Port Uint Capability Register */
#define PORT_UINT_CAP		0x8

/* Port Uint Capability Register Bitfield */
#define PORT_UINT_CAP_INT_NUM	GENMASK_ULL(11, 0)	/* Interrupts num */
#define PORT_UINT_CAP_FST_VECT	GENMASK_ULL(23, 12)	/* First Vector */

/**
 * struct dfl_fpga_port_ops - port ops
 *
 * @name: name of this port ops, to match with port platform device.
 * @owner: pointer to the module which owns this port ops.
 * @node: node to link port ops to global list.
 * @get_id: get port id from hardware.
 * @enable_set: enable/disable the port.
 */
struct dfl_fpga_port_ops {
	const char *name;
	struct module *owner;
	struct list_head node;
	int (*get_id)(struct platform_device *pdev);
	int (*enable_set)(struct platform_device *pdev, bool enable);
};

void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops);
void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops);
struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev);
void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops);
int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id);

/**
 * struct dfl_feature_id - dfl private feature id
 *
 * @id: unique dfl private feature id.
 */
struct dfl_feature_id {
	u16 id;
};

/**
 * struct dfl_feature_driver - dfl private feature driver
 *
 * @id_table: id_table for dfl private features supported by this driver.
 * @ops: ops of this dfl private feature driver.
 */
struct dfl_feature_driver {
	const struct dfl_feature_id *id_table;
	const struct dfl_feature_ops *ops;
};

/**
 * struct dfl_feature_irq_ctx - dfl private feature interrupt context
 *
 * @irq: Linux IRQ number of this interrupt.
 * @trigger: eventfd context to signal when interrupt happens.
 * @name: irq name needed when requesting irq.
 */
struct dfl_feature_irq_ctx {
	int irq;
	struct eventfd_ctx *trigger;
	char *name;
};

/**
 * struct dfl_feature - sub feature of the feature devices
 *
 * @dev: ptr to pdev of the feature device which has the sub feature.
 * @id: sub feature id.
 * @resource_index: each sub feature has one mmio resource for its registers.
 *		    this index is used to find its mmio resource from the
 *		    feature dev (platform device)'s resources.
 * @ioaddr: mapped mmio resource address.
 * @irq_ctx: interrupt context list.
 * @nr_irqs: number of interrupt contexts.
 * @ops: ops of this sub feature.
 * @ddev: ptr to the dfl device of this sub feature.
 * @priv: priv data of this feature.
 */
struct dfl_feature {
	struct platform_device *dev;
	u16 id;
	u8 revision;
	int resource_index;
	void __iomem *ioaddr;
	struct dfl_feature_irq_ctx *irq_ctx;
	unsigned int nr_irqs;
	const struct dfl_feature_ops *ops;
	struct dfl_device *ddev;
	void *priv;
};

#define FEATURE_DEV_ID_UNUSED	(-1)

/**
 * struct dfl_feature_platform_data - platform data for feature devices
 *
 * @node: node to link feature devs to container device's port_dev_list.
 * @lock: mutex to protect platform data.
 * @cdev: cdev of feature dev.
 * @dev: ptr to platform device linked with this platform data.
 * @dfl_cdev: ptr to container device.
 * @id: id used for this feature device.
 * @disable_count: count for port disable.
 * @excl_open: set on feature device exclusive open.
 * @open_count: count for feature device open.
 * @num: number for sub features.
 * @private: ptr to feature dev private data.
 * @features: sub features of this feature dev.
 */
struct dfl_feature_platform_data {
	struct list_head node;
	struct mutex lock;
	struct cdev cdev;
	struct platform_device *dev;
	struct dfl_fpga_cdev *dfl_cdev;
	int id;
	unsigned int disable_count;
	bool excl_open;
	int open_count;
	void *private;
	int num;
	struct dfl_feature features[];
};

static inline
int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata,
			      bool excl)
{
	if (pdata->excl_open)
		return -EBUSY;

	if (excl) {
		if (pdata->open_count)
			return -EBUSY;

		pdata->excl_open = true;
	}
	pdata->open_count++;

	return 0;
}

static inline
void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata)
{
	pdata->excl_open = false;

	if (WARN_ON(pdata->open_count <= 0))
		return;

	pdata->open_count--;
}

static inline
int dfl_feature_dev_use_count(struct dfl_feature_platform_data *pdata)
{
	return pdata->open_count;
}

static inline
void dfl_fpga_pdata_set_private(struct dfl_feature_platform_data *pdata,
				void *private)
{
	pdata->private = private;
}

static inline
void *dfl_fpga_pdata_get_private(struct dfl_feature_platform_data *pdata)
{
	return pdata->private;
}

struct dfl_feature_ops {
	int (*init)(struct platform_device *pdev, struct dfl_feature *feature);
	void (*uinit)(struct platform_device *pdev,
		      struct dfl_feature *feature);
	long (*ioctl)(struct platform_device *pdev, struct dfl_feature *feature,
		      unsigned int cmd, unsigned long arg);
};

#define DFL_FPGA_FEATURE_DEV_FME		"dfl-fme"
#define DFL_FPGA_FEATURE_DEV_PORT		"dfl-port"

void dfl_fpga_dev_feature_uinit(struct platform_device *pdev);
int dfl_fpga_dev_feature_init(struct platform_device *pdev,
			      struct dfl_feature_driver *feature_drvs);

int dfl_fpga_dev_ops_register(struct platform_device *pdev,
			      const struct file_operations *fops,
			      struct module *owner);
void dfl_fpga_dev_ops_unregister(struct platform_device *pdev);

static inline
struct platform_device *dfl_fpga_inode_to_feature_dev(struct inode *inode)
{
	struct dfl_feature_platform_data *pdata;

	pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data,
			     cdev);
	return pdata->dev;
}

#define dfl_fpga_dev_for_each_feature(pdata, feature)			    \
	for ((feature) = (pdata)->features;				    \
	   (feature) < (pdata)->features + (pdata)->num; (feature)++)

static inline
struct dfl_feature *dfl_get_feature_by_id(struct device *dev, u16 id)
{
	struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
	struct dfl_feature *feature;

	dfl_fpga_dev_for_each_feature(pdata, feature)
		if (feature->id == id)
			return feature;

	return NULL;
}

static inline
void __iomem *dfl_get_feature_ioaddr_by_id(struct device *dev, u16 id)
{
	struct dfl_feature *feature = dfl_get_feature_by_id(dev, id);

	if (feature && feature->ioaddr)
		return feature->ioaddr;

	WARN_ON(1);
	return NULL;
}

static inline bool is_dfl_feature_present(struct device *dev, u16 id)
{
	return !!dfl_get_feature_ioaddr_by_id(dev, id);
}

static inline
struct device *dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data *pdata)
{
	return pdata->dev->dev.parent->parent;
}

static inline bool dfl_feature_is_fme(void __iomem *base)
{
	u64 v = readq(base + DFH);

	return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
		(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME);
}

static inline bool dfl_feature_is_port(void __iomem *base)
{
	u64 v = readq(base + DFH);

	return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
		(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);
}

static inline u8 dfl_feature_revision(void __iomem *base)
{
	return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH));
}

/**
 * struct dfl_fpga_enum_info - DFL FPGA enumeration information
 *
 * @dev: parent device.
 * @dfls: list of device feature lists.
 * @nr_irqs: number of irqs for all feature devices.
 * @irq_table: Linux IRQ numbers for all irqs, indexed by hw irq numbers.
 */
struct dfl_fpga_enum_info {
	struct device *dev;
	struct list_head dfls;
	unsigned int nr_irqs;
	int *irq_table;
};

/**
 * struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info
 *
 * @start: base address of this device feature list.
 * @len: size of this device feature list.
 * @node: node in list of device feature lists.
 */
struct dfl_fpga_enum_dfl {
	resource_size_t start;
	resource_size_t len;
	struct list_head node;
};

struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev);
int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
			       resource_size_t start, resource_size_t len);
int dfl_fpga_enum_info_add_irq(struct dfl_fpga_enum_info *info,
			       unsigned int nr_irqs, int *irq_table);
void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info);

/**
 * struct dfl_fpga_cdev - container device of DFL based FPGA
 *
 * @parent: parent device of this container device.
 * @region: base fpga region.
 * @fme_dev: FME feature device under this container device.
 * @lock: mutex lock to protect the port device list.
 * @port_dev_list: list of all port feature devices under this container device.
 * @released_port_num: released port number under this container device.
 */
struct dfl_fpga_cdev {
	struct device *parent;
	struct fpga_region *region;
	struct device *fme_dev;
	struct mutex lock;
	struct list_head port_dev_list;
	int released_port_num;
};

struct dfl_fpga_cdev *
dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info);
void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev);

/*
 * need to drop the device reference with put_device() after use port platform
 * device returned by __dfl_fpga_cdev_find_port and dfl_fpga_cdev_find_port
 * functions.
 */
struct platform_device *
__dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
			  int (*match)(struct platform_device *, void *));

static inline struct platform_device *
dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
			int (*match)(struct platform_device *, void *))
{
	struct platform_device *pdev;

	mutex_lock(&cdev->lock);
	pdev = __dfl_fpga_cdev_find_port(cdev, data, match);
	mutex_unlock(&cdev->lock);

	return pdev;
}

int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id);
int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id);
void dfl_fpga_cdev_config_ports_pf(struct dfl_fpga_cdev *cdev);
int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vf);
int dfl_fpga_set_irq_triggers(struct dfl_feature *feature, unsigned int start,
			      unsigned int count, int32_t *fds);
long dfl_feature_ioctl_get_num_irqs(struct platform_device *pdev,
				    struct dfl_feature *feature,
				    unsigned long arg);
long dfl_feature_ioctl_set_irq(struct platform_device *pdev,
			       struct dfl_feature *feature,
			       unsigned long arg);

#endif /* __FPGA_DFL_H */
Commit	Line	Data
543be3d8 WH	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Driver Header File for FPGA Device Feature List (DFL) Support
	4	*
	5	* Copyright (C) 2017-2018 Intel Corporation, Inc.
	6	*
	7	* Authors:
	8	* Kang Luwei <luwei.kang@intel.com>
	9	* Zhang Yi <yi.z.zhang@intel.com>
	10	* Wu Hao <hao.wu@intel.com>
	11	* Xiao Guangrong <guangrong.xiao@linux.intel.com>
	12	*/
	13
	14	#ifndef __FPGA_DFL_H
	15	#define __FPGA_DFL_H
	16
	17	#include <linux/bitfield.h>
b16c5147	18	#include <linux/cdev.h>
543be3d8	19	#include <linux/delay.h>
322b598b	20	#include <linux/eventfd.h>
543be3d8	21	#include <linux/fs.h>
8d021039	22	#include <linux/interrupt.h>
543be3d8 WH	23	#include <linux/iopoll.h>
543be3d8 WH	24	#include <linux/io-64-nonatomic-lo-hi.h>
9326eecd	25	#include <linux/mod_devicetable.h>
543be3d8 WH	26	#include <linux/platform_device.h>
	27	#include <linux/slab.h>
	28	#include <linux/uuid.h>
	29	#include <linux/fpga/fpga-region.h>
	30
	31	/* maximum supported number of ports */
	32	#define MAX_DFL_FPGA_PORT_NUM 4
	33	/* plus one for fme device */
	34	#define MAX_DFL_FEATURE_DEV_NUM (MAX_DFL_FPGA_PORT_NUM + 1)
	35
15bbb300 WH	36	/* Reserved 0xfe for Header Group Register and 0xff for AFU */
15bbb300 WH	37	#define FEATURE_ID_FIU_HEADER 0xfe
543be3d8 WH	38	#define FEATURE_ID_AFU 0xff
	39
	40	#define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
	41	#define FME_FEATURE_ID_THERMAL_MGMT 0x1
	42	#define FME_FEATURE_ID_POWER_MGMT 0x2
	43	#define FME_FEATURE_ID_GLOBAL_IPERF 0x3
	44	#define FME_FEATURE_ID_GLOBAL_ERR 0x4
	45	#define FME_FEATURE_ID_PR_MGMT 0x5
	46	#define FME_FEATURE_ID_HSSI 0x6
	47	#define FME_FEATURE_ID_GLOBAL_DPERF 0x7
	48
	49	#define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
	50	#define PORT_FEATURE_ID_AFU FEATURE_ID_AFU
	51	#define PORT_FEATURE_ID_ERROR 0x10
	52	#define PORT_FEATURE_ID_UMSG 0x11
	53	#define PORT_FEATURE_ID_UINT 0x12
	54	#define PORT_FEATURE_ID_STP 0x13
	55
	56	/*
	57	* Device Feature Header Register Set
	58	*
	59	* For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers.
	60	* For AFUs, they have DFH + GUID as common header registers.
	61	* For private features, they only have DFH register as common header.
	62	*/
	63	#define DFH 0x0
	64	#define GUID_L 0x8
	65	#define GUID_H 0x10
	66	#define NEXT_AFU 0x18
	67
	68	#define DFH_SIZE 0x8
	69
	70	/* Device Feature Header Register Bitfield */
	71	#define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */
	72	#define DFH_ID_FIU_FME 0
	73	#define DFH_ID_FIU_PORT 1
	74	#define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */
	75	#define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */
	76	#define DFH_EOL BIT_ULL(40) /* End of list */
	77	#define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */
	78	#define DFH_TYPE_AFU 1
	79	#define DFH_TYPE_PRIVATE 3
	80	#define DFH_TYPE_FIU 4
	81
	82	/* Next AFU Register Bitfield */
	83	#define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */
	84
	85	/* FME Header Register Set */
	86	#define FME_HDR_DFH DFH
	87	#define FME_HDR_GUID_L GUID_L
	88	#define FME_HDR_GUID_H GUID_H
	89	#define FME_HDR_NEXT_AFU NEXT_AFU
	90	#define FME_HDR_CAP 0x30
	91	#define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8))
ae23f746	92	#define FME_PORT_OFST_BAR_SKIP 7
543be3d8 WH	93	#define FME_HDR_BITSTREAM_ID 0x60
	94	#define FME_HDR_BITSTREAM_MD 0x68
	95
	96	/* FME Fab Capability Register Bitfield */
	97	#define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */
	98	#define FME_CAP_SOCKET_ID BIT_ULL(8) /* Socket ID */
	99	#define FME_CAP_PCIE0_LINK_AVL BIT_ULL(12) /* PCIE0 Link */
	100	#define FME_CAP_PCIE1_LINK_AVL BIT_ULL(13) /* PCIE1 Link */
	101	#define FME_CAP_COHR_LINK_AVL BIT_ULL(14) /* Coherent Link */
	102	#define FME_CAP_IOMMU_AVL BIT_ULL(16) /* IOMMU available */
	103	#define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */
	104	#define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */
	105	#define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */
	106	#define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */
	107
	108	/* FME Port Offset Register Bitfield */
	109	/* Offset to port device feature header */
	110	#define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0)
	111	/* PCI Bar ID for this port */
	112	#define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32)
	113	/* AFU MMIO access permission. 1 - VF, 0 - PF. */
	114	#define FME_PORT_OFST_ACC_CTRL BIT_ULL(55)
	115	#define FME_PORT_OFST_ACC_PF 0
	116	#define FME_PORT_OFST_ACC_VF 1
	117	#define FME_PORT_OFST_IMP BIT_ULL(60)
	118
8d021039 XY	119	/* FME Error Capability Register */
	120	#define FME_ERROR_CAP 0x70
	121
	122	/* FME Error Capability Register Bitfield */
	123	#define FME_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */
	124	#define FME_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */
	125
543be3d8 WH	126	/* PORT Header Register Set */
	127	#define PORT_HDR_DFH DFH
	128	#define PORT_HDR_GUID_L GUID_L
	129	#define PORT_HDR_GUID_H GUID_H
	130	#define PORT_HDR_NEXT_AFU NEXT_AFU
	131	#define PORT_HDR_CAP 0x30
	132	#define PORT_HDR_CTRL 0x38
d2ad5ac1	133	#define PORT_HDR_STS 0x40
f09991ad WH	134	#define PORT_HDR_USRCLK_CMD0 0x50
	135	#define PORT_HDR_USRCLK_CMD1 0x58
	136	#define PORT_HDR_USRCLK_STS0 0x60
	137	#define PORT_HDR_USRCLK_STS1 0x68
543be3d8 WH	138
	139	/* Port Capability Register Bitfield */
	140	#define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */
	141	#define PORT_CAP_MMIO_SIZE GENMASK_ULL(23, 8) /* MMIO size in KB */
	142	#define PORT_CAP_SUPP_INT_NUM GENMASK_ULL(35, 32) /* Interrupts num */
	143
	144	/* Port Control Register Bitfield */
	145	#define PORT_CTRL_SFTRST BIT_ULL(0) /* Port soft reset */
	146	/* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/
	147	#define PORT_CTRL_LATENCY BIT_ULL(2)
	148	#define PORT_CTRL_SFTRST_ACK BIT_ULL(4) /* HW ack for reset */
d2ad5ac1 WH	149
	150	/* Port Status Register Bitfield */
	151	#define PORT_STS_AP2_EVT BIT_ULL(13) /* AP2 event detected */
	152	#define PORT_STS_AP1_EVT BIT_ULL(12) /* AP1 event detected */
	153	#define PORT_STS_PWR_STATE GENMASK_ULL(11, 8) /* AFU power states */
	154	#define PORT_STS_PWR_STATE_NORM 0
	155	#define PORT_STS_PWR_STATE_AP1 1 /* 50% throttling */
	156	#define PORT_STS_PWR_STATE_AP2 2 /* 90% throttling */
	157	#define PORT_STS_PWR_STATE_AP6 6 /* 100% throttling */
	158
8d021039 XY	159	/* Port Error Capability Register */
	160	#define PORT_ERROR_CAP 0x38
	161
	162	/* Port Error Capability Register Bitfield */
	163	#define PORT_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */
	164	#define PORT_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */
	165
	166	/* Port Uint Capability Register */
	167	#define PORT_UINT_CAP 0x8
	168
	169	/* Port Uint Capability Register Bitfield */
	170	#define PORT_UINT_CAP_INT_NUM GENMASK_ULL(11, 0) /* Interrupts num */
	171	#define PORT_UINT_CAP_FST_VECT GENMASK_ULL(23, 12) /* First Vector */
	172
6e8fd6e4 WH	173	/**
	174	* struct dfl_fpga_port_ops - port ops
	175	*
	176	* @name: name of this port ops, to match with port platform device.
	177	* @owner: pointer to the module which owns this port ops.
	178	* @node: node to link port ops to global list.
	179	* @get_id: get port id from hardware.
	180	* @enable_set: enable/disable the port.
	181	*/
	182	struct dfl_fpga_port_ops {
	183	const char *name;
	184	struct module *owner;
	185	struct list_head node;
	186	int (get_id)(struct platform_device pdev);
	187	int (enable_set)(struct platform_device pdev, bool enable);
	188	};
	189
	190	void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops);
	191	void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops);
	192	struct dfl_fpga_port_ops dfl_fpga_port_ops_get(struct platform_device pdev);
	193	void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops);
d06b004b	194	int dfl_fpga_check_port_id(struct platform_device pdev, void pport_id);
543be3d8	195
5b57d02a	196	/**
15bbb300	197	* struct dfl_feature_id - dfl private feature id
5b57d02a	198	*
15bbb300	199	* @id: unique dfl private feature id.
5b57d02a	200	*/
15bbb300	201	struct dfl_feature_id {
8a5de2de	202	u16 id;
15bbb300 WH	203	};
	204
	205	/**
	206	* struct dfl_feature_driver - dfl private feature driver
	207	*
	208	* @id_table: id_table for dfl private features supported by this driver.
	209	* @ops: ops of this dfl private feature driver.
	210	*/
	211	struct dfl_feature_driver {
	212	const struct dfl_feature_id *id_table;
5b57d02a XG	213	const struct dfl_feature_ops *ops;
	214	};
	215
8d021039 XY	216	/**
	217	* struct dfl_feature_irq_ctx - dfl private feature interrupt context
	218	*
	219	* @irq: Linux IRQ number of this interrupt.
322b598b XY	220	* @trigger: eventfd context to signal when interrupt happens.
322b598b XY	221	* @name: irq name needed when requesting irq.
8d021039 XY	222	*/
	223	struct dfl_feature_irq_ctx {
	224	int irq;
322b598b XY	225	struct eventfd_ctx *trigger;
322b598b XY	226	char *name;
8d021039 XY	227	};
8d021039 XY	228
543be3d8 WH	229	/**
	230	* struct dfl_feature - sub feature of the feature devices
	231	*
322b598b	232	* @dev: ptr to pdev of the feature device which has the sub feature.
543be3d8 WH	233	* @id: sub feature id.
	234	* @resource_index: each sub feature has one mmio resource for its registers.
	235	* this index is used to find its mmio resource from the
580e3137	236	* feature dev (platform device)'s resources.
543be3d8	237	* @ioaddr: mapped mmio resource address.
8d021039 XY	238	* @irq_ctx: interrupt context list.
8d021039 XY	239	* @nr_irqs: number of interrupt contexts.
5b57d02a	240	* @ops: ops of this sub feature.
9ba3a0aa	241	* @ddev: ptr to the dfl device of this sub feature.
724142f8	242	* @priv: priv data of this feature.
543be3d8 WH	243	*/
543be3d8 WH	244	struct dfl_feature {
322b598b	245	struct platform_device *dev;
8a5de2de	246	u16 id;
1604986c	247	u8 revision;
543be3d8 WH	248	int resource_index;
543be3d8 WH	249	void __iomem *ioaddr;
8d021039 XY	250	struct dfl_feature_irq_ctx *irq_ctx;
8d021039 XY	251	unsigned int nr_irqs;
5b57d02a	252	const struct dfl_feature_ops *ops;
9ba3a0aa	253	struct dfl_device *ddev;
724142f8	254	void *priv;
543be3d8 WH	255	};
543be3d8 WH	256
69bb18dd WH	257	#define FEATURE_DEV_ID_UNUSED (-1)
69bb18dd WH	258
543be3d8 WH	259	/**
	260	* struct dfl_feature_platform_data - platform data for feature devices
	261	*
	262	* @node: node to link feature devs to container device's port_dev_list.
	263	* @lock: mutex to protect platform data.
b16c5147	264	* @cdev: cdev of feature dev.
543be3d8 WH	265	* @dev: ptr to platform device linked with this platform data.
543be3d8 WH	266	* @dfl_cdev: ptr to container device.
69bb18dd	267	* @id: id used for this feature device.
543be3d8	268	* @disable_count: count for port disable.
b6862193 XY	269	* @excl_open: set on feature device exclusive open.
b6862193 XY	270	* @open_count: count for feature device open.
543be3d8	271	* @num: number for sub features.
5b57d02a	272	* @private: ptr to feature dev private data.
543be3d8 WH	273	* @features: sub features of this feature dev.
	274	*/
	275	struct dfl_feature_platform_data {
	276	struct list_head node;
	277	struct mutex lock;
b16c5147	278	struct cdev cdev;
543be3d8 WH	279	struct platform_device *dev;
543be3d8 WH	280	struct dfl_fpga_cdev *dfl_cdev;
69bb18dd	281	int id;
543be3d8	282	unsigned int disable_count;
b6862193 XY	283	bool excl_open;
b6862193 XY	284	int open_count;
5b57d02a	285	void *private;
543be3d8	286	int num;
5a538815	287	struct dfl_feature features[];
543be3d8 WH	288	};
543be3d8 WH	289
5b57d02a	290	static inline
b6862193 XY	291	int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata,
b6862193 XY	292	bool excl)
5b57d02a	293	{
b6862193	294	if (pdata->excl_open)
5b57d02a XG	295	return -EBUSY;
5b57d02a XG	296
b6862193 XY	297	if (excl) {
	298	if (pdata->open_count)
	299	return -EBUSY;
	300
	301	pdata->excl_open = true;
	302	}
	303	pdata->open_count++;
	304
5b57d02a XG	305	return 0;
	306	}
	307
	308	static inline
	309	void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata)
	310	{
b6862193 XY	311	pdata->excl_open = false;
	312
	313	if (WARN_ON(pdata->open_count <= 0))
	314	return;
	315
	316	pdata->open_count--;
	317	}
	318
	319	static inline
	320	int dfl_feature_dev_use_count(struct dfl_feature_platform_data *pdata)
	321	{
	322	return pdata->open_count;
5b57d02a XG	323	}
	324
	325	static inline
	326	void dfl_fpga_pdata_set_private(struct dfl_feature_platform_data *pdata,
	327	void *private)
	328	{
	329	pdata->private = private;
	330	}
	331
	332	static inline
	333	void dfl_fpga_pdata_get_private(struct dfl_feature_platform_data pdata)
	334	{
	335	return pdata->private;
	336	}
	337
	338	struct dfl_feature_ops {
	339	int (init)(struct platform_device pdev, struct dfl_feature *feature);
	340	void (uinit)(struct platform_device pdev,
	341	struct dfl_feature *feature);
	342	long (ioctl)(struct platform_device pdev, struct dfl_feature *feature,
	343	unsigned int cmd, unsigned long arg);
	344	};
	345
543be3d8 WH	346	#define DFL_FPGA_FEATURE_DEV_FME "dfl-fme"
	347	#define DFL_FPGA_FEATURE_DEV_PORT "dfl-port"
	348
5b57d02a XG	349	void dfl_fpga_dev_feature_uinit(struct platform_device *pdev);
	350	int dfl_fpga_dev_feature_init(struct platform_device *pdev,
	351	struct dfl_feature_driver *feature_drvs);
	352
b16c5147 WH	353	int dfl_fpga_dev_ops_register(struct platform_device *pdev,
	354	const struct file_operations *fops,
	355	struct module *owner);
	356	void dfl_fpga_dev_ops_unregister(struct platform_device *pdev);
	357
5b57d02a XG	358	static inline
	359	struct platform_device dfl_fpga_inode_to_feature_dev(struct inode inode)
	360	{
	361	struct dfl_feature_platform_data *pdata;
	362
	363	pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data,
	364	cdev);
	365	return pdata->dev;
	366	}
	367
543be3d8 WH	368	#define dfl_fpga_dev_for_each_feature(pdata, feature) \
	369	for ((feature) = (pdata)->features; \
	370	(feature) < (pdata)->features + (pdata)->num; (feature)++)
	371
	372	static inline
8a5de2de	373	struct dfl_feature dfl_get_feature_by_id(struct device dev, u16 id)
543be3d8 WH	374	{
	375	struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
	376	struct dfl_feature *feature;
	377
	378	dfl_fpga_dev_for_each_feature(pdata, feature)
	379	if (feature->id == id)
	380	return feature;
	381
	382	return NULL;
	383	}
	384
	385	static inline
8a5de2de	386	void __iomem dfl_get_feature_ioaddr_by_id(struct device dev, u16 id)
543be3d8 WH	387	{
	388	struct dfl_feature *feature = dfl_get_feature_by_id(dev, id);
	389
	390	if (feature && feature->ioaddr)
	391	return feature->ioaddr;
	392
	393	WARN_ON(1);
	394	return NULL;
	395	}
	396
8a5de2de	397	static inline bool is_dfl_feature_present(struct device *dev, u16 id)
5b57d02a XG	398	{
	399	return !!dfl_get_feature_ioaddr_by_id(dev, id);
	400	}
	401
	402	static inline
	403	struct device dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data pdata)
	404	{
	405	return pdata->dev->dev.parent->parent;
	406	}
	407
543be3d8 WH	408	static inline bool dfl_feature_is_fme(void __iomem *base)
	409	{
	410	u64 v = readq(base + DFH);
	411
	412	return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
	413	(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME);
	414	}
	415
	416	static inline bool dfl_feature_is_port(void __iomem *base)
	417	{
	418	u64 v = readq(base + DFH);
	419
	420	return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
	421	(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);
	422	}
	423
f09991ad WH	424	static inline u8 dfl_feature_revision(void __iomem *base)
	425	{
	426	return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH));
	427	}
	428
543be3d8 WH	429	/**
	430	* struct dfl_fpga_enum_info - DFL FPGA enumeration information
	431	*
	432	* @dev: parent device.
	433	* @dfls: list of device feature lists.
8d021039 XY	434	* @nr_irqs: number of irqs for all feature devices.
8d021039 XY	435	* @irq_table: Linux IRQ numbers for all irqs, indexed by hw irq numbers.
543be3d8 WH	436	*/
	437	struct dfl_fpga_enum_info {
	438	struct device *dev;
	439	struct list_head dfls;
8d021039 XY	440	unsigned int nr_irqs;
8d021039 XY	441	int *irq_table;
543be3d8 WH	442	};
	443
	444	/**
	445	* struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info
	446	*
	447	* @start: base address of this device feature list.
	448	* @len: size of this device feature list.
543be3d8 WH	449	* @node: node in list of device feature lists.
	450	*/
	451	struct dfl_fpga_enum_dfl {
	452	resource_size_t start;
	453	resource_size_t len;
543be3d8 WH	454	struct list_head node;
	455	};
	456
	457	struct dfl_fpga_enum_info dfl_fpga_enum_info_alloc(struct device dev);
	458	int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
89eb35e8	459	resource_size_t start, resource_size_t len);
8d021039 XY	460	int dfl_fpga_enum_info_add_irq(struct dfl_fpga_enum_info *info,
8d021039 XY	461	unsigned int nr_irqs, int *irq_table);
543be3d8 WH	462	void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info);
	463
	464	/**
	465	* struct dfl_fpga_cdev - container device of DFL based FPGA
	466	*
	467	* @parent: parent device of this container device.
	468	* @region: base fpga region.
	469	* @fme_dev: FME feature device under this container device.
	470	* @lock: mutex lock to protect the port device list.
	471	* @port_dev_list: list of all port feature devices under this container device.
69bb18dd	472	* @released_port_num: released port number under this container device.
543be3d8 WH	473	*/
	474	struct dfl_fpga_cdev {
	475	struct device *parent;
	476	struct fpga_region *region;
	477	struct device *fme_dev;
	478	struct mutex lock;
	479	struct list_head port_dev_list;
69bb18dd	480	int released_port_num;
543be3d8 WH	481	};
	482
	483	struct dfl_fpga_cdev *
	484	dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info);
	485	void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev);
	486
5d56e117 WH	487	/*
	488	* need to drop the device reference with put_device() after use port platform
	489	* device returned by __dfl_fpga_cdev_find_port and dfl_fpga_cdev_find_port
	490	* functions.
	491	*/
	492	struct platform_device *
	493	__dfl_fpga_cdev_find_port(struct dfl_fpga_cdev cdev, void data,
	494	int (match)(struct platform_device , void *));
	495
	496	static inline struct platform_device *
	497	dfl_fpga_cdev_find_port(struct dfl_fpga_cdev cdev, void data,
	498	int (match)(struct platform_device , void *))
	499	{
	500	struct platform_device *pdev;
	501
	502	mutex_lock(&cdev->lock);
	503	pdev = __dfl_fpga_cdev_find_port(cdev, data, match);
	504	mutex_unlock(&cdev->lock);
	505
	506	return pdev;
	507	}
69bb18dd WH	508
	509	int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id);
	510	int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id);
bdd4f307 WH	511	void dfl_fpga_cdev_config_ports_pf(struct dfl_fpga_cdev *cdev);
bdd4f307 WH	512	int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vf);
322b598b XY	513	int dfl_fpga_set_irq_triggers(struct dfl_feature *feature, unsigned int start,
	514	unsigned int count, int32_t *fds);
	515	long dfl_feature_ioctl_get_num_irqs(struct platform_device *pdev,
	516	struct dfl_feature *feature,
	517	unsigned long arg);
	518	long dfl_feature_ioctl_set_irq(struct platform_device *pdev,
	519	struct dfl_feature *feature,
	520	unsigned long arg);
	521
543be3d8	522	#endif /* __FPGA_DFL_H */