[linux-block.git] / drivers / fpga / dfl-pci.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Driver for FPGA Device Feature List (DFL) PCIe device
 *
 * Copyright (C) 2017-2018 Intel Corporation, Inc.
 *
 * Authors:
 *   Zhang Yi <Yi.Z.Zhang@intel.com>
 *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
 *   Joseph Grecco <joe.grecco@intel.com>
 *   Enno Luebbers <enno.luebbers@intel.com>
 *   Tim Whisonant <tim.whisonant@intel.com>
 *   Ananda Ravuri <ananda.ravuri@intel.com>
 *   Henry Mitchel <henry.mitchel@intel.com>
 */

#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/stddef.h>
#include <linux/errno.h>

#include "dfl.h"

#define DRV_VERSION	"0.8"
#define DRV_NAME	"dfl-pci"

#define PCI_VSEC_ID_INTEL_DFLS 0x43

#define PCI_VNDR_DFLS_CNT 0x8
#define PCI_VNDR_DFLS_RES 0xc

#define PCI_VNDR_DFLS_RES_BAR_MASK GENMASK(2, 0)
#define PCI_VNDR_DFLS_RES_OFF_MASK GENMASK(31, 3)

struct cci_drvdata {
	struct dfl_fpga_cdev *cdev;	/* container device */
};

static int cci_pci_alloc_irq(struct pci_dev *pcidev)
{
	int ret, nvec = pci_msix_vec_count(pcidev);

	if (nvec <= 0) {
		dev_dbg(&pcidev->dev, "fpga interrupt not supported\n");
		return 0;
	}

	ret = pci_alloc_irq_vectors(pcidev, nvec, nvec, PCI_IRQ_MSIX);
	if (ret < 0)
		return ret;

	return nvec;
}

static void cci_pci_free_irq(struct pci_dev *pcidev)
{
	pci_free_irq_vectors(pcidev);
}

/* PCI Device ID */
#define PCIE_DEVICE_ID_PF_INT_5_X		0xBCBD
#define PCIE_DEVICE_ID_PF_INT_6_X		0xBCC0
#define PCIE_DEVICE_ID_PF_DSC_1_X		0x09C4
#define PCIE_DEVICE_ID_INTEL_PAC_N3000		0x0B30
#define PCIE_DEVICE_ID_INTEL_PAC_D5005		0x0B2B
#define PCIE_DEVICE_ID_SILICOM_PAC_N5010	0x1000
#define PCIE_DEVICE_ID_SILICOM_PAC_N5011	0x1001
#define PCIE_DEVICE_ID_INTEL_DFL		0xbcce
/* PCI Subdevice ID for PCIE_DEVICE_ID_INTEL_DFL */
#define PCIE_SUBDEVICE_ID_INTEL_D5005		0x138d
#define PCIE_SUBDEVICE_ID_INTEL_N6000		0x1770
#define PCIE_SUBDEVICE_ID_INTEL_N6001		0x1771
#define PCIE_SUBDEVICE_ID_INTEL_C6100		0x17d4

/* VF Device */
#define PCIE_DEVICE_ID_VF_INT_5_X		0xBCBF
#define PCIE_DEVICE_ID_VF_INT_6_X		0xBCC1
#define PCIE_DEVICE_ID_VF_DSC_1_X		0x09C5
#define PCIE_DEVICE_ID_INTEL_PAC_D5005_VF	0x0B2C
#define PCIE_DEVICE_ID_INTEL_DFL_VF		0xbccf

static struct pci_device_id cci_pcie_id_tbl[] = {
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X),},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X),},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X),},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_N3000),},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005),},
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005_VF),},
	{PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5010),},
	{PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5011),},
	{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL,
			PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_D5005),},
	{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL,
			PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_N6000),},
	{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL_VF,
			PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_N6000),},
	{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL,
			PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_N6001),},
	{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL_VF,
			PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_N6001),},
	{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL,
			PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_C6100),},
	{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL_VF,
			PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_C6100),},
	{0,}
};
MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);

static int cci_init_drvdata(struct pci_dev *pcidev)
{
	struct cci_drvdata *drvdata;

	drvdata = devm_kzalloc(&pcidev->dev, sizeof(*drvdata), GFP_KERNEL);
	if (!drvdata)
		return -ENOMEM;

	pci_set_drvdata(pcidev, drvdata);

	return 0;
}

static void cci_remove_feature_devs(struct pci_dev *pcidev)
{
	struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);

	/* remove all children feature devices */
	dfl_fpga_feature_devs_remove(drvdata->cdev);
	cci_pci_free_irq(pcidev);
}

static int *cci_pci_create_irq_table(struct pci_dev *pcidev, unsigned int nvec)
{
	unsigned int i;
	int *table;

	table = kcalloc(nvec, sizeof(int), GFP_KERNEL);
	if (!table)
		return table;

	for (i = 0; i < nvec; i++)
		table[i] = pci_irq_vector(pcidev, i);

	return table;
}

static int find_dfls_by_vsec(struct pci_dev *pcidev, struct dfl_fpga_enum_info *info)
{
	u32 bir, offset, dfl_cnt, dfl_res;
	int dfl_res_off, i, bars, voff;
	resource_size_t start, len;

	voff = pci_find_vsec_capability(pcidev, PCI_VENDOR_ID_INTEL,
					PCI_VSEC_ID_INTEL_DFLS);
	if (!voff) {
		dev_dbg(&pcidev->dev, "%s no DFL VSEC found\n", __func__);
		return -ENODEV;
	}

	dfl_cnt = 0;
	pci_read_config_dword(pcidev, voff + PCI_VNDR_DFLS_CNT, &dfl_cnt);
	if (dfl_cnt > PCI_STD_NUM_BARS) {
		dev_err(&pcidev->dev, "%s too many DFLs %d > %d\n",
			__func__, dfl_cnt, PCI_STD_NUM_BARS);
		return -EINVAL;
	}

	dfl_res_off = voff + PCI_VNDR_DFLS_RES;
	if (dfl_res_off + (dfl_cnt * sizeof(u32)) > PCI_CFG_SPACE_EXP_SIZE) {
		dev_err(&pcidev->dev, "%s DFL VSEC too big for PCIe config space\n",
			__func__);
		return -EINVAL;
	}

	for (i = 0, bars = 0; i < dfl_cnt; i++, dfl_res_off += sizeof(u32)) {
		dfl_res = GENMASK(31, 0);
		pci_read_config_dword(pcidev, dfl_res_off, &dfl_res);

		bir = dfl_res & PCI_VNDR_DFLS_RES_BAR_MASK;
		if (bir >= PCI_STD_NUM_BARS) {
			dev_err(&pcidev->dev, "%s bad bir number %d\n",
				__func__, bir);
			return -EINVAL;
		}

		if (bars & BIT(bir)) {
			dev_err(&pcidev->dev, "%s DFL for BAR %d already specified\n",
				__func__, bir);
			return -EINVAL;
		}

		bars |= BIT(bir);

		len = pci_resource_len(pcidev, bir);
		offset = dfl_res & PCI_VNDR_DFLS_RES_OFF_MASK;
		if (offset >= len) {
			dev_err(&pcidev->dev, "%s bad offset %u >= %pa\n",
				__func__, offset, &len);
			return -EINVAL;
		}

		dev_dbg(&pcidev->dev, "%s BAR %d offset 0x%x\n", __func__, bir, offset);

		len -= offset;

		start = pci_resource_start(pcidev, bir) + offset;

		dfl_fpga_enum_info_add_dfl(info, start, len);
	}

	return 0;
}

/* default method of finding dfls starting at offset 0 of bar 0 */
static int find_dfls_by_default(struct pci_dev *pcidev,
				struct dfl_fpga_enum_info *info)
{
	int port_num, bar, i, ret = 0;
	resource_size_t start, len;
	void __iomem *base;
	u32 offset;
	u64 v;

	/* start to find Device Feature List from Bar 0 */
	base = pcim_iomap_region(pcidev, 0, DRV_NAME);
	if (IS_ERR(base))
		return PTR_ERR(base);

	/*
	 * PF device has FME and Ports/AFUs, and VF device only has one
	 * Port/AFU. Check them and add related "Device Feature List" info
	 * for the next step enumeration.
	 */
	if (dfl_feature_is_fme(base)) {
		start = pci_resource_start(pcidev, 0);
		len = pci_resource_len(pcidev, 0);

		dfl_fpga_enum_info_add_dfl(info, start, len);

		/*
		 * find more Device Feature Lists (e.g. Ports) per information
		 * indicated by FME module.
		 */
		v = readq(base + FME_HDR_CAP);
		port_num = FIELD_GET(FME_CAP_NUM_PORTS, v);

		WARN_ON(port_num > MAX_DFL_FPGA_PORT_NUM);

		for (i = 0; i < port_num; i++) {
			v = readq(base + FME_HDR_PORT_OFST(i));

			/* skip ports which are not implemented. */
			if (!(v & FME_PORT_OFST_IMP))
				continue;

			/*
			 * add Port's Device Feature List information for next
			 * step enumeration.
			 */
			bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
			offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
			if (bar == FME_PORT_OFST_BAR_SKIP) {
				continue;
			} else if (bar >= PCI_STD_NUM_BARS) {
				dev_err(&pcidev->dev, "bad BAR %d for port %d\n",
					bar, i);
				ret = -EINVAL;
				break;
			}

			start = pci_resource_start(pcidev, bar) + offset;
			len = pci_resource_len(pcidev, bar) - offset;

			dfl_fpga_enum_info_add_dfl(info, start, len);
		}
	} else if (dfl_feature_is_port(base)) {
		start = pci_resource_start(pcidev, 0);
		len = pci_resource_len(pcidev, 0);

		dfl_fpga_enum_info_add_dfl(info, start, len);
	} else {
		ret = -ENODEV;
	}

	/* release I/O mappings for next step enumeration */
	pcim_iounmap_region(pcidev, 0);

	return ret;
}

/* enumerate feature devices under pci device */
static int cci_enumerate_feature_devs(struct pci_dev *pcidev)
{
	struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
	struct dfl_fpga_enum_info *info;
	struct dfl_fpga_cdev *cdev;
	int nvec, ret = 0;
	int *irq_table;

	/* allocate enumeration info via pci_dev */
	info = dfl_fpga_enum_info_alloc(&pcidev->dev);
	if (!info)
		return -ENOMEM;

	/* add irq info for enumeration if the device support irq */
	nvec = cci_pci_alloc_irq(pcidev);
	if (nvec < 0) {
		dev_err(&pcidev->dev, "Fail to alloc irq %d.\n", nvec);
		ret = nvec;
		goto enum_info_free_exit;
	} else if (nvec) {
		irq_table = cci_pci_create_irq_table(pcidev, nvec);
		if (!irq_table) {
			ret = -ENOMEM;
			goto irq_free_exit;
		}

		ret = dfl_fpga_enum_info_add_irq(info, nvec, irq_table);
		kfree(irq_table);
		if (ret)
			goto irq_free_exit;
	}

	ret = find_dfls_by_vsec(pcidev, info);
	if (ret == -ENODEV)
		ret = find_dfls_by_default(pcidev, info);

	if (ret)
		goto irq_free_exit;

	/* start enumeration with prepared enumeration information */
	cdev = dfl_fpga_feature_devs_enumerate(info);
	if (IS_ERR(cdev)) {
		dev_err(&pcidev->dev, "Enumeration failure\n");
		ret = PTR_ERR(cdev);
		goto irq_free_exit;
	}

	drvdata->cdev = cdev;

irq_free_exit:
	if (ret)
		cci_pci_free_irq(pcidev);
enum_info_free_exit:
	dfl_fpga_enum_info_free(info);

	return ret;
}

static
int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid)
{
	int ret;

	ret = pcim_enable_device(pcidev);
	if (ret < 0) {
		dev_err(&pcidev->dev, "Failed to enable device %d.\n", ret);
		return ret;
	}

	pci_set_master(pcidev);

	ret = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(64));
	if (ret)
		ret = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32));
	if (ret) {
		dev_err(&pcidev->dev, "No suitable DMA support available.\n");
		return ret;
	}

	ret = cci_init_drvdata(pcidev);
	if (ret) {
		dev_err(&pcidev->dev, "Fail to init drvdata %d.\n", ret);
		return ret;
	}

	ret = cci_enumerate_feature_devs(pcidev);
	if (ret) {
		dev_err(&pcidev->dev, "enumeration failure %d.\n", ret);
		return ret;
	}

	return 0;
}

static int cci_pci_sriov_configure(struct pci_dev *pcidev, int num_vfs)
{
	struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
	struct dfl_fpga_cdev *cdev = drvdata->cdev;

	if (!num_vfs) {
		/*
		 * disable SRIOV and then put released ports back to default
		 * PF access mode.
		 */
		pci_disable_sriov(pcidev);

		dfl_fpga_cdev_config_ports_pf(cdev);

	} else {
		int ret;

		/*
		 * before enable SRIOV, put released ports into VF access mode
		 * first of all.
		 */
		ret = dfl_fpga_cdev_config_ports_vf(cdev, num_vfs);
		if (ret)
			return ret;

		ret = pci_enable_sriov(pcidev, num_vfs);
		if (ret) {
			dfl_fpga_cdev_config_ports_pf(cdev);
			return ret;
		}
	}

	return num_vfs;
}

static void cci_pci_remove(struct pci_dev *pcidev)
{
	if (dev_is_pf(&pcidev->dev))
		cci_pci_sriov_configure(pcidev, 0);

	cci_remove_feature_devs(pcidev);
}

static struct pci_driver cci_pci_driver = {
	.name = DRV_NAME,
	.id_table = cci_pcie_id_tbl,
	.probe = cci_pci_probe,
	.remove = cci_pci_remove,
	.sriov_configure = cci_pci_sriov_configure,
};

module_pci_driver(cci_pci_driver);

MODULE_DESCRIPTION("FPGA DFL PCIe Device Driver");
MODULE_AUTHOR("Intel Corporation");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
72ddd9f3 ZY	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Driver for FPGA Device Feature List (DFL) PCIe device
	4	*
	5	* Copyright (C) 2017-2018 Intel Corporation, Inc.
	6	*
	7	* Authors:
	8	* Zhang Yi <Yi.Z.Zhang@intel.com>
	9	* Xiao Guangrong <guangrong.xiao@linux.intel.com>
	10	* Joseph Grecco <joe.grecco@intel.com>
	11	* Enno Luebbers <enno.luebbers@intel.com>
	12	* Tim Whisonant <tim.whisonant@intel.com>
	13	* Ananda Ravuri <ananda.ravuri@intel.com>
	14	* Henry Mitchel <henry.mitchel@intel.com>
	15	*/
	16
	17	#include <linux/pci.h>
21f0a239	18	#include <linux/dma-mapping.h>
72ddd9f3 ZY	19	#include <linux/types.h>
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/stddef.h>
	23	#include <linux/errno.h>
72ddd9f3	24
968b8199 WH	25	#include "dfl.h"
968b8199 WH	26
72ddd9f3 ZY	27	#define DRV_VERSION "0.8"
	28	#define DRV_NAME "dfl-pci"
	29
fa41d105 MG	30	#define PCI_VSEC_ID_INTEL_DFLS 0x43
	31
	32	#define PCI_VNDR_DFLS_CNT 0x8
	33	#define PCI_VNDR_DFLS_RES 0xc
	34
	35	#define PCI_VNDR_DFLS_RES_BAR_MASK GENMASK(2, 0)
	36	#define PCI_VNDR_DFLS_RES_OFF_MASK GENMASK(31, 3)
	37
968b8199 WH	38	struct cci_drvdata {
	39	struct dfl_fpga_cdev cdev; / container device */
	40	};
	41
bfef946d XY	42	static int cci_pci_alloc_irq(struct pci_dev *pcidev)
	43	{
	44	int ret, nvec = pci_msix_vec_count(pcidev);
	45
	46	if (nvec <= 0) {
	47	dev_dbg(&pcidev->dev, "fpga interrupt not supported\n");
	48	return 0;
	49	}
	50
	51	ret = pci_alloc_irq_vectors(pcidev, nvec, nvec, PCI_IRQ_MSIX);
	52	if (ret < 0)
	53	return ret;
	54
	55	return nvec;
	56	}
	57
	58	static void cci_pci_free_irq(struct pci_dev *pcidev)
	59	{
	60	pci_free_irq_vectors(pcidev);
	61	}
	62
72ddd9f3	63	/* PCI Device ID */
a78a51a8 RW	64	#define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
	65	#define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
	66	#define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
	67	#define PCIE_DEVICE_ID_INTEL_PAC_N3000 0x0B30
	68	#define PCIE_DEVICE_ID_INTEL_PAC_D5005 0x0B2B
82fb70b8 MH	69	#define PCIE_DEVICE_ID_SILICOM_PAC_N5010 0x1000
82fb70b8 MH	70	#define PCIE_DEVICE_ID_SILICOM_PAC_N5011 0x1001
65f5c010 MG	71	#define PCIE_DEVICE_ID_INTEL_DFL 0xbcce
65f5c010 MG	72	/* PCI Subdevice ID for PCIE_DEVICE_ID_INTEL_DFL */
bb1dbece	73	#define PCIE_SUBDEVICE_ID_INTEL_D5005 0x138d
65f5c010 MG	74	#define PCIE_SUBDEVICE_ID_INTEL_N6000 0x1770
	75	#define PCIE_SUBDEVICE_ID_INTEL_N6001 0x1771
	76	#define PCIE_SUBDEVICE_ID_INTEL_C6100 0x17d4
82fb70b8	77
72ddd9f3	78	/* VF Device */
a78a51a8 RW	79	#define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
	80	#define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
	81	#define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
	82	#define PCIE_DEVICE_ID_INTEL_PAC_D5005_VF 0x0B2C
65f5c010	83	#define PCIE_DEVICE_ID_INTEL_DFL_VF 0xbccf
72ddd9f3 ZY	84
	85	static struct pci_device_id cci_pcie_id_tbl[] = {
	86	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),},
	87	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X),},
	88	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X),},
	89	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X),},
	90	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),},
	91	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),},
eacfbf58	92	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_N3000),},
a78a51a8 RW	93	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005),},
a78a51a8 RW	94	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005_VF),},
82fb70b8 MH	95	{PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5010),},
82fb70b8 MH	96	{PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5011),},
bb1dbece PC	97	{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL,
bb1dbece PC	98	PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_D5005),},
65f5c010 MG	99	{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL,
	100	PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_N6000),},
	101	{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL_VF,
	102	PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_N6000),},
	103	{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL,
	104	PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_N6001),},
	105	{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL_VF,
	106	PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_N6001),},
	107	{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL,
	108	PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_C6100),},
	109	{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL_VF,
	110	PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_C6100),},
72ddd9f3 ZY	111	{0,}
	112	};
	113	MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);
	114
968b8199 WH	115	static int cci_init_drvdata(struct pci_dev *pcidev)
	116	{
	117	struct cci_drvdata *drvdata;
	118
	119	drvdata = devm_kzalloc(&pcidev->dev, sizeof(*drvdata), GFP_KERNEL);
	120	if (!drvdata)
	121	return -ENOMEM;
	122
	123	pci_set_drvdata(pcidev, drvdata);
	124
	125	return 0;
	126	}
	127
	128	static void cci_remove_feature_devs(struct pci_dev *pcidev)
	129	{
	130	struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
	131
	132	/* remove all children feature devices */
	133	dfl_fpga_feature_devs_remove(drvdata->cdev);
bfef946d XY	134	cci_pci_free_irq(pcidev);
	135	}
	136
	137	static int cci_pci_create_irq_table(struct pci_dev pcidev, unsigned int nvec)
	138	{
	139	unsigned int i;
	140	int *table;
	141
	142	table = kcalloc(nvec, sizeof(int), GFP_KERNEL);
	143	if (!table)
	144	return table;
	145
	146	for (i = 0; i < nvec; i++)
	147	table[i] = pci_irq_vector(pcidev, i);
	148
	149	return table;
968b8199 WH	150	}
968b8199 WH	151
fa41d105 MG	152	static int find_dfls_by_vsec(struct pci_dev pcidev, struct dfl_fpga_enum_info info)
fa41d105 MG	153	{
8607d9c1 XW	154	u32 bir, offset, dfl_cnt, dfl_res;
8607d9c1 XW	155	int dfl_res_off, i, bars, voff;
fa41d105 MG	156	resource_size_t start, len;
fa41d105 MG	157
8607d9c1 XW	158	voff = pci_find_vsec_capability(pcidev, PCI_VENDOR_ID_INTEL,
8607d9c1 XW	159	PCI_VSEC_ID_INTEL_DFLS);
fa41d105 MG	160	if (!voff) {
	161	dev_dbg(&pcidev->dev, "%s no DFL VSEC found\n", __func__);
	162	return -ENODEV;
	163	}
	164
	165	dfl_cnt = 0;
	166	pci_read_config_dword(pcidev, voff + PCI_VNDR_DFLS_CNT, &dfl_cnt);
	167	if (dfl_cnt > PCI_STD_NUM_BARS) {
	168	dev_err(&pcidev->dev, "%s too many DFLs %d > %d\n",
	169	__func__, dfl_cnt, PCI_STD_NUM_BARS);
	170	return -EINVAL;
	171	}
	172
	173	dfl_res_off = voff + PCI_VNDR_DFLS_RES;
	174	if (dfl_res_off + (dfl_cnt * sizeof(u32)) > PCI_CFG_SPACE_EXP_SIZE) {
	175	dev_err(&pcidev->dev, "%s DFL VSEC too big for PCIe config space\n",
	176	__func__);
	177	return -EINVAL;
	178	}
	179
	180	for (i = 0, bars = 0; i < dfl_cnt; i++, dfl_res_off += sizeof(u32)) {
	181	dfl_res = GENMASK(31, 0);
	182	pci_read_config_dword(pcidev, dfl_res_off, &dfl_res);
	183
	184	bir = dfl_res & PCI_VNDR_DFLS_RES_BAR_MASK;
	185	if (bir >= PCI_STD_NUM_BARS) {
	186	dev_err(&pcidev->dev, "%s bad bir number %d\n",
	187	__func__, bir);
	188	return -EINVAL;
	189	}
	190
	191	if (bars & BIT(bir)) {
	192	dev_err(&pcidev->dev, "%s DFL for BAR %d already specified\n",
	193	__func__, bir);
	194	return -EINVAL;
	195	}
	196
	197	bars \|= BIT(bir);
	198
	199	len = pci_resource_len(pcidev, bir);
	200	offset = dfl_res & PCI_VNDR_DFLS_RES_OFF_MASK;
	201	if (offset >= len) {
	202	dev_err(&pcidev->dev, "%s bad offset %u >= %pa\n",
	203	__func__, offset, &len);
	204	return -EINVAL;
	205	}
	206
	207	dev_dbg(&pcidev->dev, "%s BAR %d offset 0x%x\n", __func__, bir, offset);
	208
	209	len -= offset;
	210
	211	start = pci_resource_start(pcidev, bir) + offset;
	212
	213	dfl_fpga_enum_info_add_dfl(info, start, len);
	214	}
	215
	216	return 0;
	217	}
	218
3e265f83 MG	219	/* default method of finding dfls starting at offset 0 of bar 0 */
	220	static int find_dfls_by_default(struct pci_dev *pcidev,
	221	struct dfl_fpga_enum_info *info)
968b8199	222	{
3e265f83	223	int port_num, bar, i, ret = 0;
968b8199	224	resource_size_t start, len;
968b8199 WH	225	void __iomem *base;
	226	u32 offset;
	227	u64 v;
	228
3e265f83	229	/* start to find Device Feature List from Bar 0 */
43657924 PS	230	base = pcim_iomap_region(pcidev, 0, DRV_NAME);
	231	if (IS_ERR(base))
	232	return PTR_ERR(base);
968b8199 WH	233
	234	/*
	235	* PF device has FME and Ports/AFUs, and VF device only has one
	236	* Port/AFU. Check them and add related "Device Feature List" info
	237	* for the next step enumeration.
	238	*/
	239	if (dfl_feature_is_fme(base)) {
	240	start = pci_resource_start(pcidev, 0);
	241	len = pci_resource_len(pcidev, 0);
	242
89eb35e8	243	dfl_fpga_enum_info_add_dfl(info, start, len);
968b8199 WH	244
	245	/*
	246	* find more Device Feature Lists (e.g. Ports) per information
	247	* indicated by FME module.
	248	*/
	249	v = readq(base + FME_HDR_CAP);
	250	port_num = FIELD_GET(FME_CAP_NUM_PORTS, v);
	251
	252	WARN_ON(port_num > MAX_DFL_FPGA_PORT_NUM);
	253
	254	for (i = 0; i < port_num; i++) {
	255	v = readq(base + FME_HDR_PORT_OFST(i));
	256
	257	/* skip ports which are not implemented. */
	258	if (!(v & FME_PORT_OFST_IMP))
	259	continue;
	260
	261	/*
	262	* add Port's Device Feature List information for next
	263	* step enumeration.
	264	*/
	265	bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
	266	offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
ae23f746 MG	267	if (bar == FME_PORT_OFST_BAR_SKIP) {
	268	continue;
	269	} else if (bar >= PCI_STD_NUM_BARS) {
	270	dev_err(&pcidev->dev, "bad BAR %d for port %d\n",
	271	bar, i);
	272	ret = -EINVAL;
	273	break;
	274	}
	275
968b8199 WH	276	start = pci_resource_start(pcidev, bar) + offset;
	277	len = pci_resource_len(pcidev, bar) - offset;
	278
89eb35e8	279	dfl_fpga_enum_info_add_dfl(info, start, len);
968b8199 WH	280	}
	281	} else if (dfl_feature_is_port(base)) {
	282	start = pci_resource_start(pcidev, 0);
	283	len = pci_resource_len(pcidev, 0);
	284
89eb35e8	285	dfl_fpga_enum_info_add_dfl(info, start, len);
968b8199 WH	286	} else {
968b8199 WH	287	ret = -ENODEV;
968b8199 WH	288	}
968b8199 WH	289
89eb35e8	290	/* release I/O mappings for next step enumeration */
43657924	291	pcim_iounmap_region(pcidev, 0);
89eb35e8	292
3e265f83 MG	293	return ret;
	294	}
	295
	296	/* enumerate feature devices under pci device */
	297	static int cci_enumerate_feature_devs(struct pci_dev *pcidev)
	298	{
	299	struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
	300	struct dfl_fpga_enum_info *info;
	301	struct dfl_fpga_cdev *cdev;
	302	int nvec, ret = 0;
	303	int *irq_table;
	304
	305	/* allocate enumeration info via pci_dev */
	306	info = dfl_fpga_enum_info_alloc(&pcidev->dev);
	307	if (!info)
	308	return -ENOMEM;
	309
	310	/* add irq info for enumeration if the device support irq */
	311	nvec = cci_pci_alloc_irq(pcidev);
	312	if (nvec < 0) {
	313	dev_err(&pcidev->dev, "Fail to alloc irq %d.\n", nvec);
	314	ret = nvec;
	315	goto enum_info_free_exit;
	316	} else if (nvec) {
	317	irq_table = cci_pci_create_irq_table(pcidev, nvec);
	318	if (!irq_table) {
	319	ret = -ENOMEM;
	320	goto irq_free_exit;
	321	}
	322
	323	ret = dfl_fpga_enum_info_add_irq(info, nvec, irq_table);
	324	kfree(irq_table);
	325	if (ret)
	326	goto irq_free_exit;
	327	}
	328
fa41d105 MG	329	ret = find_dfls_by_vsec(pcidev, info);
	330	if (ret == -ENODEV)
	331	ret = find_dfls_by_default(pcidev, info);
	332
3e265f83 MG	333	if (ret)
	334	goto irq_free_exit;
	335
968b8199 WH	336	/* start enumeration with prepared enumeration information */
	337	cdev = dfl_fpga_feature_devs_enumerate(info);
	338	if (IS_ERR(cdev)) {
	339	dev_err(&pcidev->dev, "Enumeration failure\n");
	340	ret = PTR_ERR(cdev);
bfef946d	341	goto irq_free_exit;
968b8199 WH	342	}
	343
	344	drvdata->cdev = cdev;
	345
bfef946d XY	346	irq_free_exit:
	347	if (ret)
	348	cci_pci_free_irq(pcidev);
968b8199 WH	349	enum_info_free_exit:
	350	dfl_fpga_enum_info_free(info);
	351
	352	return ret;
	353	}
	354
72ddd9f3 ZY	355	static
	356	int cci_pci_probe(struct pci_dev pcidev, const struct pci_device_id pcidevid)
	357	{
	358	int ret;
	359
	360	ret = pcim_enable_device(pcidev);
	361	if (ret < 0) {
	362	dev_err(&pcidev->dev, "Failed to enable device %d.\n", ret);
	363	return ret;
	364	}
	365
72ddd9f3 ZY	366	pci_set_master(pcidev);
72ddd9f3 ZY	367
21f0a239 CJ	368	ret = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(64));
	369	if (ret)
	370	ret = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32));
	371	if (ret) {
72ddd9f3	372	dev_err(&pcidev->dev, "No suitable DMA support available.\n");
83a458e3	373	return ret;
72ddd9f3 ZY	374	}
72ddd9f3 ZY	375
968b8199 WH	376	ret = cci_init_drvdata(pcidev);
	377	if (ret) {
	378	dev_err(&pcidev->dev, "Fail to init drvdata %d.\n", ret);
83a458e3	379	return ret;
968b8199 WH	380	}
	381
	382	ret = cci_enumerate_feature_devs(pcidev);
83a458e3 BH	383	if (ret) {
83a458e3 BH	384	dev_err(&pcidev->dev, "enumeration failure %d.\n", ret);
bfef946d	385	return ret;
83a458e3	386	}
968b8199	387
83a458e3	388	return 0;
72ddd9f3 ZY	389	}
72ddd9f3 ZY	390
bdd4f307 WH	391	static int cci_pci_sriov_configure(struct pci_dev *pcidev, int num_vfs)
	392	{
	393	struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
	394	struct dfl_fpga_cdev *cdev = drvdata->cdev;
bdd4f307 WH	395
	396	if (!num_vfs) {
	397	/*
	398	* disable SRIOV and then put released ports back to default
	399	* PF access mode.
	400	*/
	401	pci_disable_sriov(pcidev);
	402
	403	dfl_fpga_cdev_config_ports_pf(cdev);
	404
	405	} else {
e19485dc XY	406	int ret;
e19485dc XY	407
bdd4f307 WH	408	/*
	409	* before enable SRIOV, put released ports into VF access mode
	410	* first of all.
	411	*/
	412	ret = dfl_fpga_cdev_config_ports_vf(cdev, num_vfs);
	413	if (ret)
	414	return ret;
	415
	416	ret = pci_enable_sriov(pcidev, num_vfs);
3c2760b7	417	if (ret) {
bdd4f307	418	dfl_fpga_cdev_config_ports_pf(cdev);
3c2760b7 XY	419	return ret;
3c2760b7 XY	420	}
bdd4f307 WH	421	}
bdd4f307 WH	422
3c2760b7	423	return num_vfs;
bdd4f307 WH	424	}
bdd4f307 WH	425
72ddd9f3 ZY	426	static void cci_pci_remove(struct pci_dev *pcidev)
72ddd9f3 ZY	427	{
bdd4f307 WH	428	if (dev_is_pf(&pcidev->dev))
	429	cci_pci_sriov_configure(pcidev, 0);
	430
968b8199	431	cci_remove_feature_devs(pcidev);
72ddd9f3 ZY	432	}
	433
	434	static struct pci_driver cci_pci_driver = {
	435	.name = DRV_NAME,
	436	.id_table = cci_pcie_id_tbl,
	437	.probe = cci_pci_probe,
	438	.remove = cci_pci_remove,
bdd4f307	439	.sriov_configure = cci_pci_sriov_configure,
72ddd9f3 ZY	440	};
	441
	442	module_pci_driver(cci_pci_driver);
	443
	444	MODULE_DESCRIPTION("FPGA DFL PCIe Device Driver");
	445	MODULE_AUTHOR("Intel Corporation");
	446	MODULE_LICENSE("GPL v2");